1*4882a593Smuzhiyun /* SPDX-License-Identifier: MIT */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (C) 2017 Google, Inc. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Authors: 6*4882a593Smuzhiyun * Sean Paul <seanpaul@chromium.org> 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef _DRM_HDCP_H_INCLUDED_ 10*4882a593Smuzhiyun #define _DRM_HDCP_H_INCLUDED_ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #include <linux/types.h> 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun /* Period of hdcp checks (to ensure we're still authenticated) */ 15*4882a593Smuzhiyun #define DRM_HDCP_CHECK_PERIOD_MS (128 * 16) 16*4882a593Smuzhiyun #define DRM_HDCP2_CHECK_PERIOD_MS 500 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun /* Shared lengths/masks between HDMI/DVI/DisplayPort */ 19*4882a593Smuzhiyun #define DRM_HDCP_AN_LEN 8 20*4882a593Smuzhiyun #define DRM_HDCP_BSTATUS_LEN 2 21*4882a593Smuzhiyun #define DRM_HDCP_KSV_LEN 5 22*4882a593Smuzhiyun #define DRM_HDCP_RI_LEN 2 23*4882a593Smuzhiyun #define DRM_HDCP_V_PRIME_PART_LEN 4 24*4882a593Smuzhiyun #define DRM_HDCP_V_PRIME_NUM_PARTS 5 25*4882a593Smuzhiyun #define DRM_HDCP_NUM_DOWNSTREAM(x) (x & 0x7f) 26*4882a593Smuzhiyun #define DRM_HDCP_MAX_CASCADE_EXCEEDED(x) (x & BIT(3)) 27*4882a593Smuzhiyun #define DRM_HDCP_MAX_DEVICE_EXCEEDED(x) (x & BIT(7)) 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun /* Slave address for the HDCP registers in the receiver */ 30*4882a593Smuzhiyun #define DRM_HDCP_DDC_ADDR 0x3A 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun /* Value to use at the end of the SHA-1 bytestream used for repeaters */ 33*4882a593Smuzhiyun #define DRM_HDCP_SHA1_TERMINATOR 0x80 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun /* HDCP register offsets for HDMI/DVI devices */ 36*4882a593Smuzhiyun #define DRM_HDCP_DDC_BKSV 0x00 37*4882a593Smuzhiyun #define DRM_HDCP_DDC_RI_PRIME 0x08 38*4882a593Smuzhiyun #define DRM_HDCP_DDC_AKSV 0x10 39*4882a593Smuzhiyun #define DRM_HDCP_DDC_AN 0x18 40*4882a593Smuzhiyun #define DRM_HDCP_DDC_V_PRIME(h) (0x20 + h * 4) 41*4882a593Smuzhiyun #define DRM_HDCP_DDC_BCAPS 0x40 42*4882a593Smuzhiyun #define DRM_HDCP_DDC_BCAPS_REPEATER_PRESENT BIT(6) 43*4882a593Smuzhiyun #define DRM_HDCP_DDC_BCAPS_KSV_FIFO_READY BIT(5) 44*4882a593Smuzhiyun #define DRM_HDCP_DDC_BSTATUS 0x41 45*4882a593Smuzhiyun #define DRM_HDCP_DDC_KSV_FIFO 0x43 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun #define DRM_HDCP_1_4_SRM_ID 0x8 48*4882a593Smuzhiyun #define DRM_HDCP_1_4_VRL_LENGTH_SIZE 3 49*4882a593Smuzhiyun #define DRM_HDCP_1_4_DCP_SIG_SIZE 40 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun /* Protocol message definition for HDCP2.2 specification */ 52*4882a593Smuzhiyun /* 53*4882a593Smuzhiyun * Protected content streams are classified into 2 types: 54*4882a593Smuzhiyun * - Type0: Can be transmitted with HDCP 1.4+ 55*4882a593Smuzhiyun * - Type1: Can be transmitted with HDCP 2.2+ 56*4882a593Smuzhiyun */ 57*4882a593Smuzhiyun #define HDCP_STREAM_TYPE0 0x00 58*4882a593Smuzhiyun #define HDCP_STREAM_TYPE1 0x01 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun /* HDCP2.2 Msg IDs */ 61*4882a593Smuzhiyun #define HDCP_2_2_NULL_MSG 1 62*4882a593Smuzhiyun #define HDCP_2_2_AKE_INIT 2 63*4882a593Smuzhiyun #define HDCP_2_2_AKE_SEND_CERT 3 64*4882a593Smuzhiyun #define HDCP_2_2_AKE_NO_STORED_KM 4 65*4882a593Smuzhiyun #define HDCP_2_2_AKE_STORED_KM 5 66*4882a593Smuzhiyun #define HDCP_2_2_AKE_SEND_HPRIME 7 67*4882a593Smuzhiyun #define HDCP_2_2_AKE_SEND_PAIRING_INFO 8 68*4882a593Smuzhiyun #define HDCP_2_2_LC_INIT 9 69*4882a593Smuzhiyun #define HDCP_2_2_LC_SEND_LPRIME 10 70*4882a593Smuzhiyun #define HDCP_2_2_SKE_SEND_EKS 11 71*4882a593Smuzhiyun #define HDCP_2_2_REP_SEND_RECVID_LIST 12 72*4882a593Smuzhiyun #define HDCP_2_2_REP_SEND_ACK 15 73*4882a593Smuzhiyun #define HDCP_2_2_REP_STREAM_MANAGE 16 74*4882a593Smuzhiyun #define HDCP_2_2_REP_STREAM_READY 17 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun #define HDCP_2_2_RTX_LEN 8 77*4882a593Smuzhiyun #define HDCP_2_2_RRX_LEN 8 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun #define HDCP_2_2_K_PUB_RX_MOD_N_LEN 128 80*4882a593Smuzhiyun #define HDCP_2_2_K_PUB_RX_EXP_E_LEN 3 81*4882a593Smuzhiyun #define HDCP_2_2_K_PUB_RX_LEN (HDCP_2_2_K_PUB_RX_MOD_N_LEN + \ 82*4882a593Smuzhiyun HDCP_2_2_K_PUB_RX_EXP_E_LEN) 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun #define HDCP_2_2_DCP_LLC_SIG_LEN 384 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun #define HDCP_2_2_E_KPUB_KM_LEN 128 87*4882a593Smuzhiyun #define HDCP_2_2_E_KH_KM_M_LEN (16 + 16) 88*4882a593Smuzhiyun #define HDCP_2_2_H_PRIME_LEN 32 89*4882a593Smuzhiyun #define HDCP_2_2_E_KH_KM_LEN 16 90*4882a593Smuzhiyun #define HDCP_2_2_RN_LEN 8 91*4882a593Smuzhiyun #define HDCP_2_2_L_PRIME_LEN 32 92*4882a593Smuzhiyun #define HDCP_2_2_E_DKEY_KS_LEN 16 93*4882a593Smuzhiyun #define HDCP_2_2_RIV_LEN 8 94*4882a593Smuzhiyun #define HDCP_2_2_SEQ_NUM_LEN 3 95*4882a593Smuzhiyun #define HDCP_2_2_V_PRIME_HALF_LEN (HDCP_2_2_L_PRIME_LEN / 2) 96*4882a593Smuzhiyun #define HDCP_2_2_RECEIVER_ID_LEN DRM_HDCP_KSV_LEN 97*4882a593Smuzhiyun #define HDCP_2_2_MAX_DEVICE_COUNT 31 98*4882a593Smuzhiyun #define HDCP_2_2_RECEIVER_IDS_MAX_LEN (HDCP_2_2_RECEIVER_ID_LEN * \ 99*4882a593Smuzhiyun HDCP_2_2_MAX_DEVICE_COUNT) 100*4882a593Smuzhiyun #define HDCP_2_2_MPRIME_LEN 32 101*4882a593Smuzhiyun 102*4882a593Smuzhiyun /* Following Macros take a byte at a time for bit(s) masking */ 103*4882a593Smuzhiyun /* 104*4882a593Smuzhiyun * TODO: This has to be changed for DP MST, as multiple stream on 105*4882a593Smuzhiyun * same port is possible. 106*4882a593Smuzhiyun * For HDCP2.2 on HDMI and DP SST this value is always 1. 107*4882a593Smuzhiyun */ 108*4882a593Smuzhiyun #define HDCP_2_2_MAX_CONTENT_STREAMS_CNT 1 109*4882a593Smuzhiyun #define HDCP_2_2_TXCAP_MASK_LEN 2 110*4882a593Smuzhiyun #define HDCP_2_2_RXCAPS_LEN 3 111*4882a593Smuzhiyun #define HDCP_2_2_RX_REPEATER(x) ((x) & BIT(0)) 112*4882a593Smuzhiyun #define HDCP_2_2_DP_HDCP_CAPABLE(x) ((x) & BIT(1)) 113*4882a593Smuzhiyun #define HDCP_2_2_RXINFO_LEN 2 114*4882a593Smuzhiyun 115*4882a593Smuzhiyun /* HDCP1.x compliant device in downstream */ 116*4882a593Smuzhiyun #define HDCP_2_2_HDCP1_DEVICE_CONNECTED(x) ((x) & BIT(0)) 117*4882a593Smuzhiyun 118*4882a593Smuzhiyun /* HDCP2.0 Compliant repeater in downstream */ 119*4882a593Smuzhiyun #define HDCP_2_2_HDCP_2_0_REP_CONNECTED(x) ((x) & BIT(1)) 120*4882a593Smuzhiyun #define HDCP_2_2_MAX_CASCADE_EXCEEDED(x) ((x) & BIT(2)) 121*4882a593Smuzhiyun #define HDCP_2_2_MAX_DEVS_EXCEEDED(x) ((x) & BIT(3)) 122*4882a593Smuzhiyun #define HDCP_2_2_DEV_COUNT_LO(x) (((x) & (0xF << 4)) >> 4) 123*4882a593Smuzhiyun #define HDCP_2_2_DEV_COUNT_HI(x) ((x) & BIT(0)) 124*4882a593Smuzhiyun #define HDCP_2_2_DEPTH(x) (((x) & (0x7 << 1)) >> 1) 125*4882a593Smuzhiyun 126*4882a593Smuzhiyun struct hdcp2_cert_rx { 127*4882a593Smuzhiyun u8 receiver_id[HDCP_2_2_RECEIVER_ID_LEN]; 128*4882a593Smuzhiyun u8 kpub_rx[HDCP_2_2_K_PUB_RX_LEN]; 129*4882a593Smuzhiyun u8 reserved[2]; 130*4882a593Smuzhiyun u8 dcp_signature[HDCP_2_2_DCP_LLC_SIG_LEN]; 131*4882a593Smuzhiyun } __packed; 132*4882a593Smuzhiyun 133*4882a593Smuzhiyun struct hdcp2_streamid_type { 134*4882a593Smuzhiyun u8 stream_id; 135*4882a593Smuzhiyun u8 stream_type; 136*4882a593Smuzhiyun } __packed; 137*4882a593Smuzhiyun 138*4882a593Smuzhiyun /* 139*4882a593Smuzhiyun * The TxCaps field specified in the HDCP HDMI, DP specs 140*4882a593Smuzhiyun * This field is big endian as specified in the errata. 141*4882a593Smuzhiyun */ 142*4882a593Smuzhiyun struct hdcp2_tx_caps { 143*4882a593Smuzhiyun /* Transmitter must set this to 0x2 */ 144*4882a593Smuzhiyun u8 version; 145*4882a593Smuzhiyun 146*4882a593Smuzhiyun /* Reserved for HDCP and DP Spec. Read as Zero */ 147*4882a593Smuzhiyun u8 tx_cap_mask[HDCP_2_2_TXCAP_MASK_LEN]; 148*4882a593Smuzhiyun } __packed; 149*4882a593Smuzhiyun 150*4882a593Smuzhiyun /* Main structures for HDCP2.2 protocol communication */ 151*4882a593Smuzhiyun struct hdcp2_ake_init { 152*4882a593Smuzhiyun u8 msg_id; 153*4882a593Smuzhiyun u8 r_tx[HDCP_2_2_RTX_LEN]; 154*4882a593Smuzhiyun struct hdcp2_tx_caps tx_caps; 155*4882a593Smuzhiyun } __packed; 156*4882a593Smuzhiyun 157*4882a593Smuzhiyun struct hdcp2_ake_send_cert { 158*4882a593Smuzhiyun u8 msg_id; 159*4882a593Smuzhiyun struct hdcp2_cert_rx cert_rx; 160*4882a593Smuzhiyun u8 r_rx[HDCP_2_2_RRX_LEN]; 161*4882a593Smuzhiyun u8 rx_caps[HDCP_2_2_RXCAPS_LEN]; 162*4882a593Smuzhiyun } __packed; 163*4882a593Smuzhiyun 164*4882a593Smuzhiyun struct hdcp2_ake_no_stored_km { 165*4882a593Smuzhiyun u8 msg_id; 166*4882a593Smuzhiyun u8 e_kpub_km[HDCP_2_2_E_KPUB_KM_LEN]; 167*4882a593Smuzhiyun } __packed; 168*4882a593Smuzhiyun 169*4882a593Smuzhiyun struct hdcp2_ake_stored_km { 170*4882a593Smuzhiyun u8 msg_id; 171*4882a593Smuzhiyun u8 e_kh_km_m[HDCP_2_2_E_KH_KM_M_LEN]; 172*4882a593Smuzhiyun } __packed; 173*4882a593Smuzhiyun 174*4882a593Smuzhiyun struct hdcp2_ake_send_hprime { 175*4882a593Smuzhiyun u8 msg_id; 176*4882a593Smuzhiyun u8 h_prime[HDCP_2_2_H_PRIME_LEN]; 177*4882a593Smuzhiyun } __packed; 178*4882a593Smuzhiyun 179*4882a593Smuzhiyun struct hdcp2_ake_send_pairing_info { 180*4882a593Smuzhiyun u8 msg_id; 181*4882a593Smuzhiyun u8 e_kh_km[HDCP_2_2_E_KH_KM_LEN]; 182*4882a593Smuzhiyun } __packed; 183*4882a593Smuzhiyun 184*4882a593Smuzhiyun struct hdcp2_lc_init { 185*4882a593Smuzhiyun u8 msg_id; 186*4882a593Smuzhiyun u8 r_n[HDCP_2_2_RN_LEN]; 187*4882a593Smuzhiyun } __packed; 188*4882a593Smuzhiyun 189*4882a593Smuzhiyun struct hdcp2_lc_send_lprime { 190*4882a593Smuzhiyun u8 msg_id; 191*4882a593Smuzhiyun u8 l_prime[HDCP_2_2_L_PRIME_LEN]; 192*4882a593Smuzhiyun } __packed; 193*4882a593Smuzhiyun 194*4882a593Smuzhiyun struct hdcp2_ske_send_eks { 195*4882a593Smuzhiyun u8 msg_id; 196*4882a593Smuzhiyun u8 e_dkey_ks[HDCP_2_2_E_DKEY_KS_LEN]; 197*4882a593Smuzhiyun u8 riv[HDCP_2_2_RIV_LEN]; 198*4882a593Smuzhiyun } __packed; 199*4882a593Smuzhiyun 200*4882a593Smuzhiyun struct hdcp2_rep_send_receiverid_list { 201*4882a593Smuzhiyun u8 msg_id; 202*4882a593Smuzhiyun u8 rx_info[HDCP_2_2_RXINFO_LEN]; 203*4882a593Smuzhiyun u8 seq_num_v[HDCP_2_2_SEQ_NUM_LEN]; 204*4882a593Smuzhiyun u8 v_prime[HDCP_2_2_V_PRIME_HALF_LEN]; 205*4882a593Smuzhiyun u8 receiver_ids[HDCP_2_2_RECEIVER_IDS_MAX_LEN]; 206*4882a593Smuzhiyun } __packed; 207*4882a593Smuzhiyun 208*4882a593Smuzhiyun struct hdcp2_rep_send_ack { 209*4882a593Smuzhiyun u8 msg_id; 210*4882a593Smuzhiyun u8 v[HDCP_2_2_V_PRIME_HALF_LEN]; 211*4882a593Smuzhiyun } __packed; 212*4882a593Smuzhiyun 213*4882a593Smuzhiyun struct hdcp2_rep_stream_manage { 214*4882a593Smuzhiyun u8 msg_id; 215*4882a593Smuzhiyun u8 seq_num_m[HDCP_2_2_SEQ_NUM_LEN]; 216*4882a593Smuzhiyun __be16 k; 217*4882a593Smuzhiyun struct hdcp2_streamid_type streams[HDCP_2_2_MAX_CONTENT_STREAMS_CNT]; 218*4882a593Smuzhiyun } __packed; 219*4882a593Smuzhiyun 220*4882a593Smuzhiyun struct hdcp2_rep_stream_ready { 221*4882a593Smuzhiyun u8 msg_id; 222*4882a593Smuzhiyun u8 m_prime[HDCP_2_2_MPRIME_LEN]; 223*4882a593Smuzhiyun } __packed; 224*4882a593Smuzhiyun 225*4882a593Smuzhiyun /* HDCP2.2 TIMEOUTs in mSec */ 226*4882a593Smuzhiyun #define HDCP_2_2_CERT_TIMEOUT_MS 100 227*4882a593Smuzhiyun #define HDCP_2_2_HPRIME_NO_PAIRED_TIMEOUT_MS 1000 228*4882a593Smuzhiyun #define HDCP_2_2_HPRIME_PAIRED_TIMEOUT_MS 200 229*4882a593Smuzhiyun #define HDCP_2_2_PAIRING_TIMEOUT_MS 200 230*4882a593Smuzhiyun #define HDCP_2_2_HDMI_LPRIME_TIMEOUT_MS 20 231*4882a593Smuzhiyun #define HDCP_2_2_DP_LPRIME_TIMEOUT_MS 7 232*4882a593Smuzhiyun #define HDCP_2_2_RECVID_LIST_TIMEOUT_MS 3000 233*4882a593Smuzhiyun #define HDCP_2_2_STREAM_READY_TIMEOUT_MS 100 234*4882a593Smuzhiyun 235*4882a593Smuzhiyun /* HDMI HDCP2.2 Register Offsets */ 236*4882a593Smuzhiyun #define HDCP_2_2_HDMI_REG_VER_OFFSET 0x50 237*4882a593Smuzhiyun #define HDCP_2_2_HDMI_REG_WR_MSG_OFFSET 0x60 238*4882a593Smuzhiyun #define HDCP_2_2_HDMI_REG_RXSTATUS_OFFSET 0x70 239*4882a593Smuzhiyun #define HDCP_2_2_HDMI_REG_RD_MSG_OFFSET 0x80 240*4882a593Smuzhiyun #define HDCP_2_2_HDMI_REG_DBG_OFFSET 0xC0 241*4882a593Smuzhiyun 242*4882a593Smuzhiyun #define HDCP_2_2_HDMI_SUPPORT_MASK BIT(2) 243*4882a593Smuzhiyun #define HDCP_2_2_RX_CAPS_VERSION_VAL 0x02 244*4882a593Smuzhiyun #define HDCP_2_2_SEQ_NUM_MAX 0xFFFFFF 245*4882a593Smuzhiyun #define HDCP_2_2_DELAY_BEFORE_ENCRYPTION_EN 200 246*4882a593Smuzhiyun 247*4882a593Smuzhiyun /* Below macros take a byte at a time and mask the bit(s) */ 248*4882a593Smuzhiyun #define HDCP_2_2_HDMI_RXSTATUS_LEN 2 249*4882a593Smuzhiyun #define HDCP_2_2_HDMI_RXSTATUS_MSG_SZ_HI(x) ((x) & 0x3) 250*4882a593Smuzhiyun #define HDCP_2_2_HDMI_RXSTATUS_READY(x) ((x) & BIT(2)) 251*4882a593Smuzhiyun #define HDCP_2_2_HDMI_RXSTATUS_REAUTH_REQ(x) ((x) & BIT(3)) 252*4882a593Smuzhiyun 253*4882a593Smuzhiyun /* 254*4882a593Smuzhiyun * Helper functions to convert 24bit big endian hdcp sequence number to 255*4882a593Smuzhiyun * host format and back 256*4882a593Smuzhiyun */ 257*4882a593Smuzhiyun static inline drm_hdcp_be24_to_cpu(const u8 seq_num[HDCP_2_2_SEQ_NUM_LEN])258*4882a593Smuzhiyunu32 drm_hdcp_be24_to_cpu(const u8 seq_num[HDCP_2_2_SEQ_NUM_LEN]) 259*4882a593Smuzhiyun { 260*4882a593Smuzhiyun return (u32)(seq_num[2] | seq_num[1] << 8 | seq_num[0] << 16); 261*4882a593Smuzhiyun } 262*4882a593Smuzhiyun 263*4882a593Smuzhiyun static inline drm_hdcp_cpu_to_be24(u8 seq_num[HDCP_2_2_SEQ_NUM_LEN],u32 val)264*4882a593Smuzhiyunvoid drm_hdcp_cpu_to_be24(u8 seq_num[HDCP_2_2_SEQ_NUM_LEN], u32 val) 265*4882a593Smuzhiyun { 266*4882a593Smuzhiyun seq_num[0] = val >> 16; 267*4882a593Smuzhiyun seq_num[1] = val >> 8; 268*4882a593Smuzhiyun seq_num[2] = val; 269*4882a593Smuzhiyun } 270*4882a593Smuzhiyun 271*4882a593Smuzhiyun #define DRM_HDCP_SRM_GEN1_MAX_BYTES (5 * 1024) 272*4882a593Smuzhiyun #define DRM_HDCP_1_4_SRM_ID 0x8 273*4882a593Smuzhiyun #define DRM_HDCP_SRM_ID_MASK (0xF << 4) 274*4882a593Smuzhiyun #define DRM_HDCP_1_4_VRL_LENGTH_SIZE 3 275*4882a593Smuzhiyun #define DRM_HDCP_1_4_DCP_SIG_SIZE 40 276*4882a593Smuzhiyun #define DRM_HDCP_2_SRM_ID 0x9 277*4882a593Smuzhiyun #define DRM_HDCP_2_INDICATOR 0x1 278*4882a593Smuzhiyun #define DRM_HDCP_2_INDICATOR_MASK 0xF 279*4882a593Smuzhiyun #define DRM_HDCP_2_VRL_LENGTH_SIZE 3 280*4882a593Smuzhiyun #define DRM_HDCP_2_DCP_SIG_SIZE 384 281*4882a593Smuzhiyun #define DRM_HDCP_2_NO_OF_DEV_PLUS_RESERVED_SZ 4 282*4882a593Smuzhiyun #define DRM_HDCP_2_KSV_COUNT_2_LSBITS(byte) (((byte) & 0xC0) >> 6) 283*4882a593Smuzhiyun 284*4882a593Smuzhiyun struct hdcp_srm_header { 285*4882a593Smuzhiyun u8 srm_id; 286*4882a593Smuzhiyun u8 reserved; 287*4882a593Smuzhiyun __be16 srm_version; 288*4882a593Smuzhiyun u8 srm_gen_no; 289*4882a593Smuzhiyun } __packed; 290*4882a593Smuzhiyun 291*4882a593Smuzhiyun struct drm_device; 292*4882a593Smuzhiyun struct drm_connector; 293*4882a593Smuzhiyun 294*4882a593Smuzhiyun int drm_hdcp_check_ksvs_revoked(struct drm_device *dev, 295*4882a593Smuzhiyun u8 *ksvs, u32 ksv_count); 296*4882a593Smuzhiyun int drm_connector_attach_content_protection_property( 297*4882a593Smuzhiyun struct drm_connector *connector, bool hdcp_content_type); 298*4882a593Smuzhiyun void drm_hdcp_update_content_protection(struct drm_connector *connector, 299*4882a593Smuzhiyun u64 val); 300*4882a593Smuzhiyun 301*4882a593Smuzhiyun /* Content Type classification for HDCP2.2 vs others */ 302*4882a593Smuzhiyun #define DRM_MODE_HDCP_CONTENT_TYPE0 0 303*4882a593Smuzhiyun #define DRM_MODE_HDCP_CONTENT_TYPE1 1 304*4882a593Smuzhiyun 305*4882a593Smuzhiyun #endif 306