xref: /OK3568_Linux_fs/kernel/include/drm/drm_cache.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /**************************************************************************
2*4882a593Smuzhiyun  *
3*4882a593Smuzhiyun  * Copyright 2009 Red Hat Inc.
4*4882a593Smuzhiyun  * All Rights Reserved.
5*4882a593Smuzhiyun  *
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8*4882a593Smuzhiyun  * "Software"), to deal in the Software without restriction, including
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12*4882a593Smuzhiyun  * the following conditions:
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15*4882a593Smuzhiyun  * next paragraph) shall be included in all copies or substantial portions
16*4882a593Smuzhiyun  * of the Software.
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28*4882a593Smuzhiyun /*
29*4882a593Smuzhiyun  * Authors:
30*4882a593Smuzhiyun  * Dave Airlie <airlied@redhat.com>
31*4882a593Smuzhiyun  */
32*4882a593Smuzhiyun 
33*4882a593Smuzhiyun #ifndef _DRM_CACHE_H_
34*4882a593Smuzhiyun #define _DRM_CACHE_H_
35*4882a593Smuzhiyun 
36*4882a593Smuzhiyun #include <linux/scatterlist.h>
37*4882a593Smuzhiyun 
38*4882a593Smuzhiyun void drm_clflush_pages(struct page *pages[], unsigned long num_pages);
39*4882a593Smuzhiyun void drm_clflush_sg(struct sg_table *st);
40*4882a593Smuzhiyun void drm_clflush_virt_range(void *addr, unsigned long length);
41*4882a593Smuzhiyun bool drm_need_swiotlb(int dma_bits);
42*4882a593Smuzhiyun 
43*4882a593Smuzhiyun 
drm_arch_can_wc_memory(void)44*4882a593Smuzhiyun static inline bool drm_arch_can_wc_memory(void)
45*4882a593Smuzhiyun {
46*4882a593Smuzhiyun #if defined(CONFIG_PPC) && !defined(CONFIG_NOT_COHERENT_CACHE)
47*4882a593Smuzhiyun 	return false;
48*4882a593Smuzhiyun #elif defined(CONFIG_MIPS) && defined(CONFIG_CPU_LOONGSON64)
49*4882a593Smuzhiyun 	return false;
50*4882a593Smuzhiyun #elif defined(CONFIG_ARM) || defined(CONFIG_ARM64)
51*4882a593Smuzhiyun 	/*
52*4882a593Smuzhiyun 	 * The DRM driver stack is designed to work with cache coherent devices
53*4882a593Smuzhiyun 	 * only, but permits an optimization to be enabled in some cases, where
54*4882a593Smuzhiyun 	 * for some buffers, both the CPU and the GPU use uncached mappings,
55*4882a593Smuzhiyun 	 * removing the need for DMA snooping and allocation in the CPU caches.
56*4882a593Smuzhiyun 	 *
57*4882a593Smuzhiyun 	 * The use of uncached GPU mappings relies on the correct implementation
58*4882a593Smuzhiyun 	 * of the PCIe NoSnoop TLP attribute by the platform, otherwise the GPU
59*4882a593Smuzhiyun 	 * will use cached mappings nonetheless. On x86 platforms, this does not
60*4882a593Smuzhiyun 	 * seem to matter, as uncached CPU mappings will snoop the caches in any
61*4882a593Smuzhiyun 	 * case. However, on ARM and arm64, enabling this optimization on a
62*4882a593Smuzhiyun 	 * platform where NoSnoop is ignored results in loss of coherency, which
63*4882a593Smuzhiyun 	 * breaks correct operation of the device. Since we have no way of
64*4882a593Smuzhiyun 	 * detecting whether NoSnoop works or not, just disable this
65*4882a593Smuzhiyun 	 * optimization entirely for ARM and arm64.
66*4882a593Smuzhiyun 	 */
67*4882a593Smuzhiyun 	return false;
68*4882a593Smuzhiyun #else
69*4882a593Smuzhiyun 	return true;
70*4882a593Smuzhiyun #endif
71*4882a593Smuzhiyun }
72*4882a593Smuzhiyun 
73*4882a593Smuzhiyun #endif
74