1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (C) STMicroelectronics SA 2017 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Authors: Philippe Cornu <philippe.cornu@st.com> 6*4882a593Smuzhiyun * Yannick Fertre <yannick.fertre@st.com> 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef __DW_MIPI_DSI__ 10*4882a593Smuzhiyun #define __DW_MIPI_DSI__ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #include <linux/types.h> 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #include <drm/drm_modes.h> 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun struct drm_display_mode; 17*4882a593Smuzhiyun struct drm_encoder; 18*4882a593Smuzhiyun struct dw_mipi_dsi; 19*4882a593Smuzhiyun struct mipi_dsi_device; 20*4882a593Smuzhiyun struct platform_device; 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun struct dw_mipi_dsi_dphy_timing { 23*4882a593Smuzhiyun u16 data_hs2lp; 24*4882a593Smuzhiyun u16 data_lp2hs; 25*4882a593Smuzhiyun u16 clk_hs2lp; 26*4882a593Smuzhiyun u16 clk_lp2hs; 27*4882a593Smuzhiyun }; 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun struct dw_mipi_dsi_phy_ops { 30*4882a593Smuzhiyun int (*init)(void *priv_data); 31*4882a593Smuzhiyun void (*power_on)(void *priv_data); 32*4882a593Smuzhiyun void (*power_off)(void *priv_data); 33*4882a593Smuzhiyun int (*get_lane_mbps)(void *priv_data, 34*4882a593Smuzhiyun const struct drm_display_mode *mode, 35*4882a593Smuzhiyun unsigned long mode_flags, u32 lanes, u32 format, 36*4882a593Smuzhiyun unsigned int *lane_mbps); 37*4882a593Smuzhiyun int (*get_timing)(void *priv_data, unsigned int lane_mbps, 38*4882a593Smuzhiyun struct dw_mipi_dsi_dphy_timing *timing); 39*4882a593Smuzhiyun int (*get_esc_clk_rate)(void *priv_data, unsigned int *esc_clk_rate); 40*4882a593Smuzhiyun }; 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun struct dw_mipi_dsi_host_ops { 43*4882a593Smuzhiyun int (*attach)(void *priv_data, 44*4882a593Smuzhiyun struct mipi_dsi_device *dsi); 45*4882a593Smuzhiyun int (*detach)(void *priv_data, 46*4882a593Smuzhiyun struct mipi_dsi_device *dsi); 47*4882a593Smuzhiyun }; 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun struct dw_mipi_dsi_plat_data { 50*4882a593Smuzhiyun void __iomem *base; 51*4882a593Smuzhiyun unsigned int max_data_lanes; 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun enum drm_mode_status (*mode_valid)(void *priv_data, 54*4882a593Smuzhiyun const struct drm_display_mode *mode); 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun const struct dw_mipi_dsi_phy_ops *phy_ops; 57*4882a593Smuzhiyun const struct dw_mipi_dsi_host_ops *host_ops; 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun void *priv_data; 60*4882a593Smuzhiyun }; 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun struct dw_mipi_dsi *dw_mipi_dsi_probe(struct platform_device *pdev, 63*4882a593Smuzhiyun const struct dw_mipi_dsi_plat_data 64*4882a593Smuzhiyun *plat_data); 65*4882a593Smuzhiyun void dw_mipi_dsi_remove(struct dw_mipi_dsi *dsi); 66*4882a593Smuzhiyun int dw_mipi_dsi_bind(struct dw_mipi_dsi *dsi, struct drm_encoder *encoder); 67*4882a593Smuzhiyun void dw_mipi_dsi_unbind(struct dw_mipi_dsi *dsi); 68*4882a593Smuzhiyun void dw_mipi_dsi_set_slave(struct dw_mipi_dsi *dsi, struct dw_mipi_dsi *slave); 69*4882a593Smuzhiyun struct drm_connector *dw_mipi_dsi_get_connector(struct dw_mipi_dsi *dsi); 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun #endif /* __DW_MIPI_DSI__ */ 72