1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * CPPC (Collaborative Processor Performance Control) methods used 4*4882a593Smuzhiyun * by CPUfreq drivers. 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * (C) Copyright 2014, 2015 Linaro Ltd. 7*4882a593Smuzhiyun * Author: Ashwin Chaugule <ashwin.chaugule@linaro.org> 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #ifndef _CPPC_ACPI_H 11*4882a593Smuzhiyun #define _CPPC_ACPI_H 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #include <linux/acpi.h> 14*4882a593Smuzhiyun #include <linux/types.h> 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun #include <acpi/pcc.h> 17*4882a593Smuzhiyun #include <acpi/processor.h> 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun /* CPPCv2 and CPPCv3 support */ 20*4882a593Smuzhiyun #define CPPC_V2_REV 2 21*4882a593Smuzhiyun #define CPPC_V3_REV 3 22*4882a593Smuzhiyun #define CPPC_V2_NUM_ENT 21 23*4882a593Smuzhiyun #define CPPC_V3_NUM_ENT 23 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun #define PCC_CMD_COMPLETE_MASK (1 << 0) 26*4882a593Smuzhiyun #define PCC_ERROR_MASK (1 << 2) 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun #define MAX_CPC_REG_ENT 21 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun /* CPPC specific PCC commands. */ 31*4882a593Smuzhiyun #define CMD_READ 0 32*4882a593Smuzhiyun #define CMD_WRITE 1 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun /* Each register has the folowing format. */ 35*4882a593Smuzhiyun struct cpc_reg { 36*4882a593Smuzhiyun u8 descriptor; 37*4882a593Smuzhiyun u16 length; 38*4882a593Smuzhiyun u8 space_id; 39*4882a593Smuzhiyun u8 bit_width; 40*4882a593Smuzhiyun u8 bit_offset; 41*4882a593Smuzhiyun u8 access_width; 42*4882a593Smuzhiyun u64 __iomem address; 43*4882a593Smuzhiyun } __packed; 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun /* 46*4882a593Smuzhiyun * Each entry in the CPC table is either 47*4882a593Smuzhiyun * of type ACPI_TYPE_BUFFER or 48*4882a593Smuzhiyun * ACPI_TYPE_INTEGER. 49*4882a593Smuzhiyun */ 50*4882a593Smuzhiyun struct cpc_register_resource { 51*4882a593Smuzhiyun acpi_object_type type; 52*4882a593Smuzhiyun u64 __iomem *sys_mem_vaddr; 53*4882a593Smuzhiyun union { 54*4882a593Smuzhiyun struct cpc_reg reg; 55*4882a593Smuzhiyun u64 int_value; 56*4882a593Smuzhiyun } cpc_entry; 57*4882a593Smuzhiyun }; 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun /* Container to hold the CPC details for each CPU */ 60*4882a593Smuzhiyun struct cpc_desc { 61*4882a593Smuzhiyun int num_entries; 62*4882a593Smuzhiyun int version; 63*4882a593Smuzhiyun int cpu_id; 64*4882a593Smuzhiyun int write_cmd_status; 65*4882a593Smuzhiyun int write_cmd_id; 66*4882a593Smuzhiyun struct cpc_register_resource cpc_regs[MAX_CPC_REG_ENT]; 67*4882a593Smuzhiyun struct acpi_psd_package domain_info; 68*4882a593Smuzhiyun struct kobject kobj; 69*4882a593Smuzhiyun }; 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun /* These are indexes into the per-cpu cpc_regs[]. Order is important. */ 72*4882a593Smuzhiyun enum cppc_regs { 73*4882a593Smuzhiyun HIGHEST_PERF, 74*4882a593Smuzhiyun NOMINAL_PERF, 75*4882a593Smuzhiyun LOW_NON_LINEAR_PERF, 76*4882a593Smuzhiyun LOWEST_PERF, 77*4882a593Smuzhiyun GUARANTEED_PERF, 78*4882a593Smuzhiyun DESIRED_PERF, 79*4882a593Smuzhiyun MIN_PERF, 80*4882a593Smuzhiyun MAX_PERF, 81*4882a593Smuzhiyun PERF_REDUC_TOLERANCE, 82*4882a593Smuzhiyun TIME_WINDOW, 83*4882a593Smuzhiyun CTR_WRAP_TIME, 84*4882a593Smuzhiyun REFERENCE_CTR, 85*4882a593Smuzhiyun DELIVERED_CTR, 86*4882a593Smuzhiyun PERF_LIMITED, 87*4882a593Smuzhiyun ENABLE, 88*4882a593Smuzhiyun AUTO_SEL_ENABLE, 89*4882a593Smuzhiyun AUTO_ACT_WINDOW, 90*4882a593Smuzhiyun ENERGY_PERF, 91*4882a593Smuzhiyun REFERENCE_PERF, 92*4882a593Smuzhiyun LOWEST_FREQ, 93*4882a593Smuzhiyun NOMINAL_FREQ, 94*4882a593Smuzhiyun }; 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun /* 97*4882a593Smuzhiyun * Categorization of registers as described 98*4882a593Smuzhiyun * in the ACPI v.5.1 spec. 99*4882a593Smuzhiyun * XXX: Only filling up ones which are used by governors 100*4882a593Smuzhiyun * today. 101*4882a593Smuzhiyun */ 102*4882a593Smuzhiyun struct cppc_perf_caps { 103*4882a593Smuzhiyun u32 guaranteed_perf; 104*4882a593Smuzhiyun u32 highest_perf; 105*4882a593Smuzhiyun u32 nominal_perf; 106*4882a593Smuzhiyun u32 lowest_perf; 107*4882a593Smuzhiyun u32 lowest_nonlinear_perf; 108*4882a593Smuzhiyun u32 lowest_freq; 109*4882a593Smuzhiyun u32 nominal_freq; 110*4882a593Smuzhiyun }; 111*4882a593Smuzhiyun 112*4882a593Smuzhiyun struct cppc_perf_ctrls { 113*4882a593Smuzhiyun u32 max_perf; 114*4882a593Smuzhiyun u32 min_perf; 115*4882a593Smuzhiyun u32 desired_perf; 116*4882a593Smuzhiyun }; 117*4882a593Smuzhiyun 118*4882a593Smuzhiyun struct cppc_perf_fb_ctrs { 119*4882a593Smuzhiyun u64 reference; 120*4882a593Smuzhiyun u64 delivered; 121*4882a593Smuzhiyun u64 reference_perf; 122*4882a593Smuzhiyun u64 wraparound_time; 123*4882a593Smuzhiyun }; 124*4882a593Smuzhiyun 125*4882a593Smuzhiyun /* Per CPU container for runtime CPPC management. */ 126*4882a593Smuzhiyun struct cppc_cpudata { 127*4882a593Smuzhiyun int cpu; 128*4882a593Smuzhiyun struct cppc_perf_caps perf_caps; 129*4882a593Smuzhiyun struct cppc_perf_ctrls perf_ctrls; 130*4882a593Smuzhiyun struct cppc_perf_fb_ctrs perf_fb_ctrs; 131*4882a593Smuzhiyun struct cpufreq_policy *cur_policy; 132*4882a593Smuzhiyun unsigned int shared_type; 133*4882a593Smuzhiyun cpumask_var_t shared_cpu_map; 134*4882a593Smuzhiyun }; 135*4882a593Smuzhiyun 136*4882a593Smuzhiyun extern int cppc_get_desired_perf(int cpunum, u64 *desired_perf); 137*4882a593Smuzhiyun extern int cppc_get_perf_ctrs(int cpu, struct cppc_perf_fb_ctrs *perf_fb_ctrs); 138*4882a593Smuzhiyun extern int cppc_set_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls); 139*4882a593Smuzhiyun extern int cppc_get_perf_caps(int cpu, struct cppc_perf_caps *caps); 140*4882a593Smuzhiyun extern int acpi_get_psd_map(struct cppc_cpudata **); 141*4882a593Smuzhiyun extern unsigned int cppc_get_transition_latency(int cpu); 142*4882a593Smuzhiyun extern bool cpc_ffh_supported(void); 143*4882a593Smuzhiyun extern int cpc_read_ffh(int cpunum, struct cpc_reg *reg, u64 *val); 144*4882a593Smuzhiyun extern int cpc_write_ffh(int cpunum, struct cpc_reg *reg, u64 val); 145*4882a593Smuzhiyun 146*4882a593Smuzhiyun #endif /* _CPPC_ACPI_H*/ 147