1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-1.0+ */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Industrial Computer Source WDT500/501 driver 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * (c) Copyright 1995 CymruNET Ltd 6*4882a593Smuzhiyun * Innovation Centre 7*4882a593Smuzhiyun * Singleton Park 8*4882a593Smuzhiyun * Swansea 9*4882a593Smuzhiyun * Wales 10*4882a593Smuzhiyun * UK 11*4882a593Smuzhiyun * SA2 8PP 12*4882a593Smuzhiyun * 13*4882a593Smuzhiyun * http://www.cymru.net 14*4882a593Smuzhiyun * 15*4882a593Smuzhiyun * Release 0.04. 16*4882a593Smuzhiyun */ 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun #define WDT_COUNT0 (io+0) 20*4882a593Smuzhiyun #define WDT_COUNT1 (io+1) 21*4882a593Smuzhiyun #define WDT_COUNT2 (io+2) 22*4882a593Smuzhiyun #define WDT_CR (io+3) 23*4882a593Smuzhiyun #define WDT_SR (io+4) /* Start buzzer on PCI write */ 24*4882a593Smuzhiyun #define WDT_RT (io+5) /* Stop buzzer on PCI write */ 25*4882a593Smuzhiyun #define WDT_BUZZER (io+6) /* PCI only: rd=disable, wr=enable */ 26*4882a593Smuzhiyun #define WDT_DC (io+7) 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun /* The following are only on the PCI card, they're outside of I/O space on 29*4882a593Smuzhiyun * the ISA card: */ 30*4882a593Smuzhiyun #define WDT_CLOCK (io+12) /* COUNT2: rd=16.67MHz, wr=2.0833MHz */ 31*4882a593Smuzhiyun /* inverted opto isolated reset output: */ 32*4882a593Smuzhiyun #define WDT_OPTONOTRST (io+13) /* wr=enable, rd=disable */ 33*4882a593Smuzhiyun /* opto isolated reset output: */ 34*4882a593Smuzhiyun #define WDT_OPTORST (io+14) /* wr=enable, rd=disable */ 35*4882a593Smuzhiyun /* programmable outputs: */ 36*4882a593Smuzhiyun #define WDT_PROGOUT (io+15) /* wr=enable, rd=disable */ 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun /* FAN 501 500 */ 39*4882a593Smuzhiyun #define WDC_SR_WCCR 1 /* Active low */ /* X X X */ 40*4882a593Smuzhiyun #define WDC_SR_TGOOD 2 /* X X - */ 41*4882a593Smuzhiyun #define WDC_SR_ISOI0 4 /* X X X */ 42*4882a593Smuzhiyun #define WDC_SR_ISII1 8 /* X X X */ 43*4882a593Smuzhiyun #define WDC_SR_FANGOOD 16 /* X - - */ 44*4882a593Smuzhiyun #define WDC_SR_PSUOVER 32 /* Active low */ /* X X - */ 45*4882a593Smuzhiyun #define WDC_SR_PSUUNDR 64 /* Active low */ /* X X - */ 46*4882a593Smuzhiyun #define WDC_SR_IRQ 128 /* Active low */ /* X X X */ 47*4882a593Smuzhiyun 48