1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Watchdog driver for the UniPhier watchdog timer
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * (c) Copyright 2014 Panasonic Corporation
6*4882a593Smuzhiyun * (c) Copyright 2016 Socionext Inc.
7*4882a593Smuzhiyun * All rights reserved.
8*4882a593Smuzhiyun */
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #include <linux/bitops.h>
11*4882a593Smuzhiyun #include <linux/mfd/syscon.h>
12*4882a593Smuzhiyun #include <linux/module.h>
13*4882a593Smuzhiyun #include <linux/of.h>
14*4882a593Smuzhiyun #include <linux/platform_device.h>
15*4882a593Smuzhiyun #include <linux/regmap.h>
16*4882a593Smuzhiyun #include <linux/watchdog.h>
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun /* WDT timer setting register */
19*4882a593Smuzhiyun #define WDTTIMSET 0x3004
20*4882a593Smuzhiyun #define WDTTIMSET_PERIOD_MASK (0xf << 0)
21*4882a593Smuzhiyun #define WDTTIMSET_PERIOD_1_SEC (0x3 << 0)
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun /* WDT reset selection register */
24*4882a593Smuzhiyun #define WDTRSTSEL 0x3008
25*4882a593Smuzhiyun #define WDTRSTSEL_RSTSEL_MASK (0x3 << 0)
26*4882a593Smuzhiyun #define WDTRSTSEL_RSTSEL_BOTH (0x0 << 0)
27*4882a593Smuzhiyun #define WDTRSTSEL_RSTSEL_IRQ_ONLY (0x2 << 0)
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun /* WDT control register */
30*4882a593Smuzhiyun #define WDTCTRL 0x300c
31*4882a593Smuzhiyun #define WDTCTRL_STATUS BIT(8)
32*4882a593Smuzhiyun #define WDTCTRL_CLEAR BIT(1)
33*4882a593Smuzhiyun #define WDTCTRL_ENABLE BIT(0)
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun #define SEC_TO_WDTTIMSET_PRD(sec) \
36*4882a593Smuzhiyun (ilog2(sec) + WDTTIMSET_PERIOD_1_SEC)
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun #define WDTST_TIMEOUT 1000 /* usec */
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun #define WDT_DEFAULT_TIMEOUT 64 /* Default is 64 seconds */
41*4882a593Smuzhiyun #define WDT_PERIOD_MIN 1
42*4882a593Smuzhiyun #define WDT_PERIOD_MAX 128
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun static unsigned int timeout = 0;
45*4882a593Smuzhiyun static bool nowayout = WATCHDOG_NOWAYOUT;
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun struct uniphier_wdt_dev {
48*4882a593Smuzhiyun struct watchdog_device wdt_dev;
49*4882a593Smuzhiyun struct regmap *regmap;
50*4882a593Smuzhiyun };
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun /*
53*4882a593Smuzhiyun * UniPhier Watchdog operations
54*4882a593Smuzhiyun */
uniphier_watchdog_ping(struct watchdog_device * w)55*4882a593Smuzhiyun static int uniphier_watchdog_ping(struct watchdog_device *w)
56*4882a593Smuzhiyun {
57*4882a593Smuzhiyun struct uniphier_wdt_dev *wdev = watchdog_get_drvdata(w);
58*4882a593Smuzhiyun unsigned int val;
59*4882a593Smuzhiyun int ret;
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun /* Clear counter */
62*4882a593Smuzhiyun ret = regmap_write_bits(wdev->regmap, WDTCTRL,
63*4882a593Smuzhiyun WDTCTRL_CLEAR, WDTCTRL_CLEAR);
64*4882a593Smuzhiyun if (!ret)
65*4882a593Smuzhiyun /*
66*4882a593Smuzhiyun * As SoC specification, after clear counter,
67*4882a593Smuzhiyun * it needs to wait until counter status is 1.
68*4882a593Smuzhiyun */
69*4882a593Smuzhiyun ret = regmap_read_poll_timeout(wdev->regmap, WDTCTRL, val,
70*4882a593Smuzhiyun (val & WDTCTRL_STATUS),
71*4882a593Smuzhiyun 0, WDTST_TIMEOUT);
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun return ret;
74*4882a593Smuzhiyun }
75*4882a593Smuzhiyun
__uniphier_watchdog_start(struct regmap * regmap,unsigned int sec)76*4882a593Smuzhiyun static int __uniphier_watchdog_start(struct regmap *regmap, unsigned int sec)
77*4882a593Smuzhiyun {
78*4882a593Smuzhiyun unsigned int val;
79*4882a593Smuzhiyun int ret;
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun ret = regmap_read_poll_timeout(regmap, WDTCTRL, val,
82*4882a593Smuzhiyun !(val & WDTCTRL_STATUS),
83*4882a593Smuzhiyun 0, WDTST_TIMEOUT);
84*4882a593Smuzhiyun if (ret)
85*4882a593Smuzhiyun return ret;
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun /* Setup period */
88*4882a593Smuzhiyun ret = regmap_write(regmap, WDTTIMSET,
89*4882a593Smuzhiyun SEC_TO_WDTTIMSET_PRD(sec));
90*4882a593Smuzhiyun if (ret)
91*4882a593Smuzhiyun return ret;
92*4882a593Smuzhiyun
93*4882a593Smuzhiyun /* Enable and clear watchdog */
94*4882a593Smuzhiyun ret = regmap_write(regmap, WDTCTRL, WDTCTRL_ENABLE | WDTCTRL_CLEAR);
95*4882a593Smuzhiyun if (!ret)
96*4882a593Smuzhiyun /*
97*4882a593Smuzhiyun * As SoC specification, after clear counter,
98*4882a593Smuzhiyun * it needs to wait until counter status is 1.
99*4882a593Smuzhiyun */
100*4882a593Smuzhiyun ret = regmap_read_poll_timeout(regmap, WDTCTRL, val,
101*4882a593Smuzhiyun (val & WDTCTRL_STATUS),
102*4882a593Smuzhiyun 0, WDTST_TIMEOUT);
103*4882a593Smuzhiyun
104*4882a593Smuzhiyun return ret;
105*4882a593Smuzhiyun }
106*4882a593Smuzhiyun
__uniphier_watchdog_stop(struct regmap * regmap)107*4882a593Smuzhiyun static int __uniphier_watchdog_stop(struct regmap *regmap)
108*4882a593Smuzhiyun {
109*4882a593Smuzhiyun /* Disable and stop watchdog */
110*4882a593Smuzhiyun return regmap_write_bits(regmap, WDTCTRL, WDTCTRL_ENABLE, 0);
111*4882a593Smuzhiyun }
112*4882a593Smuzhiyun
__uniphier_watchdog_restart(struct regmap * regmap,unsigned int sec)113*4882a593Smuzhiyun static int __uniphier_watchdog_restart(struct regmap *regmap, unsigned int sec)
114*4882a593Smuzhiyun {
115*4882a593Smuzhiyun int ret;
116*4882a593Smuzhiyun
117*4882a593Smuzhiyun ret = __uniphier_watchdog_stop(regmap);
118*4882a593Smuzhiyun if (ret)
119*4882a593Smuzhiyun return ret;
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun return __uniphier_watchdog_start(regmap, sec);
122*4882a593Smuzhiyun }
123*4882a593Smuzhiyun
uniphier_watchdog_start(struct watchdog_device * w)124*4882a593Smuzhiyun static int uniphier_watchdog_start(struct watchdog_device *w)
125*4882a593Smuzhiyun {
126*4882a593Smuzhiyun struct uniphier_wdt_dev *wdev = watchdog_get_drvdata(w);
127*4882a593Smuzhiyun unsigned int tmp_timeout;
128*4882a593Smuzhiyun
129*4882a593Smuzhiyun tmp_timeout = roundup_pow_of_two(w->timeout);
130*4882a593Smuzhiyun
131*4882a593Smuzhiyun return __uniphier_watchdog_start(wdev->regmap, tmp_timeout);
132*4882a593Smuzhiyun }
133*4882a593Smuzhiyun
uniphier_watchdog_stop(struct watchdog_device * w)134*4882a593Smuzhiyun static int uniphier_watchdog_stop(struct watchdog_device *w)
135*4882a593Smuzhiyun {
136*4882a593Smuzhiyun struct uniphier_wdt_dev *wdev = watchdog_get_drvdata(w);
137*4882a593Smuzhiyun
138*4882a593Smuzhiyun return __uniphier_watchdog_stop(wdev->regmap);
139*4882a593Smuzhiyun }
140*4882a593Smuzhiyun
uniphier_watchdog_set_timeout(struct watchdog_device * w,unsigned int t)141*4882a593Smuzhiyun static int uniphier_watchdog_set_timeout(struct watchdog_device *w,
142*4882a593Smuzhiyun unsigned int t)
143*4882a593Smuzhiyun {
144*4882a593Smuzhiyun struct uniphier_wdt_dev *wdev = watchdog_get_drvdata(w);
145*4882a593Smuzhiyun unsigned int tmp_timeout;
146*4882a593Smuzhiyun int ret;
147*4882a593Smuzhiyun
148*4882a593Smuzhiyun tmp_timeout = roundup_pow_of_two(t);
149*4882a593Smuzhiyun if (tmp_timeout == w->timeout)
150*4882a593Smuzhiyun return 0;
151*4882a593Smuzhiyun
152*4882a593Smuzhiyun if (watchdog_active(w)) {
153*4882a593Smuzhiyun ret = __uniphier_watchdog_restart(wdev->regmap, tmp_timeout);
154*4882a593Smuzhiyun if (ret)
155*4882a593Smuzhiyun return ret;
156*4882a593Smuzhiyun }
157*4882a593Smuzhiyun
158*4882a593Smuzhiyun w->timeout = tmp_timeout;
159*4882a593Smuzhiyun
160*4882a593Smuzhiyun return 0;
161*4882a593Smuzhiyun }
162*4882a593Smuzhiyun
163*4882a593Smuzhiyun /*
164*4882a593Smuzhiyun * Kernel Interfaces
165*4882a593Smuzhiyun */
166*4882a593Smuzhiyun static const struct watchdog_info uniphier_wdt_info = {
167*4882a593Smuzhiyun .identity = "uniphier-wdt",
168*4882a593Smuzhiyun .options = WDIOF_SETTIMEOUT |
169*4882a593Smuzhiyun WDIOF_KEEPALIVEPING |
170*4882a593Smuzhiyun WDIOF_MAGICCLOSE |
171*4882a593Smuzhiyun WDIOF_OVERHEAT,
172*4882a593Smuzhiyun };
173*4882a593Smuzhiyun
174*4882a593Smuzhiyun static const struct watchdog_ops uniphier_wdt_ops = {
175*4882a593Smuzhiyun .owner = THIS_MODULE,
176*4882a593Smuzhiyun .start = uniphier_watchdog_start,
177*4882a593Smuzhiyun .stop = uniphier_watchdog_stop,
178*4882a593Smuzhiyun .ping = uniphier_watchdog_ping,
179*4882a593Smuzhiyun .set_timeout = uniphier_watchdog_set_timeout,
180*4882a593Smuzhiyun };
181*4882a593Smuzhiyun
uniphier_wdt_probe(struct platform_device * pdev)182*4882a593Smuzhiyun static int uniphier_wdt_probe(struct platform_device *pdev)
183*4882a593Smuzhiyun {
184*4882a593Smuzhiyun struct device *dev = &pdev->dev;
185*4882a593Smuzhiyun struct uniphier_wdt_dev *wdev;
186*4882a593Smuzhiyun struct regmap *regmap;
187*4882a593Smuzhiyun struct device_node *parent;
188*4882a593Smuzhiyun int ret;
189*4882a593Smuzhiyun
190*4882a593Smuzhiyun wdev = devm_kzalloc(dev, sizeof(*wdev), GFP_KERNEL);
191*4882a593Smuzhiyun if (!wdev)
192*4882a593Smuzhiyun return -ENOMEM;
193*4882a593Smuzhiyun
194*4882a593Smuzhiyun parent = of_get_parent(dev->of_node); /* parent should be syscon node */
195*4882a593Smuzhiyun regmap = syscon_node_to_regmap(parent);
196*4882a593Smuzhiyun of_node_put(parent);
197*4882a593Smuzhiyun if (IS_ERR(regmap))
198*4882a593Smuzhiyun return PTR_ERR(regmap);
199*4882a593Smuzhiyun
200*4882a593Smuzhiyun wdev->regmap = regmap;
201*4882a593Smuzhiyun wdev->wdt_dev.info = &uniphier_wdt_info;
202*4882a593Smuzhiyun wdev->wdt_dev.ops = &uniphier_wdt_ops;
203*4882a593Smuzhiyun wdev->wdt_dev.max_timeout = WDT_PERIOD_MAX;
204*4882a593Smuzhiyun wdev->wdt_dev.min_timeout = WDT_PERIOD_MIN;
205*4882a593Smuzhiyun wdev->wdt_dev.timeout = WDT_DEFAULT_TIMEOUT;
206*4882a593Smuzhiyun wdev->wdt_dev.parent = dev;
207*4882a593Smuzhiyun
208*4882a593Smuzhiyun watchdog_init_timeout(&wdev->wdt_dev, timeout, dev);
209*4882a593Smuzhiyun watchdog_set_nowayout(&wdev->wdt_dev, nowayout);
210*4882a593Smuzhiyun watchdog_stop_on_reboot(&wdev->wdt_dev);
211*4882a593Smuzhiyun
212*4882a593Smuzhiyun watchdog_set_drvdata(&wdev->wdt_dev, wdev);
213*4882a593Smuzhiyun
214*4882a593Smuzhiyun uniphier_watchdog_stop(&wdev->wdt_dev);
215*4882a593Smuzhiyun ret = regmap_write(wdev->regmap, WDTRSTSEL, WDTRSTSEL_RSTSEL_BOTH);
216*4882a593Smuzhiyun if (ret)
217*4882a593Smuzhiyun return ret;
218*4882a593Smuzhiyun
219*4882a593Smuzhiyun ret = devm_watchdog_register_device(dev, &wdev->wdt_dev);
220*4882a593Smuzhiyun if (ret)
221*4882a593Smuzhiyun return ret;
222*4882a593Smuzhiyun
223*4882a593Smuzhiyun dev_info(dev, "watchdog driver (timeout=%d sec, nowayout=%d)\n",
224*4882a593Smuzhiyun wdev->wdt_dev.timeout, nowayout);
225*4882a593Smuzhiyun
226*4882a593Smuzhiyun return 0;
227*4882a593Smuzhiyun }
228*4882a593Smuzhiyun
229*4882a593Smuzhiyun static const struct of_device_id uniphier_wdt_dt_ids[] = {
230*4882a593Smuzhiyun { .compatible = "socionext,uniphier-wdt" },
231*4882a593Smuzhiyun { /* sentinel */ }
232*4882a593Smuzhiyun };
233*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, uniphier_wdt_dt_ids);
234*4882a593Smuzhiyun
235*4882a593Smuzhiyun static struct platform_driver uniphier_wdt_driver = {
236*4882a593Smuzhiyun .probe = uniphier_wdt_probe,
237*4882a593Smuzhiyun .driver = {
238*4882a593Smuzhiyun .name = "uniphier-wdt",
239*4882a593Smuzhiyun .of_match_table = uniphier_wdt_dt_ids,
240*4882a593Smuzhiyun },
241*4882a593Smuzhiyun };
242*4882a593Smuzhiyun
243*4882a593Smuzhiyun module_platform_driver(uniphier_wdt_driver);
244*4882a593Smuzhiyun
245*4882a593Smuzhiyun module_param(timeout, uint, 0000);
246*4882a593Smuzhiyun MODULE_PARM_DESC(timeout,
247*4882a593Smuzhiyun "Watchdog timeout seconds in power of 2. (0 < timeout < 128, default="
248*4882a593Smuzhiyun __MODULE_STRING(WDT_DEFAULT_TIMEOUT) ")");
249*4882a593Smuzhiyun
250*4882a593Smuzhiyun module_param(nowayout, bool, 0000);
251*4882a593Smuzhiyun MODULE_PARM_DESC(nowayout,
252*4882a593Smuzhiyun "Watchdog cannot be stopped once started (default="
253*4882a593Smuzhiyun __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
254*4882a593Smuzhiyun
255*4882a593Smuzhiyun MODULE_AUTHOR("Keiji Hayashibara <hayashibara.keiji@socionext.com>");
256*4882a593Smuzhiyun MODULE_DESCRIPTION("UniPhier Watchdog Device Driver");
257*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
258