1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0+
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Watchdog driver for TQMx86 PLD.
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * The watchdog supports power of 2 timeouts from 1 to 4096sec.
6*4882a593Smuzhiyun * Once started, it cannot be stopped.
7*4882a593Smuzhiyun *
8*4882a593Smuzhiyun * Based on the vendor code written by Vadim V.Vlasov
9*4882a593Smuzhiyun * <vvlasov@dev.rtsoft.ru>
10*4882a593Smuzhiyun */
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun #include <linux/io.h>
13*4882a593Smuzhiyun #include <linux/log2.h>
14*4882a593Smuzhiyun #include <linux/module.h>
15*4882a593Smuzhiyun #include <linux/platform_device.h>
16*4882a593Smuzhiyun #include <linux/timer.h>
17*4882a593Smuzhiyun #include <linux/watchdog.h>
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun /* default timeout (secs) */
20*4882a593Smuzhiyun #define WDT_TIMEOUT 32
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun static unsigned int timeout;
23*4882a593Smuzhiyun module_param(timeout, uint, 0);
24*4882a593Smuzhiyun MODULE_PARM_DESC(timeout,
25*4882a593Smuzhiyun "Watchdog timeout in seconds. (1<=timeout<=4096, default="
26*4882a593Smuzhiyun __MODULE_STRING(WDT_TIMEOUT) ")");
27*4882a593Smuzhiyun struct tqmx86_wdt {
28*4882a593Smuzhiyun struct watchdog_device wdd;
29*4882a593Smuzhiyun void __iomem *io_base;
30*4882a593Smuzhiyun };
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun #define TQMX86_WDCFG 0x00 /* Watchdog Configuration Register */
33*4882a593Smuzhiyun #define TQMX86_WDCS 0x01 /* Watchdog Config/Status Register */
34*4882a593Smuzhiyun
tqmx86_wdt_start(struct watchdog_device * wdd)35*4882a593Smuzhiyun static int tqmx86_wdt_start(struct watchdog_device *wdd)
36*4882a593Smuzhiyun {
37*4882a593Smuzhiyun struct tqmx86_wdt *priv = watchdog_get_drvdata(wdd);
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun iowrite8(0x81, priv->io_base + TQMX86_WDCS);
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun return 0;
42*4882a593Smuzhiyun }
43*4882a593Smuzhiyun
tqmx86_wdt_set_timeout(struct watchdog_device * wdd,unsigned int t)44*4882a593Smuzhiyun static int tqmx86_wdt_set_timeout(struct watchdog_device *wdd, unsigned int t)
45*4882a593Smuzhiyun {
46*4882a593Smuzhiyun struct tqmx86_wdt *priv = watchdog_get_drvdata(wdd);
47*4882a593Smuzhiyun u8 val;
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun t = roundup_pow_of_two(t);
50*4882a593Smuzhiyun val = ilog2(t) | 0x90;
51*4882a593Smuzhiyun val += 3; /* values 0,1,2 correspond to 0.125,0.25,0.5s timeouts */
52*4882a593Smuzhiyun iowrite8(val, priv->io_base + TQMX86_WDCFG);
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun wdd->timeout = t;
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun return 0;
57*4882a593Smuzhiyun }
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun static const struct watchdog_info tqmx86_wdt_info = {
60*4882a593Smuzhiyun .options = WDIOF_SETTIMEOUT |
61*4882a593Smuzhiyun WDIOF_KEEPALIVEPING,
62*4882a593Smuzhiyun .identity = "TQMx86 Watchdog",
63*4882a593Smuzhiyun };
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun static struct watchdog_ops tqmx86_wdt_ops = {
66*4882a593Smuzhiyun .owner = THIS_MODULE,
67*4882a593Smuzhiyun .start = tqmx86_wdt_start,
68*4882a593Smuzhiyun .set_timeout = tqmx86_wdt_set_timeout,
69*4882a593Smuzhiyun };
70*4882a593Smuzhiyun
tqmx86_wdt_probe(struct platform_device * pdev)71*4882a593Smuzhiyun static int tqmx86_wdt_probe(struct platform_device *pdev)
72*4882a593Smuzhiyun {
73*4882a593Smuzhiyun struct device *dev = &pdev->dev;
74*4882a593Smuzhiyun struct tqmx86_wdt *priv;
75*4882a593Smuzhiyun struct resource *res;
76*4882a593Smuzhiyun int err;
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
79*4882a593Smuzhiyun if (!priv)
80*4882a593Smuzhiyun return -ENOMEM;
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun res = platform_get_resource(pdev, IORESOURCE_IO, 0);
83*4882a593Smuzhiyun if (!res)
84*4882a593Smuzhiyun return -ENODEV;
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun priv->io_base = devm_ioport_map(dev, res->start, resource_size(res));
87*4882a593Smuzhiyun if (!priv->io_base)
88*4882a593Smuzhiyun return -ENOMEM;
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun watchdog_set_drvdata(&priv->wdd, priv);
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun priv->wdd.parent = dev;
93*4882a593Smuzhiyun priv->wdd.info = &tqmx86_wdt_info;
94*4882a593Smuzhiyun priv->wdd.ops = &tqmx86_wdt_ops;
95*4882a593Smuzhiyun priv->wdd.min_timeout = 1;
96*4882a593Smuzhiyun priv->wdd.max_timeout = 4096;
97*4882a593Smuzhiyun priv->wdd.max_hw_heartbeat_ms = 4096*1000;
98*4882a593Smuzhiyun priv->wdd.timeout = WDT_TIMEOUT;
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun watchdog_init_timeout(&priv->wdd, timeout, dev);
101*4882a593Smuzhiyun watchdog_set_nowayout(&priv->wdd, WATCHDOG_NOWAYOUT);
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun tqmx86_wdt_set_timeout(&priv->wdd, priv->wdd.timeout);
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun err = devm_watchdog_register_device(dev, &priv->wdd);
106*4882a593Smuzhiyun if (err)
107*4882a593Smuzhiyun return err;
108*4882a593Smuzhiyun
109*4882a593Smuzhiyun dev_info(dev, "TQMx86 watchdog\n");
110*4882a593Smuzhiyun
111*4882a593Smuzhiyun return 0;
112*4882a593Smuzhiyun }
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun static struct platform_driver tqmx86_wdt_driver = {
115*4882a593Smuzhiyun .driver = {
116*4882a593Smuzhiyun .name = "tqmx86-wdt",
117*4882a593Smuzhiyun },
118*4882a593Smuzhiyun .probe = tqmx86_wdt_probe,
119*4882a593Smuzhiyun };
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun module_platform_driver(tqmx86_wdt_driver);
122*4882a593Smuzhiyun
123*4882a593Smuzhiyun MODULE_AUTHOR("Andrew Lunn <andrew@lunn.ch>");
124*4882a593Smuzhiyun MODULE_DESCRIPTION("TQMx86 Watchdog");
125*4882a593Smuzhiyun MODULE_ALIAS("platform:tqmx86-wdt");
126*4882a593Smuzhiyun MODULE_LICENSE("GPL");
127