1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * sp5100_tco: TCO timer driver for sp5100 chipsets. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * (c) Copyright 2009 Google Inc., All Rights Reserved. 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * TCO timer driver for sp5100 chipsets 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #include <linux/bitops.h> 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun /* 13*4882a593Smuzhiyun * Some address definitions for the Watchdog 14*4882a593Smuzhiyun */ 15*4882a593Smuzhiyun #define SP5100_WDT_MEM_MAP_SIZE 0x08 16*4882a593Smuzhiyun #define SP5100_WDT_CONTROL(base) ((base) + 0x00) /* Watchdog Control */ 17*4882a593Smuzhiyun #define SP5100_WDT_COUNT(base) ((base) + 0x04) /* Watchdog Count */ 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun #define SP5100_WDT_START_STOP_BIT BIT(0) 20*4882a593Smuzhiyun #define SP5100_WDT_FIRED BIT(1) 21*4882a593Smuzhiyun #define SP5100_WDT_ACTION_RESET BIT(2) 22*4882a593Smuzhiyun #define SP5100_WDT_DISABLED BIT(3) 23*4882a593Smuzhiyun #define SP5100_WDT_TRIGGER_BIT BIT(7) 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun #define SP5100_PM_IOPORTS_SIZE 0x02 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun /* 28*4882a593Smuzhiyun * These two IO registers are hardcoded and there doesn't seem to be a way to 29*4882a593Smuzhiyun * read them from a register. 30*4882a593Smuzhiyun */ 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun /* For SP5100/SB7x0/SB8x0 chipset */ 33*4882a593Smuzhiyun #define SP5100_IO_PM_INDEX_REG 0xCD6 34*4882a593Smuzhiyun #define SP5100_IO_PM_DATA_REG 0xCD7 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun /* For SP5100/SB7x0 chipset */ 37*4882a593Smuzhiyun #define SP5100_SB_RESOURCE_MMIO_BASE 0x9C 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun #define SP5100_PM_WATCHDOG_CONTROL 0x69 40*4882a593Smuzhiyun #define SP5100_PM_WATCHDOG_BASE 0x6C 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun #define SP5100_PCI_WATCHDOG_MISC_REG 0x41 43*4882a593Smuzhiyun #define SP5100_PCI_WATCHDOG_DECODE_EN BIT(3) 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun #define SP5100_PM_WATCHDOG_DISABLE ((u8)BIT(0)) 46*4882a593Smuzhiyun #define SP5100_PM_WATCHDOG_SECOND_RES GENMASK(2, 1) 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun #define SP5100_DEVNAME "SP5100 TCO" 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun /* For SB8x0(or later) chipset */ 51*4882a593Smuzhiyun #define SB800_PM_ACPI_MMIO_EN 0x24 52*4882a593Smuzhiyun #define SB800_PM_WATCHDOG_CONTROL 0x48 53*4882a593Smuzhiyun #define SB800_PM_WATCHDOG_BASE 0x48 54*4882a593Smuzhiyun #define SB800_PM_WATCHDOG_CONFIG 0x4C 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun #define SB800_PCI_WATCHDOG_DECODE_EN BIT(0) 57*4882a593Smuzhiyun #define SB800_PM_WATCHDOG_DISABLE ((u8)BIT(1)) 58*4882a593Smuzhiyun #define SB800_PM_WATCHDOG_SECOND_RES GENMASK(1, 0) 59*4882a593Smuzhiyun #define SB800_ACPI_MMIO_DECODE_EN BIT(0) 60*4882a593Smuzhiyun #define SB800_ACPI_MMIO_SEL BIT(1) 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun #define SB800_PM_WDT_MMIO_OFFSET 0xB00 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun #define SB800_DEVNAME "SB800 TCO" 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun /* For recent chips with embedded FCH (rev 40+) */ 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun #define EFCH_PM_DECODEEN 0x00 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun #define EFCH_PM_DECODEEN_WDT_TMREN BIT(7) 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun #define EFCH_PM_DECODEEN3 0x03 74*4882a593Smuzhiyun #define EFCH_PM_DECODEEN_SECOND_RES GENMASK(1, 0) 75*4882a593Smuzhiyun #define EFCH_PM_WATCHDOG_DISABLE ((u8)GENMASK(3, 2)) 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun /* WDT MMIO if enabled with PM00_DECODEEN_WDT_TMREN */ 78*4882a593Smuzhiyun #define EFCH_PM_WDT_ADDR 0xfeb00000 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun #define EFCH_PM_ISACONTROL 0x04 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun #define EFCH_PM_ISACONTROL_MMIOEN BIT(1) 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun #define EFCH_PM_ACPI_MMIO_ADDR 0xfed80000 85*4882a593Smuzhiyun #define EFCH_PM_ACPI_MMIO_WDT_OFFSET 0x00000b00 86