xref: /OK3568_Linux_fs/kernel/drivers/watchdog/sch311x_wdt.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0+
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  *	sch311x_wdt.c - Driver for the SCH311x Super-I/O chips
4*4882a593Smuzhiyun  *			integrated watchdog.
5*4882a593Smuzhiyun  *
6*4882a593Smuzhiyun  *	(c) Copyright 2008 Wim Van Sebroeck <wim@iguana.be>.
7*4882a593Smuzhiyun  *
8*4882a593Smuzhiyun  *	Neither Wim Van Sebroeck nor Iguana vzw. admit liability nor
9*4882a593Smuzhiyun  *	provide warranty for any of this software. This material is
10*4882a593Smuzhiyun  *	provided "AS-IS" and at no charge.
11*4882a593Smuzhiyun  */
12*4882a593Smuzhiyun 
13*4882a593Smuzhiyun /*
14*4882a593Smuzhiyun  *	Includes, defines, variables, module parameters, ...
15*4882a593Smuzhiyun  */
16*4882a593Smuzhiyun 
17*4882a593Smuzhiyun #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
18*4882a593Smuzhiyun 
19*4882a593Smuzhiyun /* Includes */
20*4882a593Smuzhiyun #include <linux/module.h>		/* For module specific items */
21*4882a593Smuzhiyun #include <linux/moduleparam.h>		/* For new moduleparam's */
22*4882a593Smuzhiyun #include <linux/types.h>		/* For standard types (like size_t) */
23*4882a593Smuzhiyun #include <linux/errno.h>		/* For the -ENODEV/... values */
24*4882a593Smuzhiyun #include <linux/kernel.h>		/* For printk/... */
25*4882a593Smuzhiyun #include <linux/miscdevice.h>		/* For struct miscdevice */
26*4882a593Smuzhiyun #include <linux/watchdog.h>		/* For the watchdog specific items */
27*4882a593Smuzhiyun #include <linux/init.h>			/* For __init/__exit/... */
28*4882a593Smuzhiyun #include <linux/fs.h>			/* For file operations */
29*4882a593Smuzhiyun #include <linux/platform_device.h>	/* For platform_driver framework */
30*4882a593Smuzhiyun #include <linux/ioport.h>		/* For io-port access */
31*4882a593Smuzhiyun #include <linux/spinlock.h>		/* For spin_lock/spin_unlock/... */
32*4882a593Smuzhiyun #include <linux/uaccess.h>		/* For copy_to_user/put_user/... */
33*4882a593Smuzhiyun #include <linux/io.h>			/* For inb/outb/... */
34*4882a593Smuzhiyun 
35*4882a593Smuzhiyun /* Module and version information */
36*4882a593Smuzhiyun #define DRV_NAME	"sch311x_wdt"
37*4882a593Smuzhiyun 
38*4882a593Smuzhiyun /* Runtime registers */
39*4882a593Smuzhiyun #define GP60			0x47
40*4882a593Smuzhiyun #define WDT_TIME_OUT		0x65
41*4882a593Smuzhiyun #define WDT_VAL			0x66
42*4882a593Smuzhiyun #define WDT_CFG			0x67
43*4882a593Smuzhiyun #define WDT_CTRL		0x68
44*4882a593Smuzhiyun 
45*4882a593Smuzhiyun /* internal variables */
46*4882a593Smuzhiyun static unsigned long sch311x_wdt_is_open;
47*4882a593Smuzhiyun static char sch311x_wdt_expect_close;
48*4882a593Smuzhiyun static struct platform_device *sch311x_wdt_pdev;
49*4882a593Smuzhiyun 
50*4882a593Smuzhiyun static int sch311x_ioports[] = { 0x2e, 0x4e, 0x162e, 0x164e, 0x00 };
51*4882a593Smuzhiyun 
52*4882a593Smuzhiyun static struct {	/* The devices private data */
53*4882a593Smuzhiyun 	/* the Runtime Register base address */
54*4882a593Smuzhiyun 	unsigned short runtime_reg;
55*4882a593Smuzhiyun 	/* The card's boot status */
56*4882a593Smuzhiyun 	int boot_status;
57*4882a593Smuzhiyun 	/* the lock for io operations */
58*4882a593Smuzhiyun 	spinlock_t io_lock;
59*4882a593Smuzhiyun } sch311x_wdt_data;
60*4882a593Smuzhiyun 
61*4882a593Smuzhiyun /* Module load parameters */
62*4882a593Smuzhiyun static unsigned short force_id;
63*4882a593Smuzhiyun module_param(force_id, ushort, 0);
64*4882a593Smuzhiyun MODULE_PARM_DESC(force_id, "Override the detected device ID");
65*4882a593Smuzhiyun 
66*4882a593Smuzhiyun #define WATCHDOG_TIMEOUT 60		/* 60 sec default timeout */
67*4882a593Smuzhiyun static int timeout = WATCHDOG_TIMEOUT;	/* in seconds */
68*4882a593Smuzhiyun module_param(timeout, int, 0);
69*4882a593Smuzhiyun MODULE_PARM_DESC(timeout,
70*4882a593Smuzhiyun 	"Watchdog timeout in seconds. 1<= timeout <=15300, default="
71*4882a593Smuzhiyun 		__MODULE_STRING(WATCHDOG_TIMEOUT) ".");
72*4882a593Smuzhiyun 
73*4882a593Smuzhiyun static bool nowayout = WATCHDOG_NOWAYOUT;
74*4882a593Smuzhiyun module_param(nowayout, bool, 0);
75*4882a593Smuzhiyun MODULE_PARM_DESC(nowayout,
76*4882a593Smuzhiyun 	"Watchdog cannot be stopped once started (default="
77*4882a593Smuzhiyun 		__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
78*4882a593Smuzhiyun 
79*4882a593Smuzhiyun /*
80*4882a593Smuzhiyun  *	Super-IO functions
81*4882a593Smuzhiyun  */
82*4882a593Smuzhiyun 
sch311x_sio_enter(int sio_config_port)83*4882a593Smuzhiyun static inline void sch311x_sio_enter(int sio_config_port)
84*4882a593Smuzhiyun {
85*4882a593Smuzhiyun 	outb(0x55, sio_config_port);
86*4882a593Smuzhiyun }
87*4882a593Smuzhiyun 
sch311x_sio_exit(int sio_config_port)88*4882a593Smuzhiyun static inline void sch311x_sio_exit(int sio_config_port)
89*4882a593Smuzhiyun {
90*4882a593Smuzhiyun 	outb(0xaa, sio_config_port);
91*4882a593Smuzhiyun }
92*4882a593Smuzhiyun 
sch311x_sio_inb(int sio_config_port,int reg)93*4882a593Smuzhiyun static inline int sch311x_sio_inb(int sio_config_port, int reg)
94*4882a593Smuzhiyun {
95*4882a593Smuzhiyun 	outb(reg, sio_config_port);
96*4882a593Smuzhiyun 	return inb(sio_config_port + 1);
97*4882a593Smuzhiyun }
98*4882a593Smuzhiyun 
sch311x_sio_outb(int sio_config_port,int reg,int val)99*4882a593Smuzhiyun static inline void sch311x_sio_outb(int sio_config_port, int reg, int val)
100*4882a593Smuzhiyun {
101*4882a593Smuzhiyun 	outb(reg, sio_config_port);
102*4882a593Smuzhiyun 	outb(val, sio_config_port + 1);
103*4882a593Smuzhiyun }
104*4882a593Smuzhiyun 
105*4882a593Smuzhiyun /*
106*4882a593Smuzhiyun  *	Watchdog Operations
107*4882a593Smuzhiyun  */
108*4882a593Smuzhiyun 
sch311x_wdt_set_timeout(int t)109*4882a593Smuzhiyun static void sch311x_wdt_set_timeout(int t)
110*4882a593Smuzhiyun {
111*4882a593Smuzhiyun 	unsigned char timeout_unit = 0x80;
112*4882a593Smuzhiyun 
113*4882a593Smuzhiyun 	/* When new timeout is bigger then 255 seconds, we will use minutes */
114*4882a593Smuzhiyun 	if (t > 255) {
115*4882a593Smuzhiyun 		timeout_unit = 0;
116*4882a593Smuzhiyun 		t /= 60;
117*4882a593Smuzhiyun 	}
118*4882a593Smuzhiyun 
119*4882a593Smuzhiyun 	/* -- Watchdog Timeout --
120*4882a593Smuzhiyun 	 * Bit 0-6 (Reserved)
121*4882a593Smuzhiyun 	 * Bit 7   WDT Time-out Value Units Select
122*4882a593Smuzhiyun 	 *         (0 = Minutes, 1 = Seconds)
123*4882a593Smuzhiyun 	 */
124*4882a593Smuzhiyun 	outb(timeout_unit, sch311x_wdt_data.runtime_reg + WDT_TIME_OUT);
125*4882a593Smuzhiyun 
126*4882a593Smuzhiyun 	/* -- Watchdog Timer Time-out Value --
127*4882a593Smuzhiyun 	 * Bit 0-7 Binary coded units (0=Disabled, 1..255)
128*4882a593Smuzhiyun 	 */
129*4882a593Smuzhiyun 	outb(t, sch311x_wdt_data.runtime_reg + WDT_VAL);
130*4882a593Smuzhiyun }
131*4882a593Smuzhiyun 
sch311x_wdt_start(void)132*4882a593Smuzhiyun static void sch311x_wdt_start(void)
133*4882a593Smuzhiyun {
134*4882a593Smuzhiyun 	unsigned char t;
135*4882a593Smuzhiyun 
136*4882a593Smuzhiyun 	spin_lock(&sch311x_wdt_data.io_lock);
137*4882a593Smuzhiyun 
138*4882a593Smuzhiyun 	/* set watchdog's timeout */
139*4882a593Smuzhiyun 	sch311x_wdt_set_timeout(timeout);
140*4882a593Smuzhiyun 	/* enable the watchdog */
141*4882a593Smuzhiyun 	/* -- General Purpose I/O Bit 6.0 --
142*4882a593Smuzhiyun 	 * Bit 0,   In/Out: 0 = Output, 1 = Input
143*4882a593Smuzhiyun 	 * Bit 1,   Polarity: 0 = No Invert, 1 = Invert
144*4882a593Smuzhiyun 	 * Bit 2-3, Function select: 00 = GPI/O, 01 = LED1, 11 = WDT,
145*4882a593Smuzhiyun 	 *                           10 = Either Edge Triggered Intr.4
146*4882a593Smuzhiyun 	 * Bit 4-6  (Reserved)
147*4882a593Smuzhiyun 	 * Bit 7,   Output Type: 0 = Push Pull Bit, 1 = Open Drain
148*4882a593Smuzhiyun 	 */
149*4882a593Smuzhiyun 	t = inb(sch311x_wdt_data.runtime_reg + GP60);
150*4882a593Smuzhiyun 	outb((t & ~0x0d) | 0x0c, sch311x_wdt_data.runtime_reg + GP60);
151*4882a593Smuzhiyun 
152*4882a593Smuzhiyun 	spin_unlock(&sch311x_wdt_data.io_lock);
153*4882a593Smuzhiyun 
154*4882a593Smuzhiyun }
155*4882a593Smuzhiyun 
sch311x_wdt_stop(void)156*4882a593Smuzhiyun static void sch311x_wdt_stop(void)
157*4882a593Smuzhiyun {
158*4882a593Smuzhiyun 	unsigned char t;
159*4882a593Smuzhiyun 
160*4882a593Smuzhiyun 	spin_lock(&sch311x_wdt_data.io_lock);
161*4882a593Smuzhiyun 
162*4882a593Smuzhiyun 	/* stop the watchdog */
163*4882a593Smuzhiyun 	t = inb(sch311x_wdt_data.runtime_reg + GP60);
164*4882a593Smuzhiyun 	outb((t & ~0x0d) | 0x01, sch311x_wdt_data.runtime_reg + GP60);
165*4882a593Smuzhiyun 	/* disable timeout by setting it to 0 */
166*4882a593Smuzhiyun 	sch311x_wdt_set_timeout(0);
167*4882a593Smuzhiyun 
168*4882a593Smuzhiyun 	spin_unlock(&sch311x_wdt_data.io_lock);
169*4882a593Smuzhiyun }
170*4882a593Smuzhiyun 
sch311x_wdt_keepalive(void)171*4882a593Smuzhiyun static void sch311x_wdt_keepalive(void)
172*4882a593Smuzhiyun {
173*4882a593Smuzhiyun 	spin_lock(&sch311x_wdt_data.io_lock);
174*4882a593Smuzhiyun 	sch311x_wdt_set_timeout(timeout);
175*4882a593Smuzhiyun 	spin_unlock(&sch311x_wdt_data.io_lock);
176*4882a593Smuzhiyun }
177*4882a593Smuzhiyun 
sch311x_wdt_set_heartbeat(int t)178*4882a593Smuzhiyun static int sch311x_wdt_set_heartbeat(int t)
179*4882a593Smuzhiyun {
180*4882a593Smuzhiyun 	if (t < 1 || t > (255*60))
181*4882a593Smuzhiyun 		return -EINVAL;
182*4882a593Smuzhiyun 
183*4882a593Smuzhiyun 	/* When new timeout is bigger then 255 seconds,
184*4882a593Smuzhiyun 	 * we will round up to minutes (with a max of 255) */
185*4882a593Smuzhiyun 	if (t > 255)
186*4882a593Smuzhiyun 		t = (((t - 1) / 60) + 1) * 60;
187*4882a593Smuzhiyun 
188*4882a593Smuzhiyun 	timeout = t;
189*4882a593Smuzhiyun 	return 0;
190*4882a593Smuzhiyun }
191*4882a593Smuzhiyun 
sch311x_wdt_get_status(int * status)192*4882a593Smuzhiyun static void sch311x_wdt_get_status(int *status)
193*4882a593Smuzhiyun {
194*4882a593Smuzhiyun 	unsigned char new_status;
195*4882a593Smuzhiyun 
196*4882a593Smuzhiyun 	*status = 0;
197*4882a593Smuzhiyun 
198*4882a593Smuzhiyun 	spin_lock(&sch311x_wdt_data.io_lock);
199*4882a593Smuzhiyun 
200*4882a593Smuzhiyun 	/* -- Watchdog timer control --
201*4882a593Smuzhiyun 	 * Bit 0   Status Bit: 0 = Timer counting, 1 = Timeout occurred
202*4882a593Smuzhiyun 	 * Bit 1   Reserved
203*4882a593Smuzhiyun 	 * Bit 2   Force Timeout: 1 = Forces WD timeout event (self-cleaning)
204*4882a593Smuzhiyun 	 * Bit 3   P20 Force Timeout enabled:
205*4882a593Smuzhiyun 	 *          0 = P20 activity does not generate the WD timeout event
206*4882a593Smuzhiyun 	 *          1 = P20 Allows rising edge of P20, from the keyboard
207*4882a593Smuzhiyun 	 *              controller, to force the WD timeout event.
208*4882a593Smuzhiyun 	 * Bit 4-7 Reserved
209*4882a593Smuzhiyun 	 */
210*4882a593Smuzhiyun 	new_status = inb(sch311x_wdt_data.runtime_reg + WDT_CTRL);
211*4882a593Smuzhiyun 	if (new_status & 0x01)
212*4882a593Smuzhiyun 		*status |= WDIOF_CARDRESET;
213*4882a593Smuzhiyun 
214*4882a593Smuzhiyun 	spin_unlock(&sch311x_wdt_data.io_lock);
215*4882a593Smuzhiyun }
216*4882a593Smuzhiyun 
217*4882a593Smuzhiyun /*
218*4882a593Smuzhiyun  *	/dev/watchdog handling
219*4882a593Smuzhiyun  */
220*4882a593Smuzhiyun 
sch311x_wdt_write(struct file * file,const char __user * buf,size_t count,loff_t * ppos)221*4882a593Smuzhiyun static ssize_t sch311x_wdt_write(struct file *file, const char __user *buf,
222*4882a593Smuzhiyun 						size_t count, loff_t *ppos)
223*4882a593Smuzhiyun {
224*4882a593Smuzhiyun 	if (count) {
225*4882a593Smuzhiyun 		if (!nowayout) {
226*4882a593Smuzhiyun 			size_t i;
227*4882a593Smuzhiyun 
228*4882a593Smuzhiyun 			sch311x_wdt_expect_close = 0;
229*4882a593Smuzhiyun 
230*4882a593Smuzhiyun 			for (i = 0; i != count; i++) {
231*4882a593Smuzhiyun 				char c;
232*4882a593Smuzhiyun 				if (get_user(c, buf + i))
233*4882a593Smuzhiyun 					return -EFAULT;
234*4882a593Smuzhiyun 				if (c == 'V')
235*4882a593Smuzhiyun 					sch311x_wdt_expect_close = 42;
236*4882a593Smuzhiyun 			}
237*4882a593Smuzhiyun 		}
238*4882a593Smuzhiyun 		sch311x_wdt_keepalive();
239*4882a593Smuzhiyun 	}
240*4882a593Smuzhiyun 	return count;
241*4882a593Smuzhiyun }
242*4882a593Smuzhiyun 
sch311x_wdt_ioctl(struct file * file,unsigned int cmd,unsigned long arg)243*4882a593Smuzhiyun static long sch311x_wdt_ioctl(struct file *file, unsigned int cmd,
244*4882a593Smuzhiyun 							unsigned long arg)
245*4882a593Smuzhiyun {
246*4882a593Smuzhiyun 	int status;
247*4882a593Smuzhiyun 	int new_timeout;
248*4882a593Smuzhiyun 	void __user *argp = (void __user *)arg;
249*4882a593Smuzhiyun 	int __user *p = argp;
250*4882a593Smuzhiyun 	static const struct watchdog_info ident = {
251*4882a593Smuzhiyun 		.options		= WDIOF_KEEPALIVEPING |
252*4882a593Smuzhiyun 					  WDIOF_SETTIMEOUT |
253*4882a593Smuzhiyun 					  WDIOF_MAGICCLOSE,
254*4882a593Smuzhiyun 		.firmware_version	= 1,
255*4882a593Smuzhiyun 		.identity		= DRV_NAME,
256*4882a593Smuzhiyun 	};
257*4882a593Smuzhiyun 
258*4882a593Smuzhiyun 	switch (cmd) {
259*4882a593Smuzhiyun 	case WDIOC_GETSUPPORT:
260*4882a593Smuzhiyun 		if (copy_to_user(argp, &ident, sizeof(ident)))
261*4882a593Smuzhiyun 			return -EFAULT;
262*4882a593Smuzhiyun 		break;
263*4882a593Smuzhiyun 
264*4882a593Smuzhiyun 	case WDIOC_GETSTATUS:
265*4882a593Smuzhiyun 	{
266*4882a593Smuzhiyun 		sch311x_wdt_get_status(&status);
267*4882a593Smuzhiyun 		return put_user(status, p);
268*4882a593Smuzhiyun 	}
269*4882a593Smuzhiyun 	case WDIOC_GETBOOTSTATUS:
270*4882a593Smuzhiyun 		return put_user(sch311x_wdt_data.boot_status, p);
271*4882a593Smuzhiyun 
272*4882a593Smuzhiyun 	case WDIOC_SETOPTIONS:
273*4882a593Smuzhiyun 	{
274*4882a593Smuzhiyun 		int options, retval = -EINVAL;
275*4882a593Smuzhiyun 
276*4882a593Smuzhiyun 		if (get_user(options, p))
277*4882a593Smuzhiyun 			return -EFAULT;
278*4882a593Smuzhiyun 		if (options & WDIOS_DISABLECARD) {
279*4882a593Smuzhiyun 			sch311x_wdt_stop();
280*4882a593Smuzhiyun 			retval = 0;
281*4882a593Smuzhiyun 		}
282*4882a593Smuzhiyun 		if (options & WDIOS_ENABLECARD) {
283*4882a593Smuzhiyun 			sch311x_wdt_start();
284*4882a593Smuzhiyun 			retval = 0;
285*4882a593Smuzhiyun 		}
286*4882a593Smuzhiyun 		return retval;
287*4882a593Smuzhiyun 	}
288*4882a593Smuzhiyun 	case WDIOC_KEEPALIVE:
289*4882a593Smuzhiyun 		sch311x_wdt_keepalive();
290*4882a593Smuzhiyun 		break;
291*4882a593Smuzhiyun 
292*4882a593Smuzhiyun 	case WDIOC_SETTIMEOUT:
293*4882a593Smuzhiyun 		if (get_user(new_timeout, p))
294*4882a593Smuzhiyun 			return -EFAULT;
295*4882a593Smuzhiyun 		if (sch311x_wdt_set_heartbeat(new_timeout))
296*4882a593Smuzhiyun 			return -EINVAL;
297*4882a593Smuzhiyun 		sch311x_wdt_keepalive();
298*4882a593Smuzhiyun 		fallthrough;
299*4882a593Smuzhiyun 	case WDIOC_GETTIMEOUT:
300*4882a593Smuzhiyun 		return put_user(timeout, p);
301*4882a593Smuzhiyun 	default:
302*4882a593Smuzhiyun 		return -ENOTTY;
303*4882a593Smuzhiyun 	}
304*4882a593Smuzhiyun 	return 0;
305*4882a593Smuzhiyun }
306*4882a593Smuzhiyun 
sch311x_wdt_open(struct inode * inode,struct file * file)307*4882a593Smuzhiyun static int sch311x_wdt_open(struct inode *inode, struct file *file)
308*4882a593Smuzhiyun {
309*4882a593Smuzhiyun 	if (test_and_set_bit(0, &sch311x_wdt_is_open))
310*4882a593Smuzhiyun 		return -EBUSY;
311*4882a593Smuzhiyun 	/*
312*4882a593Smuzhiyun 	 *	Activate
313*4882a593Smuzhiyun 	 */
314*4882a593Smuzhiyun 	sch311x_wdt_start();
315*4882a593Smuzhiyun 	return stream_open(inode, file);
316*4882a593Smuzhiyun }
317*4882a593Smuzhiyun 
sch311x_wdt_close(struct inode * inode,struct file * file)318*4882a593Smuzhiyun static int sch311x_wdt_close(struct inode *inode, struct file *file)
319*4882a593Smuzhiyun {
320*4882a593Smuzhiyun 	if (sch311x_wdt_expect_close == 42) {
321*4882a593Smuzhiyun 		sch311x_wdt_stop();
322*4882a593Smuzhiyun 	} else {
323*4882a593Smuzhiyun 		pr_crit("Unexpected close, not stopping watchdog!\n");
324*4882a593Smuzhiyun 		sch311x_wdt_keepalive();
325*4882a593Smuzhiyun 	}
326*4882a593Smuzhiyun 	clear_bit(0, &sch311x_wdt_is_open);
327*4882a593Smuzhiyun 	sch311x_wdt_expect_close = 0;
328*4882a593Smuzhiyun 	return 0;
329*4882a593Smuzhiyun }
330*4882a593Smuzhiyun 
331*4882a593Smuzhiyun /*
332*4882a593Smuzhiyun  *	Kernel Interfaces
333*4882a593Smuzhiyun  */
334*4882a593Smuzhiyun 
335*4882a593Smuzhiyun static const struct file_operations sch311x_wdt_fops = {
336*4882a593Smuzhiyun 	.owner		= THIS_MODULE,
337*4882a593Smuzhiyun 	.llseek		= no_llseek,
338*4882a593Smuzhiyun 	.write		= sch311x_wdt_write,
339*4882a593Smuzhiyun 	.unlocked_ioctl	= sch311x_wdt_ioctl,
340*4882a593Smuzhiyun 	.compat_ioctl	= compat_ptr_ioctl,
341*4882a593Smuzhiyun 	.open		= sch311x_wdt_open,
342*4882a593Smuzhiyun 	.release	= sch311x_wdt_close,
343*4882a593Smuzhiyun };
344*4882a593Smuzhiyun 
345*4882a593Smuzhiyun static struct miscdevice sch311x_wdt_miscdev = {
346*4882a593Smuzhiyun 	.minor	= WATCHDOG_MINOR,
347*4882a593Smuzhiyun 	.name	= "watchdog",
348*4882a593Smuzhiyun 	.fops	= &sch311x_wdt_fops,
349*4882a593Smuzhiyun };
350*4882a593Smuzhiyun 
351*4882a593Smuzhiyun /*
352*4882a593Smuzhiyun  *	Init & exit routines
353*4882a593Smuzhiyun  */
354*4882a593Smuzhiyun 
sch311x_wdt_probe(struct platform_device * pdev)355*4882a593Smuzhiyun static int sch311x_wdt_probe(struct platform_device *pdev)
356*4882a593Smuzhiyun {
357*4882a593Smuzhiyun 	struct device *dev = &pdev->dev;
358*4882a593Smuzhiyun 	int err;
359*4882a593Smuzhiyun 
360*4882a593Smuzhiyun 	spin_lock_init(&sch311x_wdt_data.io_lock);
361*4882a593Smuzhiyun 
362*4882a593Smuzhiyun 	if (!request_region(sch311x_wdt_data.runtime_reg + GP60, 1, DRV_NAME)) {
363*4882a593Smuzhiyun 		dev_err(dev, "Failed to request region 0x%04x-0x%04x.\n",
364*4882a593Smuzhiyun 			sch311x_wdt_data.runtime_reg + GP60,
365*4882a593Smuzhiyun 			sch311x_wdt_data.runtime_reg + GP60);
366*4882a593Smuzhiyun 		err = -EBUSY;
367*4882a593Smuzhiyun 		goto exit;
368*4882a593Smuzhiyun 	}
369*4882a593Smuzhiyun 
370*4882a593Smuzhiyun 	if (!request_region(sch311x_wdt_data.runtime_reg + WDT_TIME_OUT, 4,
371*4882a593Smuzhiyun 								DRV_NAME)) {
372*4882a593Smuzhiyun 		dev_err(dev, "Failed to request region 0x%04x-0x%04x.\n",
373*4882a593Smuzhiyun 			sch311x_wdt_data.runtime_reg + WDT_TIME_OUT,
374*4882a593Smuzhiyun 			sch311x_wdt_data.runtime_reg + WDT_CTRL);
375*4882a593Smuzhiyun 		err = -EBUSY;
376*4882a593Smuzhiyun 		goto exit_release_region;
377*4882a593Smuzhiyun 	}
378*4882a593Smuzhiyun 
379*4882a593Smuzhiyun 	/* Make sure that the watchdog is not running */
380*4882a593Smuzhiyun 	sch311x_wdt_stop();
381*4882a593Smuzhiyun 
382*4882a593Smuzhiyun 	/* Disable keyboard and mouse interaction and interrupt */
383*4882a593Smuzhiyun 	/* -- Watchdog timer configuration --
384*4882a593Smuzhiyun 	 * Bit 0   Reserved
385*4882a593Smuzhiyun 	 * Bit 1   Keyboard enable: 0* = No Reset, 1 = Reset WDT upon KBD Intr.
386*4882a593Smuzhiyun 	 * Bit 2   Mouse enable: 0* = No Reset, 1 = Reset WDT upon Mouse Intr
387*4882a593Smuzhiyun 	 * Bit 3   Reserved
388*4882a593Smuzhiyun 	 * Bit 4-7 WDT Interrupt Mapping: (0000* = Disabled,
389*4882a593Smuzhiyun 	 *            0001=IRQ1, 0010=(Invalid), 0011=IRQ3 to 1111=IRQ15)
390*4882a593Smuzhiyun 	 */
391*4882a593Smuzhiyun 	outb(0, sch311x_wdt_data.runtime_reg + WDT_CFG);
392*4882a593Smuzhiyun 
393*4882a593Smuzhiyun 	/* Check that the heartbeat value is within it's range ;
394*4882a593Smuzhiyun 	 * if not reset to the default */
395*4882a593Smuzhiyun 	if (sch311x_wdt_set_heartbeat(timeout)) {
396*4882a593Smuzhiyun 		sch311x_wdt_set_heartbeat(WATCHDOG_TIMEOUT);
397*4882a593Smuzhiyun 		dev_info(dev, "timeout value must be 1<=x<=15300, using %d\n",
398*4882a593Smuzhiyun 			timeout);
399*4882a593Smuzhiyun 	}
400*4882a593Smuzhiyun 
401*4882a593Smuzhiyun 	/* Get status at boot */
402*4882a593Smuzhiyun 	sch311x_wdt_get_status(&sch311x_wdt_data.boot_status);
403*4882a593Smuzhiyun 
404*4882a593Smuzhiyun 	sch311x_wdt_miscdev.parent = dev;
405*4882a593Smuzhiyun 
406*4882a593Smuzhiyun 	err = misc_register(&sch311x_wdt_miscdev);
407*4882a593Smuzhiyun 	if (err != 0) {
408*4882a593Smuzhiyun 		dev_err(dev, "cannot register miscdev on minor=%d (err=%d)\n",
409*4882a593Smuzhiyun 							WATCHDOG_MINOR, err);
410*4882a593Smuzhiyun 		goto exit_release_region2;
411*4882a593Smuzhiyun 	}
412*4882a593Smuzhiyun 
413*4882a593Smuzhiyun 	dev_info(dev,
414*4882a593Smuzhiyun 		"SMSC SCH311x WDT initialized. timeout=%d sec (nowayout=%d)\n",
415*4882a593Smuzhiyun 		timeout, nowayout);
416*4882a593Smuzhiyun 
417*4882a593Smuzhiyun 	return 0;
418*4882a593Smuzhiyun 
419*4882a593Smuzhiyun exit_release_region2:
420*4882a593Smuzhiyun 	release_region(sch311x_wdt_data.runtime_reg + WDT_TIME_OUT, 4);
421*4882a593Smuzhiyun exit_release_region:
422*4882a593Smuzhiyun 	release_region(sch311x_wdt_data.runtime_reg + GP60, 1);
423*4882a593Smuzhiyun 	sch311x_wdt_data.runtime_reg = 0;
424*4882a593Smuzhiyun exit:
425*4882a593Smuzhiyun 	return err;
426*4882a593Smuzhiyun }
427*4882a593Smuzhiyun 
sch311x_wdt_remove(struct platform_device * pdev)428*4882a593Smuzhiyun static int sch311x_wdt_remove(struct platform_device *pdev)
429*4882a593Smuzhiyun {
430*4882a593Smuzhiyun 	/* Stop the timer before we leave */
431*4882a593Smuzhiyun 	if (!nowayout)
432*4882a593Smuzhiyun 		sch311x_wdt_stop();
433*4882a593Smuzhiyun 
434*4882a593Smuzhiyun 	/* Deregister */
435*4882a593Smuzhiyun 	misc_deregister(&sch311x_wdt_miscdev);
436*4882a593Smuzhiyun 	release_region(sch311x_wdt_data.runtime_reg + WDT_TIME_OUT, 4);
437*4882a593Smuzhiyun 	release_region(sch311x_wdt_data.runtime_reg + GP60, 1);
438*4882a593Smuzhiyun 	sch311x_wdt_data.runtime_reg = 0;
439*4882a593Smuzhiyun 	return 0;
440*4882a593Smuzhiyun }
441*4882a593Smuzhiyun 
sch311x_wdt_shutdown(struct platform_device * dev)442*4882a593Smuzhiyun static void sch311x_wdt_shutdown(struct platform_device *dev)
443*4882a593Smuzhiyun {
444*4882a593Smuzhiyun 	/* Turn the WDT off if we have a soft shutdown */
445*4882a593Smuzhiyun 	sch311x_wdt_stop();
446*4882a593Smuzhiyun }
447*4882a593Smuzhiyun 
448*4882a593Smuzhiyun static struct platform_driver sch311x_wdt_driver = {
449*4882a593Smuzhiyun 	.probe		= sch311x_wdt_probe,
450*4882a593Smuzhiyun 	.remove		= sch311x_wdt_remove,
451*4882a593Smuzhiyun 	.shutdown	= sch311x_wdt_shutdown,
452*4882a593Smuzhiyun 	.driver		= {
453*4882a593Smuzhiyun 		.name = DRV_NAME,
454*4882a593Smuzhiyun 	},
455*4882a593Smuzhiyun };
456*4882a593Smuzhiyun 
sch311x_detect(int sio_config_port,unsigned short * addr)457*4882a593Smuzhiyun static int __init sch311x_detect(int sio_config_port, unsigned short *addr)
458*4882a593Smuzhiyun {
459*4882a593Smuzhiyun 	int err = 0, reg;
460*4882a593Smuzhiyun 	unsigned short base_addr;
461*4882a593Smuzhiyun 	unsigned char dev_id;
462*4882a593Smuzhiyun 
463*4882a593Smuzhiyun 	sch311x_sio_enter(sio_config_port);
464*4882a593Smuzhiyun 
465*4882a593Smuzhiyun 	/* Check device ID. We currently know about:
466*4882a593Smuzhiyun 	 * SCH3112 (0x7c), SCH3114 (0x7d), and SCH3116 (0x7f). */
467*4882a593Smuzhiyun 	reg = force_id ? force_id : sch311x_sio_inb(sio_config_port, 0x20);
468*4882a593Smuzhiyun 	if (!(reg == 0x7c || reg == 0x7d || reg == 0x7f)) {
469*4882a593Smuzhiyun 		err = -ENODEV;
470*4882a593Smuzhiyun 		goto exit;
471*4882a593Smuzhiyun 	}
472*4882a593Smuzhiyun 	dev_id = reg == 0x7c ? 2 : reg == 0x7d ? 4 : 6;
473*4882a593Smuzhiyun 
474*4882a593Smuzhiyun 	/* Select logical device A (runtime registers) */
475*4882a593Smuzhiyun 	sch311x_sio_outb(sio_config_port, 0x07, 0x0a);
476*4882a593Smuzhiyun 
477*4882a593Smuzhiyun 	/* Check if Logical Device Register is currently active */
478*4882a593Smuzhiyun 	if ((sch311x_sio_inb(sio_config_port, 0x30) & 0x01) == 0)
479*4882a593Smuzhiyun 		pr_info("Seems that LDN 0x0a is not active...\n");
480*4882a593Smuzhiyun 
481*4882a593Smuzhiyun 	/* Get the base address of the runtime registers */
482*4882a593Smuzhiyun 	base_addr = (sch311x_sio_inb(sio_config_port, 0x60) << 8) |
483*4882a593Smuzhiyun 			   sch311x_sio_inb(sio_config_port, 0x61);
484*4882a593Smuzhiyun 	if (!base_addr) {
485*4882a593Smuzhiyun 		pr_err("Base address not set\n");
486*4882a593Smuzhiyun 		err = -ENODEV;
487*4882a593Smuzhiyun 		goto exit;
488*4882a593Smuzhiyun 	}
489*4882a593Smuzhiyun 	*addr = base_addr;
490*4882a593Smuzhiyun 
491*4882a593Smuzhiyun 	pr_info("Found an SMSC SCH311%d chip at 0x%04x\n", dev_id, base_addr);
492*4882a593Smuzhiyun 
493*4882a593Smuzhiyun exit:
494*4882a593Smuzhiyun 	sch311x_sio_exit(sio_config_port);
495*4882a593Smuzhiyun 	return err;
496*4882a593Smuzhiyun }
497*4882a593Smuzhiyun 
sch311x_wdt_init(void)498*4882a593Smuzhiyun static int __init sch311x_wdt_init(void)
499*4882a593Smuzhiyun {
500*4882a593Smuzhiyun 	int err, i, found = 0;
501*4882a593Smuzhiyun 	unsigned short addr = 0;
502*4882a593Smuzhiyun 
503*4882a593Smuzhiyun 	for (i = 0; !found && sch311x_ioports[i]; i++)
504*4882a593Smuzhiyun 		if (sch311x_detect(sch311x_ioports[i], &addr) == 0)
505*4882a593Smuzhiyun 			found++;
506*4882a593Smuzhiyun 
507*4882a593Smuzhiyun 	if (!found)
508*4882a593Smuzhiyun 		return -ENODEV;
509*4882a593Smuzhiyun 
510*4882a593Smuzhiyun 	sch311x_wdt_data.runtime_reg = addr;
511*4882a593Smuzhiyun 
512*4882a593Smuzhiyun 	err = platform_driver_register(&sch311x_wdt_driver);
513*4882a593Smuzhiyun 	if (err)
514*4882a593Smuzhiyun 		return err;
515*4882a593Smuzhiyun 
516*4882a593Smuzhiyun 	sch311x_wdt_pdev = platform_device_register_simple(DRV_NAME, addr,
517*4882a593Smuzhiyun 								NULL, 0);
518*4882a593Smuzhiyun 
519*4882a593Smuzhiyun 	if (IS_ERR(sch311x_wdt_pdev)) {
520*4882a593Smuzhiyun 		err = PTR_ERR(sch311x_wdt_pdev);
521*4882a593Smuzhiyun 		goto unreg_platform_driver;
522*4882a593Smuzhiyun 	}
523*4882a593Smuzhiyun 
524*4882a593Smuzhiyun 	return 0;
525*4882a593Smuzhiyun 
526*4882a593Smuzhiyun unreg_platform_driver:
527*4882a593Smuzhiyun 	platform_driver_unregister(&sch311x_wdt_driver);
528*4882a593Smuzhiyun 	return err;
529*4882a593Smuzhiyun }
530*4882a593Smuzhiyun 
sch311x_wdt_exit(void)531*4882a593Smuzhiyun static void __exit sch311x_wdt_exit(void)
532*4882a593Smuzhiyun {
533*4882a593Smuzhiyun 	platform_device_unregister(sch311x_wdt_pdev);
534*4882a593Smuzhiyun 	platform_driver_unregister(&sch311x_wdt_driver);
535*4882a593Smuzhiyun }
536*4882a593Smuzhiyun 
537*4882a593Smuzhiyun module_init(sch311x_wdt_init);
538*4882a593Smuzhiyun module_exit(sch311x_wdt_exit);
539*4882a593Smuzhiyun 
540*4882a593Smuzhiyun MODULE_AUTHOR("Wim Van Sebroeck <wim@iguana.be>");
541*4882a593Smuzhiyun MODULE_DESCRIPTION("SMSC SCH311x WatchDog Timer Driver");
542*4882a593Smuzhiyun MODULE_LICENSE("GPL");
543