1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Watchdog driver for the K3 RTI module
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * (c) Copyright 2019-2020 Texas Instruments Inc.
6*4882a593Smuzhiyun * All rights reserved.
7*4882a593Smuzhiyun */
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun #include <linux/clk.h>
10*4882a593Smuzhiyun #include <linux/device.h>
11*4882a593Smuzhiyun #include <linux/err.h>
12*4882a593Smuzhiyun #include <linux/io.h>
13*4882a593Smuzhiyun #include <linux/kernel.h>
14*4882a593Smuzhiyun #include <linux/mod_devicetable.h>
15*4882a593Smuzhiyun #include <linux/module.h>
16*4882a593Smuzhiyun #include <linux/moduleparam.h>
17*4882a593Smuzhiyun #include <linux/platform_device.h>
18*4882a593Smuzhiyun #include <linux/pm_runtime.h>
19*4882a593Smuzhiyun #include <linux/types.h>
20*4882a593Smuzhiyun #include <linux/watchdog.h>
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun #define DEFAULT_HEARTBEAT 60
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun /* Max heartbeat is calculated at 32kHz source clock */
25*4882a593Smuzhiyun #define MAX_HEARTBEAT 1000
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun /* Timer register set definition */
28*4882a593Smuzhiyun #define RTIDWDCTRL 0x90
29*4882a593Smuzhiyun #define RTIDWDPRLD 0x94
30*4882a593Smuzhiyun #define RTIWDSTATUS 0x98
31*4882a593Smuzhiyun #define RTIWDKEY 0x9c
32*4882a593Smuzhiyun #define RTIDWDCNTR 0xa0
33*4882a593Smuzhiyun #define RTIWWDRXCTRL 0xa4
34*4882a593Smuzhiyun #define RTIWWDSIZECTRL 0xa8
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun #define RTIWWDRX_NMI 0xa
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun #define RTIWWDSIZE_50P 0x50
39*4882a593Smuzhiyun #define RTIWWDSIZE_25P 0x500
40*4882a593Smuzhiyun #define RTIWWDSIZE_12P5 0x5000
41*4882a593Smuzhiyun #define RTIWWDSIZE_6P25 0x50000
42*4882a593Smuzhiyun #define RTIWWDSIZE_3P125 0x500000
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun #define WDENABLE_KEY 0xa98559da
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun #define WDKEY_SEQ0 0xe51a
47*4882a593Smuzhiyun #define WDKEY_SEQ1 0xa35c
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun #define WDT_PRELOAD_SHIFT 13
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun #define WDT_PRELOAD_MAX 0xfff
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun #define DWDST BIT(1)
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun static int heartbeat = DEFAULT_HEARTBEAT;
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun /*
58*4882a593Smuzhiyun * struct to hold data for each WDT device
59*4882a593Smuzhiyun * @base - base io address of WD device
60*4882a593Smuzhiyun * @freq - source clock frequency of WDT
61*4882a593Smuzhiyun * @wdd - hold watchdog device as is in WDT core
62*4882a593Smuzhiyun */
63*4882a593Smuzhiyun struct rti_wdt_device {
64*4882a593Smuzhiyun void __iomem *base;
65*4882a593Smuzhiyun unsigned long freq;
66*4882a593Smuzhiyun struct watchdog_device wdd;
67*4882a593Smuzhiyun };
68*4882a593Smuzhiyun
rti_wdt_start(struct watchdog_device * wdd)69*4882a593Smuzhiyun static int rti_wdt_start(struct watchdog_device *wdd)
70*4882a593Smuzhiyun {
71*4882a593Smuzhiyun u32 timer_margin;
72*4882a593Smuzhiyun struct rti_wdt_device *wdt = watchdog_get_drvdata(wdd);
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun /* set timeout period */
75*4882a593Smuzhiyun timer_margin = (u64)wdd->timeout * wdt->freq;
76*4882a593Smuzhiyun timer_margin >>= WDT_PRELOAD_SHIFT;
77*4882a593Smuzhiyun if (timer_margin > WDT_PRELOAD_MAX)
78*4882a593Smuzhiyun timer_margin = WDT_PRELOAD_MAX;
79*4882a593Smuzhiyun writel_relaxed(timer_margin, wdt->base + RTIDWDPRLD);
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun /*
82*4882a593Smuzhiyun * RTI only supports a windowed mode, where the watchdog can only
83*4882a593Smuzhiyun * be petted during the open window; not too early or not too late.
84*4882a593Smuzhiyun * The HW configuration options only allow for the open window size
85*4882a593Smuzhiyun * to be 50% or less than that; we obviouly want to configure the open
86*4882a593Smuzhiyun * window as large as possible so we select the 50% option.
87*4882a593Smuzhiyun */
88*4882a593Smuzhiyun wdd->min_hw_heartbeat_ms = 500 * wdd->timeout;
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun /* Generate NMI when wdt expires */
91*4882a593Smuzhiyun writel_relaxed(RTIWWDRX_NMI, wdt->base + RTIWWDRXCTRL);
92*4882a593Smuzhiyun
93*4882a593Smuzhiyun /* Open window size 50%; this is the largest window size available */
94*4882a593Smuzhiyun writel_relaxed(RTIWWDSIZE_50P, wdt->base + RTIWWDSIZECTRL);
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun readl_relaxed(wdt->base + RTIWWDSIZECTRL);
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun /* enable watchdog */
99*4882a593Smuzhiyun writel_relaxed(WDENABLE_KEY, wdt->base + RTIDWDCTRL);
100*4882a593Smuzhiyun return 0;
101*4882a593Smuzhiyun }
102*4882a593Smuzhiyun
rti_wdt_ping(struct watchdog_device * wdd)103*4882a593Smuzhiyun static int rti_wdt_ping(struct watchdog_device *wdd)
104*4882a593Smuzhiyun {
105*4882a593Smuzhiyun struct rti_wdt_device *wdt = watchdog_get_drvdata(wdd);
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun /* put watchdog in service state */
108*4882a593Smuzhiyun writel_relaxed(WDKEY_SEQ0, wdt->base + RTIWDKEY);
109*4882a593Smuzhiyun /* put watchdog in active state */
110*4882a593Smuzhiyun writel_relaxed(WDKEY_SEQ1, wdt->base + RTIWDKEY);
111*4882a593Smuzhiyun
112*4882a593Smuzhiyun return 0;
113*4882a593Smuzhiyun }
114*4882a593Smuzhiyun
rti_wdt_setup_hw_hb(struct watchdog_device * wdd,u32 wsize)115*4882a593Smuzhiyun static int rti_wdt_setup_hw_hb(struct watchdog_device *wdd, u32 wsize)
116*4882a593Smuzhiyun {
117*4882a593Smuzhiyun /*
118*4882a593Smuzhiyun * RTI only supports a windowed mode, where the watchdog can only
119*4882a593Smuzhiyun * be petted during the open window; not too early or not too late.
120*4882a593Smuzhiyun * The HW configuration options only allow for the open window size
121*4882a593Smuzhiyun * to be 50% or less than that.
122*4882a593Smuzhiyun */
123*4882a593Smuzhiyun switch (wsize) {
124*4882a593Smuzhiyun case RTIWWDSIZE_50P:
125*4882a593Smuzhiyun /* 50% open window => 50% min heartbeat */
126*4882a593Smuzhiyun wdd->min_hw_heartbeat_ms = 500 * heartbeat;
127*4882a593Smuzhiyun break;
128*4882a593Smuzhiyun
129*4882a593Smuzhiyun case RTIWWDSIZE_25P:
130*4882a593Smuzhiyun /* 25% open window => 75% min heartbeat */
131*4882a593Smuzhiyun wdd->min_hw_heartbeat_ms = 750 * heartbeat;
132*4882a593Smuzhiyun break;
133*4882a593Smuzhiyun
134*4882a593Smuzhiyun case RTIWWDSIZE_12P5:
135*4882a593Smuzhiyun /* 12.5% open window => 87.5% min heartbeat */
136*4882a593Smuzhiyun wdd->min_hw_heartbeat_ms = 875 * heartbeat;
137*4882a593Smuzhiyun break;
138*4882a593Smuzhiyun
139*4882a593Smuzhiyun case RTIWWDSIZE_6P25:
140*4882a593Smuzhiyun /* 6.5% open window => 93.5% min heartbeat */
141*4882a593Smuzhiyun wdd->min_hw_heartbeat_ms = 935 * heartbeat;
142*4882a593Smuzhiyun break;
143*4882a593Smuzhiyun
144*4882a593Smuzhiyun case RTIWWDSIZE_3P125:
145*4882a593Smuzhiyun /* 3.125% open window => 96.9% min heartbeat */
146*4882a593Smuzhiyun wdd->min_hw_heartbeat_ms = 969 * heartbeat;
147*4882a593Smuzhiyun break;
148*4882a593Smuzhiyun
149*4882a593Smuzhiyun default:
150*4882a593Smuzhiyun return -EINVAL;
151*4882a593Smuzhiyun }
152*4882a593Smuzhiyun
153*4882a593Smuzhiyun return 0;
154*4882a593Smuzhiyun }
155*4882a593Smuzhiyun
rti_wdt_get_timeleft_ms(struct watchdog_device * wdd)156*4882a593Smuzhiyun static unsigned int rti_wdt_get_timeleft_ms(struct watchdog_device *wdd)
157*4882a593Smuzhiyun {
158*4882a593Smuzhiyun u64 timer_counter;
159*4882a593Smuzhiyun u32 val;
160*4882a593Smuzhiyun struct rti_wdt_device *wdt = watchdog_get_drvdata(wdd);
161*4882a593Smuzhiyun
162*4882a593Smuzhiyun /* if timeout has occurred then return 0 */
163*4882a593Smuzhiyun val = readl_relaxed(wdt->base + RTIWDSTATUS);
164*4882a593Smuzhiyun if (val & DWDST)
165*4882a593Smuzhiyun return 0;
166*4882a593Smuzhiyun
167*4882a593Smuzhiyun timer_counter = readl_relaxed(wdt->base + RTIDWDCNTR);
168*4882a593Smuzhiyun
169*4882a593Smuzhiyun timer_counter *= 1000;
170*4882a593Smuzhiyun
171*4882a593Smuzhiyun do_div(timer_counter, wdt->freq);
172*4882a593Smuzhiyun
173*4882a593Smuzhiyun return timer_counter;
174*4882a593Smuzhiyun }
175*4882a593Smuzhiyun
rti_wdt_get_timeleft(struct watchdog_device * wdd)176*4882a593Smuzhiyun static unsigned int rti_wdt_get_timeleft(struct watchdog_device *wdd)
177*4882a593Smuzhiyun {
178*4882a593Smuzhiyun return rti_wdt_get_timeleft_ms(wdd) / 1000;
179*4882a593Smuzhiyun }
180*4882a593Smuzhiyun
181*4882a593Smuzhiyun static const struct watchdog_info rti_wdt_info = {
182*4882a593Smuzhiyun .options = WDIOF_KEEPALIVEPING,
183*4882a593Smuzhiyun .identity = "K3 RTI Watchdog",
184*4882a593Smuzhiyun };
185*4882a593Smuzhiyun
186*4882a593Smuzhiyun static const struct watchdog_ops rti_wdt_ops = {
187*4882a593Smuzhiyun .owner = THIS_MODULE,
188*4882a593Smuzhiyun .start = rti_wdt_start,
189*4882a593Smuzhiyun .ping = rti_wdt_ping,
190*4882a593Smuzhiyun .get_timeleft = rti_wdt_get_timeleft,
191*4882a593Smuzhiyun };
192*4882a593Smuzhiyun
rti_wdt_probe(struct platform_device * pdev)193*4882a593Smuzhiyun static int rti_wdt_probe(struct platform_device *pdev)
194*4882a593Smuzhiyun {
195*4882a593Smuzhiyun int ret = 0;
196*4882a593Smuzhiyun struct device *dev = &pdev->dev;
197*4882a593Smuzhiyun struct resource *wdt_mem;
198*4882a593Smuzhiyun struct watchdog_device *wdd;
199*4882a593Smuzhiyun struct rti_wdt_device *wdt;
200*4882a593Smuzhiyun struct clk *clk;
201*4882a593Smuzhiyun u32 last_ping = 0;
202*4882a593Smuzhiyun
203*4882a593Smuzhiyun wdt = devm_kzalloc(dev, sizeof(*wdt), GFP_KERNEL);
204*4882a593Smuzhiyun if (!wdt)
205*4882a593Smuzhiyun return -ENOMEM;
206*4882a593Smuzhiyun
207*4882a593Smuzhiyun clk = clk_get(dev, NULL);
208*4882a593Smuzhiyun if (IS_ERR(clk))
209*4882a593Smuzhiyun return dev_err_probe(dev, PTR_ERR(clk), "failed to get clock\n");
210*4882a593Smuzhiyun
211*4882a593Smuzhiyun wdt->freq = clk_get_rate(clk);
212*4882a593Smuzhiyun
213*4882a593Smuzhiyun clk_put(clk);
214*4882a593Smuzhiyun
215*4882a593Smuzhiyun if (!wdt->freq) {
216*4882a593Smuzhiyun dev_err(dev, "Failed to get fck rate.\n");
217*4882a593Smuzhiyun return -EINVAL;
218*4882a593Smuzhiyun }
219*4882a593Smuzhiyun
220*4882a593Smuzhiyun /*
221*4882a593Smuzhiyun * If watchdog is running at 32k clock, it is not accurate.
222*4882a593Smuzhiyun * Adjust frequency down in this case so that we don't pet
223*4882a593Smuzhiyun * the watchdog too often.
224*4882a593Smuzhiyun */
225*4882a593Smuzhiyun if (wdt->freq < 32768)
226*4882a593Smuzhiyun wdt->freq = wdt->freq * 9 / 10;
227*4882a593Smuzhiyun
228*4882a593Smuzhiyun pm_runtime_enable(dev);
229*4882a593Smuzhiyun ret = pm_runtime_get_sync(dev);
230*4882a593Smuzhiyun if (ret < 0) {
231*4882a593Smuzhiyun pm_runtime_put_noidle(dev);
232*4882a593Smuzhiyun pm_runtime_disable(&pdev->dev);
233*4882a593Smuzhiyun return dev_err_probe(dev, ret, "runtime pm failed\n");
234*4882a593Smuzhiyun }
235*4882a593Smuzhiyun
236*4882a593Smuzhiyun platform_set_drvdata(pdev, wdt);
237*4882a593Smuzhiyun
238*4882a593Smuzhiyun wdd = &wdt->wdd;
239*4882a593Smuzhiyun wdd->info = &rti_wdt_info;
240*4882a593Smuzhiyun wdd->ops = &rti_wdt_ops;
241*4882a593Smuzhiyun wdd->min_timeout = 1;
242*4882a593Smuzhiyun wdd->max_hw_heartbeat_ms = (WDT_PRELOAD_MAX << WDT_PRELOAD_SHIFT) /
243*4882a593Smuzhiyun wdt->freq * 1000;
244*4882a593Smuzhiyun wdd->parent = dev;
245*4882a593Smuzhiyun
246*4882a593Smuzhiyun watchdog_set_drvdata(wdd, wdt);
247*4882a593Smuzhiyun watchdog_set_nowayout(wdd, 1);
248*4882a593Smuzhiyun watchdog_set_restart_priority(wdd, 128);
249*4882a593Smuzhiyun
250*4882a593Smuzhiyun wdt_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
251*4882a593Smuzhiyun wdt->base = devm_ioremap_resource(dev, wdt_mem);
252*4882a593Smuzhiyun if (IS_ERR(wdt->base)) {
253*4882a593Smuzhiyun ret = PTR_ERR(wdt->base);
254*4882a593Smuzhiyun goto err_iomap;
255*4882a593Smuzhiyun }
256*4882a593Smuzhiyun
257*4882a593Smuzhiyun if (readl(wdt->base + RTIDWDCTRL) == WDENABLE_KEY) {
258*4882a593Smuzhiyun u32 time_left_ms;
259*4882a593Smuzhiyun u64 heartbeat_ms;
260*4882a593Smuzhiyun u32 wsize;
261*4882a593Smuzhiyun
262*4882a593Smuzhiyun set_bit(WDOG_HW_RUNNING, &wdd->status);
263*4882a593Smuzhiyun time_left_ms = rti_wdt_get_timeleft_ms(wdd);
264*4882a593Smuzhiyun heartbeat_ms = readl(wdt->base + RTIDWDPRLD);
265*4882a593Smuzhiyun heartbeat_ms <<= WDT_PRELOAD_SHIFT;
266*4882a593Smuzhiyun heartbeat_ms *= 1000;
267*4882a593Smuzhiyun do_div(heartbeat_ms, wdt->freq);
268*4882a593Smuzhiyun if (heartbeat_ms != heartbeat * 1000)
269*4882a593Smuzhiyun dev_warn(dev, "watchdog already running, ignoring heartbeat config!\n");
270*4882a593Smuzhiyun
271*4882a593Smuzhiyun heartbeat = heartbeat_ms;
272*4882a593Smuzhiyun heartbeat /= 1000;
273*4882a593Smuzhiyun
274*4882a593Smuzhiyun wsize = readl(wdt->base + RTIWWDSIZECTRL);
275*4882a593Smuzhiyun ret = rti_wdt_setup_hw_hb(wdd, wsize);
276*4882a593Smuzhiyun if (ret) {
277*4882a593Smuzhiyun dev_err(dev, "bad window size.\n");
278*4882a593Smuzhiyun goto err_iomap;
279*4882a593Smuzhiyun }
280*4882a593Smuzhiyun
281*4882a593Smuzhiyun last_ping = heartbeat_ms - time_left_ms;
282*4882a593Smuzhiyun if (time_left_ms > heartbeat_ms) {
283*4882a593Smuzhiyun dev_warn(dev, "time_left > heartbeat? Assuming last ping just before now.\n");
284*4882a593Smuzhiyun last_ping = 0;
285*4882a593Smuzhiyun }
286*4882a593Smuzhiyun }
287*4882a593Smuzhiyun
288*4882a593Smuzhiyun watchdog_init_timeout(wdd, heartbeat, dev);
289*4882a593Smuzhiyun
290*4882a593Smuzhiyun ret = watchdog_register_device(wdd);
291*4882a593Smuzhiyun if (ret) {
292*4882a593Smuzhiyun dev_err(dev, "cannot register watchdog device\n");
293*4882a593Smuzhiyun goto err_iomap;
294*4882a593Smuzhiyun }
295*4882a593Smuzhiyun
296*4882a593Smuzhiyun if (last_ping)
297*4882a593Smuzhiyun watchdog_set_last_hw_keepalive(wdd, last_ping);
298*4882a593Smuzhiyun
299*4882a593Smuzhiyun return 0;
300*4882a593Smuzhiyun
301*4882a593Smuzhiyun err_iomap:
302*4882a593Smuzhiyun pm_runtime_put_sync(&pdev->dev);
303*4882a593Smuzhiyun pm_runtime_disable(&pdev->dev);
304*4882a593Smuzhiyun
305*4882a593Smuzhiyun return ret;
306*4882a593Smuzhiyun }
307*4882a593Smuzhiyun
rti_wdt_remove(struct platform_device * pdev)308*4882a593Smuzhiyun static int rti_wdt_remove(struct platform_device *pdev)
309*4882a593Smuzhiyun {
310*4882a593Smuzhiyun struct rti_wdt_device *wdt = platform_get_drvdata(pdev);
311*4882a593Smuzhiyun
312*4882a593Smuzhiyun watchdog_unregister_device(&wdt->wdd);
313*4882a593Smuzhiyun pm_runtime_put(&pdev->dev);
314*4882a593Smuzhiyun pm_runtime_disable(&pdev->dev);
315*4882a593Smuzhiyun
316*4882a593Smuzhiyun return 0;
317*4882a593Smuzhiyun }
318*4882a593Smuzhiyun
319*4882a593Smuzhiyun static const struct of_device_id rti_wdt_of_match[] = {
320*4882a593Smuzhiyun { .compatible = "ti,j7-rti-wdt", },
321*4882a593Smuzhiyun {},
322*4882a593Smuzhiyun };
323*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, rti_wdt_of_match);
324*4882a593Smuzhiyun
325*4882a593Smuzhiyun static struct platform_driver rti_wdt_driver = {
326*4882a593Smuzhiyun .driver = {
327*4882a593Smuzhiyun .name = "rti-wdt",
328*4882a593Smuzhiyun .of_match_table = rti_wdt_of_match,
329*4882a593Smuzhiyun },
330*4882a593Smuzhiyun .probe = rti_wdt_probe,
331*4882a593Smuzhiyun .remove = rti_wdt_remove,
332*4882a593Smuzhiyun };
333*4882a593Smuzhiyun
334*4882a593Smuzhiyun module_platform_driver(rti_wdt_driver);
335*4882a593Smuzhiyun
336*4882a593Smuzhiyun MODULE_AUTHOR("Tero Kristo <t-kristo@ti.com>");
337*4882a593Smuzhiyun MODULE_DESCRIPTION("K3 RTI Watchdog Driver");
338*4882a593Smuzhiyun
339*4882a593Smuzhiyun module_param(heartbeat, int, 0);
340*4882a593Smuzhiyun MODULE_PARM_DESC(heartbeat,
341*4882a593Smuzhiyun "Watchdog heartbeat period in seconds from 1 to "
342*4882a593Smuzhiyun __MODULE_STRING(MAX_HEARTBEAT) ", default "
343*4882a593Smuzhiyun __MODULE_STRING(DEFAULT_HEARTBEAT));
344*4882a593Smuzhiyun
345*4882a593Smuzhiyun MODULE_LICENSE("GPL");
346*4882a593Smuzhiyun MODULE_ALIAS("platform:rti-wdt");
347