1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * IDT Interprise 79RC32434 watchdog driver
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2006, Ondrej Zajicek <santiago@crfreenet.org>
6*4882a593Smuzhiyun * Copyright (C) 2008, Florian Fainelli <florian@openwrt.org>
7*4882a593Smuzhiyun *
8*4882a593Smuzhiyun * based on
9*4882a593Smuzhiyun * SoftDog 0.05: A Software Watchdog Device
10*4882a593Smuzhiyun *
11*4882a593Smuzhiyun * (c) Copyright 1996 Alan Cox <alan@lxorguk.ukuu.org.uk>,
12*4882a593Smuzhiyun * All Rights Reserved.
13*4882a593Smuzhiyun */
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun #include <linux/module.h> /* For module specific items */
18*4882a593Smuzhiyun #include <linux/moduleparam.h> /* For new moduleparam's */
19*4882a593Smuzhiyun #include <linux/types.h> /* For standard types (like size_t) */
20*4882a593Smuzhiyun #include <linux/errno.h> /* For the -ENODEV/... values */
21*4882a593Smuzhiyun #include <linux/kernel.h> /* For printk/panic/... */
22*4882a593Smuzhiyun #include <linux/fs.h> /* For file operations */
23*4882a593Smuzhiyun #include <linux/miscdevice.h> /* For struct miscdevice */
24*4882a593Smuzhiyun #include <linux/watchdog.h> /* For the watchdog specific items */
25*4882a593Smuzhiyun #include <linux/init.h> /* For __init/__exit/... */
26*4882a593Smuzhiyun #include <linux/platform_device.h> /* For platform_driver framework */
27*4882a593Smuzhiyun #include <linux/spinlock.h> /* For spin_lock/spin_unlock/... */
28*4882a593Smuzhiyun #include <linux/uaccess.h> /* For copy_to_user/put_user/... */
29*4882a593Smuzhiyun #include <linux/io.h> /* For devm_ioremap */
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun #include <asm/mach-rc32434/integ.h> /* For the Watchdog registers */
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun #define VERSION "1.0"
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun static struct {
36*4882a593Smuzhiyun unsigned long inuse;
37*4882a593Smuzhiyun spinlock_t io_lock;
38*4882a593Smuzhiyun } rc32434_wdt_device;
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun static struct integ __iomem *wdt_reg;
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun static int expect_close;
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun /* Board internal clock speed in Hz,
45*4882a593Smuzhiyun * the watchdog timer ticks at. */
46*4882a593Smuzhiyun extern unsigned int idt_cpu_freq;
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun /* translate wtcompare value to seconds and vice versa */
49*4882a593Smuzhiyun #define WTCOMP2SEC(x) (x / idt_cpu_freq)
50*4882a593Smuzhiyun #define SEC2WTCOMP(x) (x * idt_cpu_freq)
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun /* Use a default timeout of 20s. This should be
53*4882a593Smuzhiyun * safe for CPU clock speeds up to 400MHz, as
54*4882a593Smuzhiyun * ((2 ^ 32) - 1) / (400MHz / 2) = 21s. */
55*4882a593Smuzhiyun #define WATCHDOG_TIMEOUT 20
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun static int timeout = WATCHDOG_TIMEOUT;
58*4882a593Smuzhiyun module_param(timeout, int, 0);
59*4882a593Smuzhiyun MODULE_PARM_DESC(timeout, "Watchdog timeout value, in seconds (default="
60*4882a593Smuzhiyun __MODULE_STRING(WATCHDOG_TIMEOUT) ")");
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun static bool nowayout = WATCHDOG_NOWAYOUT;
63*4882a593Smuzhiyun module_param(nowayout, bool, 0);
64*4882a593Smuzhiyun MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
65*4882a593Smuzhiyun __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun /* apply or and nand masks to data read from addr and write back */
68*4882a593Smuzhiyun #define SET_BITS(addr, or, nand) \
69*4882a593Smuzhiyun writel((readl(&addr) | or) & ~nand, &addr)
70*4882a593Smuzhiyun
rc32434_wdt_set(int new_timeout)71*4882a593Smuzhiyun static int rc32434_wdt_set(int new_timeout)
72*4882a593Smuzhiyun {
73*4882a593Smuzhiyun int max_to = WTCOMP2SEC((u32)-1);
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun if (new_timeout < 0 || new_timeout > max_to) {
76*4882a593Smuzhiyun pr_err("timeout value must be between 0 and %d\n", max_to);
77*4882a593Smuzhiyun return -EINVAL;
78*4882a593Smuzhiyun }
79*4882a593Smuzhiyun timeout = new_timeout;
80*4882a593Smuzhiyun spin_lock(&rc32434_wdt_device.io_lock);
81*4882a593Smuzhiyun writel(SEC2WTCOMP(timeout), &wdt_reg->wtcompare);
82*4882a593Smuzhiyun spin_unlock(&rc32434_wdt_device.io_lock);
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun return 0;
85*4882a593Smuzhiyun }
86*4882a593Smuzhiyun
rc32434_wdt_start(void)87*4882a593Smuzhiyun static void rc32434_wdt_start(void)
88*4882a593Smuzhiyun {
89*4882a593Smuzhiyun u32 or, nand;
90*4882a593Smuzhiyun
91*4882a593Smuzhiyun spin_lock(&rc32434_wdt_device.io_lock);
92*4882a593Smuzhiyun
93*4882a593Smuzhiyun /* zero the counter before enabling */
94*4882a593Smuzhiyun writel(0, &wdt_reg->wtcount);
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun /* don't generate a non-maskable interrupt,
97*4882a593Smuzhiyun * do a warm reset instead */
98*4882a593Smuzhiyun nand = 1 << RC32434_ERR_WNE;
99*4882a593Smuzhiyun or = 1 << RC32434_ERR_WRE;
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun /* reset the ERRCS timeout bit in case it's set */
102*4882a593Smuzhiyun nand |= 1 << RC32434_ERR_WTO;
103*4882a593Smuzhiyun
104*4882a593Smuzhiyun SET_BITS(wdt_reg->errcs, or, nand);
105*4882a593Smuzhiyun
106*4882a593Smuzhiyun /* set the timeout (either default or based on module param) */
107*4882a593Smuzhiyun rc32434_wdt_set(timeout);
108*4882a593Smuzhiyun
109*4882a593Smuzhiyun /* reset WTC timeout bit and enable WDT */
110*4882a593Smuzhiyun nand = 1 << RC32434_WTC_TO;
111*4882a593Smuzhiyun or = 1 << RC32434_WTC_EN;
112*4882a593Smuzhiyun
113*4882a593Smuzhiyun SET_BITS(wdt_reg->wtc, or, nand);
114*4882a593Smuzhiyun
115*4882a593Smuzhiyun spin_unlock(&rc32434_wdt_device.io_lock);
116*4882a593Smuzhiyun pr_info("Started watchdog timer\n");
117*4882a593Smuzhiyun }
118*4882a593Smuzhiyun
rc32434_wdt_stop(void)119*4882a593Smuzhiyun static void rc32434_wdt_stop(void)
120*4882a593Smuzhiyun {
121*4882a593Smuzhiyun spin_lock(&rc32434_wdt_device.io_lock);
122*4882a593Smuzhiyun
123*4882a593Smuzhiyun /* Disable WDT */
124*4882a593Smuzhiyun SET_BITS(wdt_reg->wtc, 0, 1 << RC32434_WTC_EN);
125*4882a593Smuzhiyun
126*4882a593Smuzhiyun spin_unlock(&rc32434_wdt_device.io_lock);
127*4882a593Smuzhiyun pr_info("Stopped watchdog timer\n");
128*4882a593Smuzhiyun }
129*4882a593Smuzhiyun
rc32434_wdt_ping(void)130*4882a593Smuzhiyun static void rc32434_wdt_ping(void)
131*4882a593Smuzhiyun {
132*4882a593Smuzhiyun spin_lock(&rc32434_wdt_device.io_lock);
133*4882a593Smuzhiyun writel(0, &wdt_reg->wtcount);
134*4882a593Smuzhiyun spin_unlock(&rc32434_wdt_device.io_lock);
135*4882a593Smuzhiyun }
136*4882a593Smuzhiyun
rc32434_wdt_open(struct inode * inode,struct file * file)137*4882a593Smuzhiyun static int rc32434_wdt_open(struct inode *inode, struct file *file)
138*4882a593Smuzhiyun {
139*4882a593Smuzhiyun if (test_and_set_bit(0, &rc32434_wdt_device.inuse))
140*4882a593Smuzhiyun return -EBUSY;
141*4882a593Smuzhiyun
142*4882a593Smuzhiyun if (nowayout)
143*4882a593Smuzhiyun __module_get(THIS_MODULE);
144*4882a593Smuzhiyun
145*4882a593Smuzhiyun rc32434_wdt_start();
146*4882a593Smuzhiyun rc32434_wdt_ping();
147*4882a593Smuzhiyun
148*4882a593Smuzhiyun return stream_open(inode, file);
149*4882a593Smuzhiyun }
150*4882a593Smuzhiyun
rc32434_wdt_release(struct inode * inode,struct file * file)151*4882a593Smuzhiyun static int rc32434_wdt_release(struct inode *inode, struct file *file)
152*4882a593Smuzhiyun {
153*4882a593Smuzhiyun if (expect_close == 42) {
154*4882a593Smuzhiyun rc32434_wdt_stop();
155*4882a593Smuzhiyun module_put(THIS_MODULE);
156*4882a593Smuzhiyun } else {
157*4882a593Smuzhiyun pr_crit("device closed unexpectedly. WDT will not stop!\n");
158*4882a593Smuzhiyun rc32434_wdt_ping();
159*4882a593Smuzhiyun }
160*4882a593Smuzhiyun clear_bit(0, &rc32434_wdt_device.inuse);
161*4882a593Smuzhiyun return 0;
162*4882a593Smuzhiyun }
163*4882a593Smuzhiyun
rc32434_wdt_write(struct file * file,const char * data,size_t len,loff_t * ppos)164*4882a593Smuzhiyun static ssize_t rc32434_wdt_write(struct file *file, const char *data,
165*4882a593Smuzhiyun size_t len, loff_t *ppos)
166*4882a593Smuzhiyun {
167*4882a593Smuzhiyun if (len) {
168*4882a593Smuzhiyun if (!nowayout) {
169*4882a593Smuzhiyun size_t i;
170*4882a593Smuzhiyun
171*4882a593Smuzhiyun /* In case it was set long ago */
172*4882a593Smuzhiyun expect_close = 0;
173*4882a593Smuzhiyun
174*4882a593Smuzhiyun for (i = 0; i != len; i++) {
175*4882a593Smuzhiyun char c;
176*4882a593Smuzhiyun if (get_user(c, data + i))
177*4882a593Smuzhiyun return -EFAULT;
178*4882a593Smuzhiyun if (c == 'V')
179*4882a593Smuzhiyun expect_close = 42;
180*4882a593Smuzhiyun }
181*4882a593Smuzhiyun }
182*4882a593Smuzhiyun rc32434_wdt_ping();
183*4882a593Smuzhiyun return len;
184*4882a593Smuzhiyun }
185*4882a593Smuzhiyun return 0;
186*4882a593Smuzhiyun }
187*4882a593Smuzhiyun
rc32434_wdt_ioctl(struct file * file,unsigned int cmd,unsigned long arg)188*4882a593Smuzhiyun static long rc32434_wdt_ioctl(struct file *file, unsigned int cmd,
189*4882a593Smuzhiyun unsigned long arg)
190*4882a593Smuzhiyun {
191*4882a593Smuzhiyun void __user *argp = (void __user *)arg;
192*4882a593Smuzhiyun int new_timeout;
193*4882a593Smuzhiyun unsigned int value;
194*4882a593Smuzhiyun static const struct watchdog_info ident = {
195*4882a593Smuzhiyun .options = WDIOF_SETTIMEOUT |
196*4882a593Smuzhiyun WDIOF_KEEPALIVEPING |
197*4882a593Smuzhiyun WDIOF_MAGICCLOSE,
198*4882a593Smuzhiyun .identity = "RC32434_WDT Watchdog",
199*4882a593Smuzhiyun };
200*4882a593Smuzhiyun switch (cmd) {
201*4882a593Smuzhiyun case WDIOC_GETSUPPORT:
202*4882a593Smuzhiyun if (copy_to_user(argp, &ident, sizeof(ident)))
203*4882a593Smuzhiyun return -EFAULT;
204*4882a593Smuzhiyun break;
205*4882a593Smuzhiyun case WDIOC_GETSTATUS:
206*4882a593Smuzhiyun case WDIOC_GETBOOTSTATUS:
207*4882a593Smuzhiyun value = 0;
208*4882a593Smuzhiyun if (copy_to_user(argp, &value, sizeof(int)))
209*4882a593Smuzhiyun return -EFAULT;
210*4882a593Smuzhiyun break;
211*4882a593Smuzhiyun case WDIOC_SETOPTIONS:
212*4882a593Smuzhiyun if (copy_from_user(&value, argp, sizeof(int)))
213*4882a593Smuzhiyun return -EFAULT;
214*4882a593Smuzhiyun switch (value) {
215*4882a593Smuzhiyun case WDIOS_ENABLECARD:
216*4882a593Smuzhiyun rc32434_wdt_start();
217*4882a593Smuzhiyun break;
218*4882a593Smuzhiyun case WDIOS_DISABLECARD:
219*4882a593Smuzhiyun rc32434_wdt_stop();
220*4882a593Smuzhiyun break;
221*4882a593Smuzhiyun default:
222*4882a593Smuzhiyun return -EINVAL;
223*4882a593Smuzhiyun }
224*4882a593Smuzhiyun break;
225*4882a593Smuzhiyun case WDIOC_KEEPALIVE:
226*4882a593Smuzhiyun rc32434_wdt_ping();
227*4882a593Smuzhiyun break;
228*4882a593Smuzhiyun case WDIOC_SETTIMEOUT:
229*4882a593Smuzhiyun if (copy_from_user(&new_timeout, argp, sizeof(int)))
230*4882a593Smuzhiyun return -EFAULT;
231*4882a593Smuzhiyun if (rc32434_wdt_set(new_timeout))
232*4882a593Smuzhiyun return -EINVAL;
233*4882a593Smuzhiyun fallthrough;
234*4882a593Smuzhiyun case WDIOC_GETTIMEOUT:
235*4882a593Smuzhiyun return copy_to_user(argp, &timeout, sizeof(int)) ? -EFAULT : 0;
236*4882a593Smuzhiyun default:
237*4882a593Smuzhiyun return -ENOTTY;
238*4882a593Smuzhiyun }
239*4882a593Smuzhiyun
240*4882a593Smuzhiyun return 0;
241*4882a593Smuzhiyun }
242*4882a593Smuzhiyun
243*4882a593Smuzhiyun static const struct file_operations rc32434_wdt_fops = {
244*4882a593Smuzhiyun .owner = THIS_MODULE,
245*4882a593Smuzhiyun .llseek = no_llseek,
246*4882a593Smuzhiyun .write = rc32434_wdt_write,
247*4882a593Smuzhiyun .unlocked_ioctl = rc32434_wdt_ioctl,
248*4882a593Smuzhiyun .compat_ioctl = compat_ptr_ioctl,
249*4882a593Smuzhiyun .open = rc32434_wdt_open,
250*4882a593Smuzhiyun .release = rc32434_wdt_release,
251*4882a593Smuzhiyun };
252*4882a593Smuzhiyun
253*4882a593Smuzhiyun static struct miscdevice rc32434_wdt_miscdev = {
254*4882a593Smuzhiyun .minor = WATCHDOG_MINOR,
255*4882a593Smuzhiyun .name = "watchdog",
256*4882a593Smuzhiyun .fops = &rc32434_wdt_fops,
257*4882a593Smuzhiyun };
258*4882a593Smuzhiyun
rc32434_wdt_probe(struct platform_device * pdev)259*4882a593Smuzhiyun static int rc32434_wdt_probe(struct platform_device *pdev)
260*4882a593Smuzhiyun {
261*4882a593Smuzhiyun int ret;
262*4882a593Smuzhiyun struct resource *r;
263*4882a593Smuzhiyun
264*4882a593Smuzhiyun r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rb532_wdt_res");
265*4882a593Smuzhiyun if (!r) {
266*4882a593Smuzhiyun pr_err("failed to retrieve resources\n");
267*4882a593Smuzhiyun return -ENODEV;
268*4882a593Smuzhiyun }
269*4882a593Smuzhiyun
270*4882a593Smuzhiyun wdt_reg = devm_ioremap(&pdev->dev, r->start, resource_size(r));
271*4882a593Smuzhiyun if (!wdt_reg) {
272*4882a593Smuzhiyun pr_err("failed to remap I/O resources\n");
273*4882a593Smuzhiyun return -ENXIO;
274*4882a593Smuzhiyun }
275*4882a593Smuzhiyun
276*4882a593Smuzhiyun spin_lock_init(&rc32434_wdt_device.io_lock);
277*4882a593Smuzhiyun
278*4882a593Smuzhiyun /* Make sure the watchdog is not running */
279*4882a593Smuzhiyun rc32434_wdt_stop();
280*4882a593Smuzhiyun
281*4882a593Smuzhiyun /* Check that the heartbeat value is within it's range;
282*4882a593Smuzhiyun * if not reset to the default */
283*4882a593Smuzhiyun if (rc32434_wdt_set(timeout)) {
284*4882a593Smuzhiyun rc32434_wdt_set(WATCHDOG_TIMEOUT);
285*4882a593Smuzhiyun pr_info("timeout value must be between 0 and %d\n",
286*4882a593Smuzhiyun WTCOMP2SEC((u32)-1));
287*4882a593Smuzhiyun }
288*4882a593Smuzhiyun
289*4882a593Smuzhiyun ret = misc_register(&rc32434_wdt_miscdev);
290*4882a593Smuzhiyun if (ret < 0) {
291*4882a593Smuzhiyun pr_err("failed to register watchdog device\n");
292*4882a593Smuzhiyun return ret;
293*4882a593Smuzhiyun }
294*4882a593Smuzhiyun
295*4882a593Smuzhiyun pr_info("Watchdog Timer version " VERSION ", timer margin: %d sec\n",
296*4882a593Smuzhiyun timeout);
297*4882a593Smuzhiyun
298*4882a593Smuzhiyun return 0;
299*4882a593Smuzhiyun }
300*4882a593Smuzhiyun
rc32434_wdt_remove(struct platform_device * pdev)301*4882a593Smuzhiyun static int rc32434_wdt_remove(struct platform_device *pdev)
302*4882a593Smuzhiyun {
303*4882a593Smuzhiyun misc_deregister(&rc32434_wdt_miscdev);
304*4882a593Smuzhiyun return 0;
305*4882a593Smuzhiyun }
306*4882a593Smuzhiyun
rc32434_wdt_shutdown(struct platform_device * pdev)307*4882a593Smuzhiyun static void rc32434_wdt_shutdown(struct platform_device *pdev)
308*4882a593Smuzhiyun {
309*4882a593Smuzhiyun rc32434_wdt_stop();
310*4882a593Smuzhiyun }
311*4882a593Smuzhiyun
312*4882a593Smuzhiyun static struct platform_driver rc32434_wdt_driver = {
313*4882a593Smuzhiyun .probe = rc32434_wdt_probe,
314*4882a593Smuzhiyun .remove = rc32434_wdt_remove,
315*4882a593Smuzhiyun .shutdown = rc32434_wdt_shutdown,
316*4882a593Smuzhiyun .driver = {
317*4882a593Smuzhiyun .name = "rc32434_wdt",
318*4882a593Smuzhiyun }
319*4882a593Smuzhiyun };
320*4882a593Smuzhiyun
321*4882a593Smuzhiyun module_platform_driver(rc32434_wdt_driver);
322*4882a593Smuzhiyun
323*4882a593Smuzhiyun MODULE_AUTHOR("Ondrej Zajicek <santiago@crfreenet.org>,"
324*4882a593Smuzhiyun "Florian Fainelli <florian@openwrt.org>");
325*4882a593Smuzhiyun MODULE_DESCRIPTION("Driver for the IDT RC32434 SoC watchdog");
326*4882a593Smuzhiyun MODULE_LICENSE("GPL");
327