1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun #include <linux/bitops.h>
3*4882a593Smuzhiyun #include <linux/interrupt.h>
4*4882a593Smuzhiyun #include <linux/kernel.h>
5*4882a593Smuzhiyun #include <linux/module.h>
6*4882a593Smuzhiyun #include <linux/of.h>
7*4882a593Smuzhiyun #include <linux/property.h>
8*4882a593Smuzhiyun #include <linux/platform_device.h>
9*4882a593Smuzhiyun #include <linux/regmap.h>
10*4882a593Smuzhiyun #include <linux/watchdog.h>
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun #define PON_INT_RT_STS 0x10
13*4882a593Smuzhiyun #define PMIC_WD_BARK_STS_BIT BIT(6)
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun #define PON_PMIC_WD_RESET_S1_TIMER 0x54
16*4882a593Smuzhiyun #define PON_PMIC_WD_RESET_S2_TIMER 0x55
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun #define PON_PMIC_WD_RESET_S2_CTL 0x56
19*4882a593Smuzhiyun #define RESET_TYPE_WARM 0x01
20*4882a593Smuzhiyun #define RESET_TYPE_SHUTDOWN 0x04
21*4882a593Smuzhiyun #define RESET_TYPE_HARD 0x07
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun #define PON_PMIC_WD_RESET_S2_CTL2 0x57
24*4882a593Smuzhiyun #define S2_RESET_EN_BIT BIT(7)
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun #define PON_PMIC_WD_RESET_PET 0x58
27*4882a593Smuzhiyun #define WATCHDOG_PET_BIT BIT(0)
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun #define PM8916_WDT_DEFAULT_TIMEOUT 32
30*4882a593Smuzhiyun #define PM8916_WDT_MIN_TIMEOUT 1
31*4882a593Smuzhiyun #define PM8916_WDT_MAX_TIMEOUT 127
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun struct pm8916_wdt {
34*4882a593Smuzhiyun struct regmap *regmap;
35*4882a593Smuzhiyun struct watchdog_device wdev;
36*4882a593Smuzhiyun u32 baseaddr;
37*4882a593Smuzhiyun };
38*4882a593Smuzhiyun
pm8916_wdt_start(struct watchdog_device * wdev)39*4882a593Smuzhiyun static int pm8916_wdt_start(struct watchdog_device *wdev)
40*4882a593Smuzhiyun {
41*4882a593Smuzhiyun struct pm8916_wdt *wdt = watchdog_get_drvdata(wdev);
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun return regmap_update_bits(wdt->regmap,
44*4882a593Smuzhiyun wdt->baseaddr + PON_PMIC_WD_RESET_S2_CTL2,
45*4882a593Smuzhiyun S2_RESET_EN_BIT, S2_RESET_EN_BIT);
46*4882a593Smuzhiyun }
47*4882a593Smuzhiyun
pm8916_wdt_stop(struct watchdog_device * wdev)48*4882a593Smuzhiyun static int pm8916_wdt_stop(struct watchdog_device *wdev)
49*4882a593Smuzhiyun {
50*4882a593Smuzhiyun struct pm8916_wdt *wdt = watchdog_get_drvdata(wdev);
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun return regmap_update_bits(wdt->regmap,
53*4882a593Smuzhiyun wdt->baseaddr + PON_PMIC_WD_RESET_S2_CTL2,
54*4882a593Smuzhiyun S2_RESET_EN_BIT, 0);
55*4882a593Smuzhiyun }
56*4882a593Smuzhiyun
pm8916_wdt_ping(struct watchdog_device * wdev)57*4882a593Smuzhiyun static int pm8916_wdt_ping(struct watchdog_device *wdev)
58*4882a593Smuzhiyun {
59*4882a593Smuzhiyun struct pm8916_wdt *wdt = watchdog_get_drvdata(wdev);
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun return regmap_update_bits(wdt->regmap,
62*4882a593Smuzhiyun wdt->baseaddr + PON_PMIC_WD_RESET_PET,
63*4882a593Smuzhiyun WATCHDOG_PET_BIT, WATCHDOG_PET_BIT);
64*4882a593Smuzhiyun }
65*4882a593Smuzhiyun
pm8916_wdt_configure_timers(struct watchdog_device * wdev)66*4882a593Smuzhiyun static int pm8916_wdt_configure_timers(struct watchdog_device *wdev)
67*4882a593Smuzhiyun {
68*4882a593Smuzhiyun struct pm8916_wdt *wdt = watchdog_get_drvdata(wdev);
69*4882a593Smuzhiyun int err;
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun err = regmap_write(wdt->regmap,
72*4882a593Smuzhiyun wdt->baseaddr + PON_PMIC_WD_RESET_S1_TIMER,
73*4882a593Smuzhiyun wdev->timeout - wdev->pretimeout);
74*4882a593Smuzhiyun if (err)
75*4882a593Smuzhiyun return err;
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun return regmap_write(wdt->regmap,
78*4882a593Smuzhiyun wdt->baseaddr + PON_PMIC_WD_RESET_S2_TIMER,
79*4882a593Smuzhiyun wdev->pretimeout);
80*4882a593Smuzhiyun }
81*4882a593Smuzhiyun
pm8916_wdt_set_timeout(struct watchdog_device * wdev,unsigned int timeout)82*4882a593Smuzhiyun static int pm8916_wdt_set_timeout(struct watchdog_device *wdev,
83*4882a593Smuzhiyun unsigned int timeout)
84*4882a593Smuzhiyun {
85*4882a593Smuzhiyun wdev->timeout = timeout;
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun return pm8916_wdt_configure_timers(wdev);
88*4882a593Smuzhiyun }
89*4882a593Smuzhiyun
pm8916_wdt_set_pretimeout(struct watchdog_device * wdev,unsigned int pretimeout)90*4882a593Smuzhiyun static int pm8916_wdt_set_pretimeout(struct watchdog_device *wdev,
91*4882a593Smuzhiyun unsigned int pretimeout)
92*4882a593Smuzhiyun {
93*4882a593Smuzhiyun wdev->pretimeout = pretimeout;
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun return pm8916_wdt_configure_timers(wdev);
96*4882a593Smuzhiyun }
97*4882a593Smuzhiyun
pm8916_wdt_isr(int irq,void * arg)98*4882a593Smuzhiyun static irqreturn_t pm8916_wdt_isr(int irq, void *arg)
99*4882a593Smuzhiyun {
100*4882a593Smuzhiyun struct pm8916_wdt *wdt = arg;
101*4882a593Smuzhiyun int err, sts;
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun err = regmap_read(wdt->regmap, wdt->baseaddr + PON_INT_RT_STS, &sts);
104*4882a593Smuzhiyun if (err)
105*4882a593Smuzhiyun return IRQ_HANDLED;
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun if (sts & PMIC_WD_BARK_STS_BIT)
108*4882a593Smuzhiyun watchdog_notify_pretimeout(&wdt->wdev);
109*4882a593Smuzhiyun
110*4882a593Smuzhiyun return IRQ_HANDLED;
111*4882a593Smuzhiyun }
112*4882a593Smuzhiyun
113*4882a593Smuzhiyun static const struct watchdog_info pm8916_wdt_ident = {
114*4882a593Smuzhiyun .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE,
115*4882a593Smuzhiyun .identity = "QCOM PM8916 PON WDT",
116*4882a593Smuzhiyun };
117*4882a593Smuzhiyun
118*4882a593Smuzhiyun static const struct watchdog_info pm8916_wdt_pt_ident = {
119*4882a593Smuzhiyun .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE |
120*4882a593Smuzhiyun WDIOF_PRETIMEOUT,
121*4882a593Smuzhiyun .identity = "QCOM PM8916 PON WDT",
122*4882a593Smuzhiyun };
123*4882a593Smuzhiyun
124*4882a593Smuzhiyun static const struct watchdog_ops pm8916_wdt_ops = {
125*4882a593Smuzhiyun .owner = THIS_MODULE,
126*4882a593Smuzhiyun .start = pm8916_wdt_start,
127*4882a593Smuzhiyun .stop = pm8916_wdt_stop,
128*4882a593Smuzhiyun .ping = pm8916_wdt_ping,
129*4882a593Smuzhiyun .set_timeout = pm8916_wdt_set_timeout,
130*4882a593Smuzhiyun .set_pretimeout = pm8916_wdt_set_pretimeout,
131*4882a593Smuzhiyun };
132*4882a593Smuzhiyun
pm8916_wdt_probe(struct platform_device * pdev)133*4882a593Smuzhiyun static int pm8916_wdt_probe(struct platform_device *pdev)
134*4882a593Smuzhiyun {
135*4882a593Smuzhiyun struct device *dev = &pdev->dev;
136*4882a593Smuzhiyun struct pm8916_wdt *wdt;
137*4882a593Smuzhiyun struct device *parent;
138*4882a593Smuzhiyun int err, irq;
139*4882a593Smuzhiyun
140*4882a593Smuzhiyun wdt = devm_kzalloc(dev, sizeof(*wdt), GFP_KERNEL);
141*4882a593Smuzhiyun if (!wdt)
142*4882a593Smuzhiyun return -ENOMEM;
143*4882a593Smuzhiyun
144*4882a593Smuzhiyun parent = dev->parent;
145*4882a593Smuzhiyun
146*4882a593Smuzhiyun /*
147*4882a593Smuzhiyun * The pm8916-pon-wdt is a child of the pon device, which is a child
148*4882a593Smuzhiyun * of the pm8916 mfd device. We want access to the pm8916 registers.
149*4882a593Smuzhiyun * Retrieve regmap from pm8916 (parent->parent) and base address
150*4882a593Smuzhiyun * from pm8916-pon (pon).
151*4882a593Smuzhiyun */
152*4882a593Smuzhiyun wdt->regmap = dev_get_regmap(parent->parent, NULL);
153*4882a593Smuzhiyun if (!wdt->regmap) {
154*4882a593Smuzhiyun dev_err(dev, "failed to locate regmap\n");
155*4882a593Smuzhiyun return -ENODEV;
156*4882a593Smuzhiyun }
157*4882a593Smuzhiyun
158*4882a593Smuzhiyun err = device_property_read_u32(parent, "reg", &wdt->baseaddr);
159*4882a593Smuzhiyun if (err) {
160*4882a593Smuzhiyun dev_err(dev, "failed to get pm8916-pon address\n");
161*4882a593Smuzhiyun return err;
162*4882a593Smuzhiyun }
163*4882a593Smuzhiyun
164*4882a593Smuzhiyun irq = platform_get_irq(pdev, 0);
165*4882a593Smuzhiyun if (irq > 0) {
166*4882a593Smuzhiyun err = devm_request_irq(dev, irq, pm8916_wdt_isr, 0,
167*4882a593Smuzhiyun "pm8916_wdt", wdt);
168*4882a593Smuzhiyun if (err)
169*4882a593Smuzhiyun return err;
170*4882a593Smuzhiyun
171*4882a593Smuzhiyun wdt->wdev.info = &pm8916_wdt_pt_ident;
172*4882a593Smuzhiyun } else {
173*4882a593Smuzhiyun if (irq == -EPROBE_DEFER)
174*4882a593Smuzhiyun return -EPROBE_DEFER;
175*4882a593Smuzhiyun
176*4882a593Smuzhiyun wdt->wdev.info = &pm8916_wdt_ident;
177*4882a593Smuzhiyun }
178*4882a593Smuzhiyun
179*4882a593Smuzhiyun /* Configure watchdog to hard-reset mode */
180*4882a593Smuzhiyun err = regmap_write(wdt->regmap,
181*4882a593Smuzhiyun wdt->baseaddr + PON_PMIC_WD_RESET_S2_CTL,
182*4882a593Smuzhiyun RESET_TYPE_HARD);
183*4882a593Smuzhiyun if (err) {
184*4882a593Smuzhiyun dev_err(dev, "failed configure watchdog\n");
185*4882a593Smuzhiyun return err;
186*4882a593Smuzhiyun }
187*4882a593Smuzhiyun
188*4882a593Smuzhiyun wdt->wdev.ops = &pm8916_wdt_ops,
189*4882a593Smuzhiyun wdt->wdev.parent = dev;
190*4882a593Smuzhiyun wdt->wdev.min_timeout = PM8916_WDT_MIN_TIMEOUT;
191*4882a593Smuzhiyun wdt->wdev.max_timeout = PM8916_WDT_MAX_TIMEOUT;
192*4882a593Smuzhiyun wdt->wdev.timeout = PM8916_WDT_DEFAULT_TIMEOUT;
193*4882a593Smuzhiyun wdt->wdev.pretimeout = 0;
194*4882a593Smuzhiyun watchdog_set_drvdata(&wdt->wdev, wdt);
195*4882a593Smuzhiyun platform_set_drvdata(pdev, wdt);
196*4882a593Smuzhiyun
197*4882a593Smuzhiyun watchdog_init_timeout(&wdt->wdev, 0, dev);
198*4882a593Smuzhiyun pm8916_wdt_configure_timers(&wdt->wdev);
199*4882a593Smuzhiyun
200*4882a593Smuzhiyun return devm_watchdog_register_device(dev, &wdt->wdev);
201*4882a593Smuzhiyun }
202*4882a593Smuzhiyun
pm8916_wdt_suspend(struct device * dev)203*4882a593Smuzhiyun static int __maybe_unused pm8916_wdt_suspend(struct device *dev)
204*4882a593Smuzhiyun {
205*4882a593Smuzhiyun struct pm8916_wdt *wdt = dev_get_drvdata(dev);
206*4882a593Smuzhiyun
207*4882a593Smuzhiyun if (watchdog_active(&wdt->wdev))
208*4882a593Smuzhiyun return pm8916_wdt_stop(&wdt->wdev);
209*4882a593Smuzhiyun
210*4882a593Smuzhiyun return 0;
211*4882a593Smuzhiyun }
212*4882a593Smuzhiyun
pm8916_wdt_resume(struct device * dev)213*4882a593Smuzhiyun static int __maybe_unused pm8916_wdt_resume(struct device *dev)
214*4882a593Smuzhiyun {
215*4882a593Smuzhiyun struct pm8916_wdt *wdt = dev_get_drvdata(dev);
216*4882a593Smuzhiyun
217*4882a593Smuzhiyun if (watchdog_active(&wdt->wdev))
218*4882a593Smuzhiyun return pm8916_wdt_start(&wdt->wdev);
219*4882a593Smuzhiyun
220*4882a593Smuzhiyun return 0;
221*4882a593Smuzhiyun }
222*4882a593Smuzhiyun
223*4882a593Smuzhiyun static SIMPLE_DEV_PM_OPS(pm8916_wdt_pm_ops, pm8916_wdt_suspend,
224*4882a593Smuzhiyun pm8916_wdt_resume);
225*4882a593Smuzhiyun
226*4882a593Smuzhiyun static const struct of_device_id pm8916_wdt_id_table[] = {
227*4882a593Smuzhiyun { .compatible = "qcom,pm8916-wdt" },
228*4882a593Smuzhiyun { }
229*4882a593Smuzhiyun };
230*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, pm8916_wdt_id_table);
231*4882a593Smuzhiyun
232*4882a593Smuzhiyun static struct platform_driver pm8916_wdt_driver = {
233*4882a593Smuzhiyun .probe = pm8916_wdt_probe,
234*4882a593Smuzhiyun .driver = {
235*4882a593Smuzhiyun .name = "pm8916-wdt",
236*4882a593Smuzhiyun .of_match_table = of_match_ptr(pm8916_wdt_id_table),
237*4882a593Smuzhiyun .pm = &pm8916_wdt_pm_ops,
238*4882a593Smuzhiyun },
239*4882a593Smuzhiyun };
240*4882a593Smuzhiyun module_platform_driver(pm8916_wdt_driver);
241*4882a593Smuzhiyun
242*4882a593Smuzhiyun MODULE_AUTHOR("Loic Poulain <loic.poulain@linaro.org>");
243*4882a593Smuzhiyun MODULE_DESCRIPTION("Qualcomm pm8916 watchdog driver");
244*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
245