1*4882a593Smuzhiyun/* 2*4882a593Smuzhiyun * This file is subject to the terms and conditions of the GNU General Public 3*4882a593Smuzhiyun * License. See the file "COPYING" in the main directory of this archive 4*4882a593Smuzhiyun * for more details. 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * Copyright (C) 2007-2017 Cavium, Inc. 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun#include <asm/asm.h> 9*4882a593Smuzhiyun#include <asm/regdef.h> 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun#define CVMSEG_BASE -32768 12*4882a593Smuzhiyun#define CVMSEG_SIZE 6912 13*4882a593Smuzhiyun#define SAVE_REG(r) sd $r, CVMSEG_BASE + CVMSEG_SIZE - ((32 - r) * 8)($0) 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun NESTED(octeon_wdt_nmi_stage2, 0, sp) 16*4882a593Smuzhiyun .set push 17*4882a593Smuzhiyun .set noreorder 18*4882a593Smuzhiyun .set noat 19*4882a593Smuzhiyun /* Clear Dcache so cvmseg works right. */ 20*4882a593Smuzhiyun cache 1,0($0) 21*4882a593Smuzhiyun /* Use K0 to do a read/modify/write of CVMMEMCTL */ 22*4882a593Smuzhiyun dmfc0 k0, $11, 7 23*4882a593Smuzhiyun /* Clear out the size of CVMSEG */ 24*4882a593Smuzhiyun dins k0, $0, 0, 6 25*4882a593Smuzhiyun /* Set CVMSEG to its largest value */ 26*4882a593Smuzhiyun ori k0, k0, 0x1c0 | 54 27*4882a593Smuzhiyun /* Store the CVMMEMCTL value */ 28*4882a593Smuzhiyun dmtc0 k0, $11, 7 29*4882a593Smuzhiyun /* 30*4882a593Smuzhiyun * Restore K0 from the debug scratch register, it was saved in 31*4882a593Smuzhiyun * the boot-vector code. 32*4882a593Smuzhiyun */ 33*4882a593Smuzhiyun dmfc0 k0, $31 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun /* 36*4882a593Smuzhiyun * Save all registers to the top CVMSEG. This shouldn't 37*4882a593Smuzhiyun * corrupt any state used by the kernel. Also all registers 38*4882a593Smuzhiyun * should have the value right before the NMI. 39*4882a593Smuzhiyun */ 40*4882a593Smuzhiyun SAVE_REG(0) 41*4882a593Smuzhiyun SAVE_REG(1) 42*4882a593Smuzhiyun SAVE_REG(2) 43*4882a593Smuzhiyun SAVE_REG(3) 44*4882a593Smuzhiyun SAVE_REG(4) 45*4882a593Smuzhiyun SAVE_REG(5) 46*4882a593Smuzhiyun SAVE_REG(6) 47*4882a593Smuzhiyun SAVE_REG(7) 48*4882a593Smuzhiyun SAVE_REG(8) 49*4882a593Smuzhiyun SAVE_REG(9) 50*4882a593Smuzhiyun SAVE_REG(10) 51*4882a593Smuzhiyun SAVE_REG(11) 52*4882a593Smuzhiyun SAVE_REG(12) 53*4882a593Smuzhiyun SAVE_REG(13) 54*4882a593Smuzhiyun SAVE_REG(14) 55*4882a593Smuzhiyun SAVE_REG(15) 56*4882a593Smuzhiyun SAVE_REG(16) 57*4882a593Smuzhiyun SAVE_REG(17) 58*4882a593Smuzhiyun SAVE_REG(18) 59*4882a593Smuzhiyun SAVE_REG(19) 60*4882a593Smuzhiyun SAVE_REG(20) 61*4882a593Smuzhiyun SAVE_REG(21) 62*4882a593Smuzhiyun SAVE_REG(22) 63*4882a593Smuzhiyun SAVE_REG(23) 64*4882a593Smuzhiyun SAVE_REG(24) 65*4882a593Smuzhiyun SAVE_REG(25) 66*4882a593Smuzhiyun SAVE_REG(26) 67*4882a593Smuzhiyun SAVE_REG(27) 68*4882a593Smuzhiyun SAVE_REG(28) 69*4882a593Smuzhiyun SAVE_REG(29) 70*4882a593Smuzhiyun SAVE_REG(30) 71*4882a593Smuzhiyun SAVE_REG(31) 72*4882a593Smuzhiyun /* Write zero to all CVMSEG locations per Core-15169 */ 73*4882a593Smuzhiyun dli a0, CVMSEG_SIZE - (33 * 8) 74*4882a593Smuzhiyun1: sd zero, CVMSEG_BASE(a0) 75*4882a593Smuzhiyun daddiu a0, a0, -8 76*4882a593Smuzhiyun bgez a0, 1b 77*4882a593Smuzhiyun nop 78*4882a593Smuzhiyun /* Set the stack to begin right below the registers */ 79*4882a593Smuzhiyun dli sp, CVMSEG_BASE + CVMSEG_SIZE - (32 * 8) 80*4882a593Smuzhiyun /* Load the address of the third stage handler */ 81*4882a593Smuzhiyun dla $25, octeon_wdt_nmi_stage3 82*4882a593Smuzhiyun /* Call the third stage handler */ 83*4882a593Smuzhiyun jal $25 84*4882a593Smuzhiyun /* a0 is the address of the saved registers */ 85*4882a593Smuzhiyun move a0, sp 86*4882a593Smuzhiyun /* Loop forvever if we get here. */ 87*4882a593Smuzhiyun2: b 2b 88*4882a593Smuzhiyun nop 89*4882a593Smuzhiyun .set pop 90*4882a593Smuzhiyun END(octeon_wdt_nmi_stage2) 91