1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0+ */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * nv_tco: TCO timer driver for nVidia chipsets. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * (c) Copyright 2005 Google Inc., All Rights Reserved. 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * Supported Chipsets: 8*4882a593Smuzhiyun * - MCP51/MCP55 9*4882a593Smuzhiyun * 10*4882a593Smuzhiyun * (c) Copyright 2000 kernel concepts <nils@kernelconcepts.de>, All Rights 11*4882a593Smuzhiyun * Reserved. 12*4882a593Smuzhiyun * https://www.kernelconcepts.de 13*4882a593Smuzhiyun * 14*4882a593Smuzhiyun * Neither kernel concepts nor Nils Faerber admit liability nor provide 15*4882a593Smuzhiyun * warranty for any of this software. This material is provided 16*4882a593Smuzhiyun * "AS-IS" and at no charge. 17*4882a593Smuzhiyun * 18*4882a593Smuzhiyun * (c) Copyright 2000 kernel concepts <nils@kernelconcepts.de> 19*4882a593Smuzhiyun * developed for 20*4882a593Smuzhiyun * Jentro AG, Haar/Munich (Germany) 21*4882a593Smuzhiyun * 22*4882a593Smuzhiyun * TCO timer driver for NV chipsets 23*4882a593Smuzhiyun * based on softdog.c by Alan Cox <alan@redhat.com> 24*4882a593Smuzhiyun */ 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun /* 27*4882a593Smuzhiyun * Some address definitions for the TCO 28*4882a593Smuzhiyun */ 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun #define TCO_RLD(base) ((base) + 0x00) /* TCO Timer Reload and Current Value */ 31*4882a593Smuzhiyun #define TCO_TMR(base) ((base) + 0x01) /* TCO Timer Initial Value */ 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun #define TCO_STS(base) ((base) + 0x04) /* TCO Status Register */ 34*4882a593Smuzhiyun /* 35*4882a593Smuzhiyun * TCO Boot Status bit: set on TCO reset, reset by software or standby 36*4882a593Smuzhiyun * power-good (survives reboots), unfortunately this bit is never 37*4882a593Smuzhiyun * set. 38*4882a593Smuzhiyun */ 39*4882a593Smuzhiyun # define TCO_STS_BOOT_STS (1 << 9) 40*4882a593Smuzhiyun /* 41*4882a593Smuzhiyun * first and 2nd timeout status bits, these also survive a warm boot, 42*4882a593Smuzhiyun * and they work, so we use them. 43*4882a593Smuzhiyun */ 44*4882a593Smuzhiyun # define TCO_STS_TCO_INT_STS (1 << 1) 45*4882a593Smuzhiyun # define TCO_STS_TCO2TO_STS (1 << 10) 46*4882a593Smuzhiyun # define TCO_STS_RESET (TCO_STS_BOOT_STS | TCO_STS_TCO2TO_STS | \ 47*4882a593Smuzhiyun TCO_STS_TCO_INT_STS) 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun #define TCO_CNT(base) ((base) + 0x08) /* TCO Control Register */ 50*4882a593Smuzhiyun # define TCO_CNT_TCOHALT (1 << 12) 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun #define MCP51_SMBUS_SETUP_B 0xe8 53*4882a593Smuzhiyun # define MCP51_SMBUS_SETUP_B_TCO_REBOOT (1 << 25) 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun /* 56*4882a593Smuzhiyun * The SMI_EN register is at the base io address + 0x04, 57*4882a593Smuzhiyun * while TCOBASE is + 0x40. 58*4882a593Smuzhiyun */ 59*4882a593Smuzhiyun #define MCP51_SMI_EN(base) ((base) - 0x40 + 0x04) 60*4882a593Smuzhiyun # define MCP51_SMI_EN_TCO ((1 << 4) | (1 << 5)) 61