1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * nv_tco 0.01: TCO timer driver for NV chipsets
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * (c) Copyright 2005 Google Inc., All Rights Reserved.
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Based off i8xx_tco.c:
8*4882a593Smuzhiyun * (c) Copyright 2000 kernel concepts <nils@kernelconcepts.de>, All Rights
9*4882a593Smuzhiyun * Reserved.
10*4882a593Smuzhiyun * https://www.kernelconcepts.de
11*4882a593Smuzhiyun *
12*4882a593Smuzhiyun * TCO timer driver for NV chipsets
13*4882a593Smuzhiyun * based on softdog.c by Alan Cox <alan@redhat.com>
14*4882a593Smuzhiyun */
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun /*
17*4882a593Smuzhiyun * Includes, defines, variables, module parameters, ...
18*4882a593Smuzhiyun */
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun #include <linux/module.h>
23*4882a593Smuzhiyun #include <linux/moduleparam.h>
24*4882a593Smuzhiyun #include <linux/types.h>
25*4882a593Smuzhiyun #include <linux/miscdevice.h>
26*4882a593Smuzhiyun #include <linux/watchdog.h>
27*4882a593Smuzhiyun #include <linux/init.h>
28*4882a593Smuzhiyun #include <linux/fs.h>
29*4882a593Smuzhiyun #include <linux/pci.h>
30*4882a593Smuzhiyun #include <linux/ioport.h>
31*4882a593Smuzhiyun #include <linux/jiffies.h>
32*4882a593Smuzhiyun #include <linux/platform_device.h>
33*4882a593Smuzhiyun #include <linux/uaccess.h>
34*4882a593Smuzhiyun #include <linux/io.h>
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun #include "nv_tco.h"
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun /* Module and version information */
39*4882a593Smuzhiyun #define TCO_VERSION "0.01"
40*4882a593Smuzhiyun #define TCO_MODULE_NAME "NV_TCO"
41*4882a593Smuzhiyun #define TCO_DRIVER_NAME TCO_MODULE_NAME ", v" TCO_VERSION
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun /* internal variables */
44*4882a593Smuzhiyun static unsigned int tcobase;
45*4882a593Smuzhiyun static DEFINE_SPINLOCK(tco_lock); /* Guards the hardware */
46*4882a593Smuzhiyun static unsigned long timer_alive;
47*4882a593Smuzhiyun static char tco_expect_close;
48*4882a593Smuzhiyun static struct pci_dev *tco_pci;
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun /* the watchdog platform device */
51*4882a593Smuzhiyun static struct platform_device *nv_tco_platform_device;
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun /* module parameters */
54*4882a593Smuzhiyun #define WATCHDOG_HEARTBEAT 30 /* 30 sec default heartbeat (2<heartbeat<39) */
55*4882a593Smuzhiyun static int heartbeat = WATCHDOG_HEARTBEAT; /* in seconds */
56*4882a593Smuzhiyun module_param(heartbeat, int, 0);
57*4882a593Smuzhiyun MODULE_PARM_DESC(heartbeat, "Watchdog heartbeat in seconds. (2<heartbeat<39, "
58*4882a593Smuzhiyun "default=" __MODULE_STRING(WATCHDOG_HEARTBEAT) ")");
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun static bool nowayout = WATCHDOG_NOWAYOUT;
61*4882a593Smuzhiyun module_param(nowayout, bool, 0);
62*4882a593Smuzhiyun MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started"
63*4882a593Smuzhiyun " (default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun /*
66*4882a593Smuzhiyun * Some TCO specific functions
67*4882a593Smuzhiyun */
seconds_to_ticks(int seconds)68*4882a593Smuzhiyun static inline unsigned char seconds_to_ticks(int seconds)
69*4882a593Smuzhiyun {
70*4882a593Smuzhiyun /* the internal timer is stored as ticks which decrement
71*4882a593Smuzhiyun * every 0.6 seconds */
72*4882a593Smuzhiyun return (seconds * 10) / 6;
73*4882a593Smuzhiyun }
74*4882a593Smuzhiyun
tco_timer_start(void)75*4882a593Smuzhiyun static void tco_timer_start(void)
76*4882a593Smuzhiyun {
77*4882a593Smuzhiyun u32 val;
78*4882a593Smuzhiyun unsigned long flags;
79*4882a593Smuzhiyun
80*4882a593Smuzhiyun spin_lock_irqsave(&tco_lock, flags);
81*4882a593Smuzhiyun val = inl(TCO_CNT(tcobase));
82*4882a593Smuzhiyun val &= ~TCO_CNT_TCOHALT;
83*4882a593Smuzhiyun outl(val, TCO_CNT(tcobase));
84*4882a593Smuzhiyun spin_unlock_irqrestore(&tco_lock, flags);
85*4882a593Smuzhiyun }
86*4882a593Smuzhiyun
tco_timer_stop(void)87*4882a593Smuzhiyun static void tco_timer_stop(void)
88*4882a593Smuzhiyun {
89*4882a593Smuzhiyun u32 val;
90*4882a593Smuzhiyun unsigned long flags;
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun spin_lock_irqsave(&tco_lock, flags);
93*4882a593Smuzhiyun val = inl(TCO_CNT(tcobase));
94*4882a593Smuzhiyun val |= TCO_CNT_TCOHALT;
95*4882a593Smuzhiyun outl(val, TCO_CNT(tcobase));
96*4882a593Smuzhiyun spin_unlock_irqrestore(&tco_lock, flags);
97*4882a593Smuzhiyun }
98*4882a593Smuzhiyun
tco_timer_keepalive(void)99*4882a593Smuzhiyun static void tco_timer_keepalive(void)
100*4882a593Smuzhiyun {
101*4882a593Smuzhiyun unsigned long flags;
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun spin_lock_irqsave(&tco_lock, flags);
104*4882a593Smuzhiyun outb(0x01, TCO_RLD(tcobase));
105*4882a593Smuzhiyun spin_unlock_irqrestore(&tco_lock, flags);
106*4882a593Smuzhiyun }
107*4882a593Smuzhiyun
tco_timer_set_heartbeat(int t)108*4882a593Smuzhiyun static int tco_timer_set_heartbeat(int t)
109*4882a593Smuzhiyun {
110*4882a593Smuzhiyun int ret = 0;
111*4882a593Smuzhiyun unsigned char tmrval;
112*4882a593Smuzhiyun unsigned long flags;
113*4882a593Smuzhiyun u8 val;
114*4882a593Smuzhiyun
115*4882a593Smuzhiyun /*
116*4882a593Smuzhiyun * note seconds_to_ticks(t) > t, so if t > 0x3f, so is
117*4882a593Smuzhiyun * tmrval=seconds_to_ticks(t). Check that the count in seconds isn't
118*4882a593Smuzhiyun * out of range on it's own (to avoid overflow in tmrval).
119*4882a593Smuzhiyun */
120*4882a593Smuzhiyun if (t < 0 || t > 0x3f)
121*4882a593Smuzhiyun return -EINVAL;
122*4882a593Smuzhiyun tmrval = seconds_to_ticks(t);
123*4882a593Smuzhiyun
124*4882a593Smuzhiyun /* "Values of 0h-3h are ignored and should not be attempted" */
125*4882a593Smuzhiyun if (tmrval > 0x3f || tmrval < 0x04)
126*4882a593Smuzhiyun return -EINVAL;
127*4882a593Smuzhiyun
128*4882a593Smuzhiyun /* Write new heartbeat to watchdog */
129*4882a593Smuzhiyun spin_lock_irqsave(&tco_lock, flags);
130*4882a593Smuzhiyun val = inb(TCO_TMR(tcobase));
131*4882a593Smuzhiyun val &= 0xc0;
132*4882a593Smuzhiyun val |= tmrval;
133*4882a593Smuzhiyun outb(val, TCO_TMR(tcobase));
134*4882a593Smuzhiyun val = inb(TCO_TMR(tcobase));
135*4882a593Smuzhiyun
136*4882a593Smuzhiyun if ((val & 0x3f) != tmrval)
137*4882a593Smuzhiyun ret = -EINVAL;
138*4882a593Smuzhiyun spin_unlock_irqrestore(&tco_lock, flags);
139*4882a593Smuzhiyun
140*4882a593Smuzhiyun if (ret)
141*4882a593Smuzhiyun return ret;
142*4882a593Smuzhiyun
143*4882a593Smuzhiyun heartbeat = t;
144*4882a593Smuzhiyun return 0;
145*4882a593Smuzhiyun }
146*4882a593Smuzhiyun
147*4882a593Smuzhiyun /*
148*4882a593Smuzhiyun * /dev/watchdog handling
149*4882a593Smuzhiyun */
150*4882a593Smuzhiyun
nv_tco_open(struct inode * inode,struct file * file)151*4882a593Smuzhiyun static int nv_tco_open(struct inode *inode, struct file *file)
152*4882a593Smuzhiyun {
153*4882a593Smuzhiyun /* /dev/watchdog can only be opened once */
154*4882a593Smuzhiyun if (test_and_set_bit(0, &timer_alive))
155*4882a593Smuzhiyun return -EBUSY;
156*4882a593Smuzhiyun
157*4882a593Smuzhiyun /* Reload and activate timer */
158*4882a593Smuzhiyun tco_timer_keepalive();
159*4882a593Smuzhiyun tco_timer_start();
160*4882a593Smuzhiyun return stream_open(inode, file);
161*4882a593Smuzhiyun }
162*4882a593Smuzhiyun
nv_tco_release(struct inode * inode,struct file * file)163*4882a593Smuzhiyun static int nv_tco_release(struct inode *inode, struct file *file)
164*4882a593Smuzhiyun {
165*4882a593Smuzhiyun /* Shut off the timer */
166*4882a593Smuzhiyun if (tco_expect_close == 42) {
167*4882a593Smuzhiyun tco_timer_stop();
168*4882a593Smuzhiyun } else {
169*4882a593Smuzhiyun pr_crit("Unexpected close, not stopping watchdog!\n");
170*4882a593Smuzhiyun tco_timer_keepalive();
171*4882a593Smuzhiyun }
172*4882a593Smuzhiyun clear_bit(0, &timer_alive);
173*4882a593Smuzhiyun tco_expect_close = 0;
174*4882a593Smuzhiyun return 0;
175*4882a593Smuzhiyun }
176*4882a593Smuzhiyun
nv_tco_write(struct file * file,const char __user * data,size_t len,loff_t * ppos)177*4882a593Smuzhiyun static ssize_t nv_tco_write(struct file *file, const char __user *data,
178*4882a593Smuzhiyun size_t len, loff_t *ppos)
179*4882a593Smuzhiyun {
180*4882a593Smuzhiyun /* See if we got the magic character 'V' and reload the timer */
181*4882a593Smuzhiyun if (len) {
182*4882a593Smuzhiyun if (!nowayout) {
183*4882a593Smuzhiyun size_t i;
184*4882a593Smuzhiyun
185*4882a593Smuzhiyun /*
186*4882a593Smuzhiyun * note: just in case someone wrote the magic character
187*4882a593Smuzhiyun * five months ago...
188*4882a593Smuzhiyun */
189*4882a593Smuzhiyun tco_expect_close = 0;
190*4882a593Smuzhiyun
191*4882a593Smuzhiyun /*
192*4882a593Smuzhiyun * scan to see whether or not we got the magic
193*4882a593Smuzhiyun * character
194*4882a593Smuzhiyun */
195*4882a593Smuzhiyun for (i = 0; i != len; i++) {
196*4882a593Smuzhiyun char c;
197*4882a593Smuzhiyun if (get_user(c, data + i))
198*4882a593Smuzhiyun return -EFAULT;
199*4882a593Smuzhiyun if (c == 'V')
200*4882a593Smuzhiyun tco_expect_close = 42;
201*4882a593Smuzhiyun }
202*4882a593Smuzhiyun }
203*4882a593Smuzhiyun
204*4882a593Smuzhiyun /* someone wrote to us, we should reload the timer */
205*4882a593Smuzhiyun tco_timer_keepalive();
206*4882a593Smuzhiyun }
207*4882a593Smuzhiyun return len;
208*4882a593Smuzhiyun }
209*4882a593Smuzhiyun
nv_tco_ioctl(struct file * file,unsigned int cmd,unsigned long arg)210*4882a593Smuzhiyun static long nv_tco_ioctl(struct file *file, unsigned int cmd,
211*4882a593Smuzhiyun unsigned long arg)
212*4882a593Smuzhiyun {
213*4882a593Smuzhiyun int new_options, retval = -EINVAL;
214*4882a593Smuzhiyun int new_heartbeat;
215*4882a593Smuzhiyun void __user *argp = (void __user *)arg;
216*4882a593Smuzhiyun int __user *p = argp;
217*4882a593Smuzhiyun static const struct watchdog_info ident = {
218*4882a593Smuzhiyun .options = WDIOF_SETTIMEOUT |
219*4882a593Smuzhiyun WDIOF_KEEPALIVEPING |
220*4882a593Smuzhiyun WDIOF_MAGICCLOSE,
221*4882a593Smuzhiyun .firmware_version = 0,
222*4882a593Smuzhiyun .identity = TCO_MODULE_NAME,
223*4882a593Smuzhiyun };
224*4882a593Smuzhiyun
225*4882a593Smuzhiyun switch (cmd) {
226*4882a593Smuzhiyun case WDIOC_GETSUPPORT:
227*4882a593Smuzhiyun return copy_to_user(argp, &ident, sizeof(ident)) ? -EFAULT : 0;
228*4882a593Smuzhiyun case WDIOC_GETSTATUS:
229*4882a593Smuzhiyun case WDIOC_GETBOOTSTATUS:
230*4882a593Smuzhiyun return put_user(0, p);
231*4882a593Smuzhiyun case WDIOC_SETOPTIONS:
232*4882a593Smuzhiyun if (get_user(new_options, p))
233*4882a593Smuzhiyun return -EFAULT;
234*4882a593Smuzhiyun if (new_options & WDIOS_DISABLECARD) {
235*4882a593Smuzhiyun tco_timer_stop();
236*4882a593Smuzhiyun retval = 0;
237*4882a593Smuzhiyun }
238*4882a593Smuzhiyun if (new_options & WDIOS_ENABLECARD) {
239*4882a593Smuzhiyun tco_timer_keepalive();
240*4882a593Smuzhiyun tco_timer_start();
241*4882a593Smuzhiyun retval = 0;
242*4882a593Smuzhiyun }
243*4882a593Smuzhiyun return retval;
244*4882a593Smuzhiyun case WDIOC_KEEPALIVE:
245*4882a593Smuzhiyun tco_timer_keepalive();
246*4882a593Smuzhiyun return 0;
247*4882a593Smuzhiyun case WDIOC_SETTIMEOUT:
248*4882a593Smuzhiyun if (get_user(new_heartbeat, p))
249*4882a593Smuzhiyun return -EFAULT;
250*4882a593Smuzhiyun if (tco_timer_set_heartbeat(new_heartbeat))
251*4882a593Smuzhiyun return -EINVAL;
252*4882a593Smuzhiyun tco_timer_keepalive();
253*4882a593Smuzhiyun fallthrough;
254*4882a593Smuzhiyun case WDIOC_GETTIMEOUT:
255*4882a593Smuzhiyun return put_user(heartbeat, p);
256*4882a593Smuzhiyun default:
257*4882a593Smuzhiyun return -ENOTTY;
258*4882a593Smuzhiyun }
259*4882a593Smuzhiyun }
260*4882a593Smuzhiyun
261*4882a593Smuzhiyun /*
262*4882a593Smuzhiyun * Kernel Interfaces
263*4882a593Smuzhiyun */
264*4882a593Smuzhiyun
265*4882a593Smuzhiyun static const struct file_operations nv_tco_fops = {
266*4882a593Smuzhiyun .owner = THIS_MODULE,
267*4882a593Smuzhiyun .llseek = no_llseek,
268*4882a593Smuzhiyun .write = nv_tco_write,
269*4882a593Smuzhiyun .unlocked_ioctl = nv_tco_ioctl,
270*4882a593Smuzhiyun .compat_ioctl = compat_ptr_ioctl,
271*4882a593Smuzhiyun .open = nv_tco_open,
272*4882a593Smuzhiyun .release = nv_tco_release,
273*4882a593Smuzhiyun };
274*4882a593Smuzhiyun
275*4882a593Smuzhiyun static struct miscdevice nv_tco_miscdev = {
276*4882a593Smuzhiyun .minor = WATCHDOG_MINOR,
277*4882a593Smuzhiyun .name = "watchdog",
278*4882a593Smuzhiyun .fops = &nv_tco_fops,
279*4882a593Smuzhiyun };
280*4882a593Smuzhiyun
281*4882a593Smuzhiyun /*
282*4882a593Smuzhiyun * Data for PCI driver interface
283*4882a593Smuzhiyun *
284*4882a593Smuzhiyun * This data only exists for exporting the supported
285*4882a593Smuzhiyun * PCI ids via MODULE_DEVICE_TABLE. We do not actually
286*4882a593Smuzhiyun * register a pci_driver, because someone else might one day
287*4882a593Smuzhiyun * want to register another driver on the same PCI id.
288*4882a593Smuzhiyun */
289*4882a593Smuzhiyun static const struct pci_device_id tco_pci_tbl[] = {
290*4882a593Smuzhiyun { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_SMBUS,
291*4882a593Smuzhiyun PCI_ANY_ID, PCI_ANY_ID, },
292*4882a593Smuzhiyun { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_SMBUS,
293*4882a593Smuzhiyun PCI_ANY_ID, PCI_ANY_ID, },
294*4882a593Smuzhiyun { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP78S_SMBUS,
295*4882a593Smuzhiyun PCI_ANY_ID, PCI_ANY_ID, },
296*4882a593Smuzhiyun { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP79_SMBUS,
297*4882a593Smuzhiyun PCI_ANY_ID, PCI_ANY_ID, },
298*4882a593Smuzhiyun { 0, }, /* End of list */
299*4882a593Smuzhiyun };
300*4882a593Smuzhiyun MODULE_DEVICE_TABLE(pci, tco_pci_tbl);
301*4882a593Smuzhiyun
302*4882a593Smuzhiyun /*
303*4882a593Smuzhiyun * Init & exit routines
304*4882a593Smuzhiyun */
305*4882a593Smuzhiyun
nv_tco_getdevice(void)306*4882a593Smuzhiyun static unsigned char nv_tco_getdevice(void)
307*4882a593Smuzhiyun {
308*4882a593Smuzhiyun struct pci_dev *dev = NULL;
309*4882a593Smuzhiyun u32 val;
310*4882a593Smuzhiyun
311*4882a593Smuzhiyun /* Find the PCI device */
312*4882a593Smuzhiyun for_each_pci_dev(dev) {
313*4882a593Smuzhiyun if (pci_match_id(tco_pci_tbl, dev) != NULL) {
314*4882a593Smuzhiyun tco_pci = dev;
315*4882a593Smuzhiyun break;
316*4882a593Smuzhiyun }
317*4882a593Smuzhiyun }
318*4882a593Smuzhiyun
319*4882a593Smuzhiyun if (!tco_pci)
320*4882a593Smuzhiyun return 0;
321*4882a593Smuzhiyun
322*4882a593Smuzhiyun /* Find the base io port */
323*4882a593Smuzhiyun pci_read_config_dword(tco_pci, 0x64, &val);
324*4882a593Smuzhiyun val &= 0xffff;
325*4882a593Smuzhiyun if (val == 0x0001 || val == 0x0000) {
326*4882a593Smuzhiyun /* Something is wrong here, bar isn't setup */
327*4882a593Smuzhiyun pr_err("failed to get tcobase address\n");
328*4882a593Smuzhiyun return 0;
329*4882a593Smuzhiyun }
330*4882a593Smuzhiyun val &= 0xff00;
331*4882a593Smuzhiyun tcobase = val + 0x40;
332*4882a593Smuzhiyun
333*4882a593Smuzhiyun if (!request_region(tcobase, 0x10, "NV TCO")) {
334*4882a593Smuzhiyun pr_err("I/O address 0x%04x already in use\n", tcobase);
335*4882a593Smuzhiyun return 0;
336*4882a593Smuzhiyun }
337*4882a593Smuzhiyun
338*4882a593Smuzhiyun /* Set a reasonable heartbeat before we stop the timer */
339*4882a593Smuzhiyun tco_timer_set_heartbeat(30);
340*4882a593Smuzhiyun
341*4882a593Smuzhiyun /*
342*4882a593Smuzhiyun * Stop the TCO before we change anything so we don't race with
343*4882a593Smuzhiyun * a zeroed timer.
344*4882a593Smuzhiyun */
345*4882a593Smuzhiyun tco_timer_keepalive();
346*4882a593Smuzhiyun tco_timer_stop();
347*4882a593Smuzhiyun
348*4882a593Smuzhiyun /* Disable SMI caused by TCO */
349*4882a593Smuzhiyun if (!request_region(MCP51_SMI_EN(tcobase), 4, "NV TCO")) {
350*4882a593Smuzhiyun pr_err("I/O address 0x%04x already in use\n",
351*4882a593Smuzhiyun MCP51_SMI_EN(tcobase));
352*4882a593Smuzhiyun goto out;
353*4882a593Smuzhiyun }
354*4882a593Smuzhiyun val = inl(MCP51_SMI_EN(tcobase));
355*4882a593Smuzhiyun val &= ~MCP51_SMI_EN_TCO;
356*4882a593Smuzhiyun outl(val, MCP51_SMI_EN(tcobase));
357*4882a593Smuzhiyun val = inl(MCP51_SMI_EN(tcobase));
358*4882a593Smuzhiyun release_region(MCP51_SMI_EN(tcobase), 4);
359*4882a593Smuzhiyun if (val & MCP51_SMI_EN_TCO) {
360*4882a593Smuzhiyun pr_err("Could not disable SMI caused by TCO\n");
361*4882a593Smuzhiyun goto out;
362*4882a593Smuzhiyun }
363*4882a593Smuzhiyun
364*4882a593Smuzhiyun /* Check chipset's NO_REBOOT bit */
365*4882a593Smuzhiyun pci_read_config_dword(tco_pci, MCP51_SMBUS_SETUP_B, &val);
366*4882a593Smuzhiyun val |= MCP51_SMBUS_SETUP_B_TCO_REBOOT;
367*4882a593Smuzhiyun pci_write_config_dword(tco_pci, MCP51_SMBUS_SETUP_B, val);
368*4882a593Smuzhiyun pci_read_config_dword(tco_pci, MCP51_SMBUS_SETUP_B, &val);
369*4882a593Smuzhiyun if (!(val & MCP51_SMBUS_SETUP_B_TCO_REBOOT)) {
370*4882a593Smuzhiyun pr_err("failed to reset NO_REBOOT flag, reboot disabled by hardware\n");
371*4882a593Smuzhiyun goto out;
372*4882a593Smuzhiyun }
373*4882a593Smuzhiyun
374*4882a593Smuzhiyun return 1;
375*4882a593Smuzhiyun out:
376*4882a593Smuzhiyun release_region(tcobase, 0x10);
377*4882a593Smuzhiyun return 0;
378*4882a593Smuzhiyun }
379*4882a593Smuzhiyun
nv_tco_init(struct platform_device * dev)380*4882a593Smuzhiyun static int nv_tco_init(struct platform_device *dev)
381*4882a593Smuzhiyun {
382*4882a593Smuzhiyun int ret;
383*4882a593Smuzhiyun
384*4882a593Smuzhiyun /* Check whether or not the hardware watchdog is there */
385*4882a593Smuzhiyun if (!nv_tco_getdevice())
386*4882a593Smuzhiyun return -ENODEV;
387*4882a593Smuzhiyun
388*4882a593Smuzhiyun /* Check to see if last reboot was due to watchdog timeout */
389*4882a593Smuzhiyun pr_info("Watchdog reboot %sdetected\n",
390*4882a593Smuzhiyun inl(TCO_STS(tcobase)) & TCO_STS_TCO2TO_STS ? "" : "not ");
391*4882a593Smuzhiyun
392*4882a593Smuzhiyun /* Clear out the old status */
393*4882a593Smuzhiyun outl(TCO_STS_RESET, TCO_STS(tcobase));
394*4882a593Smuzhiyun
395*4882a593Smuzhiyun /*
396*4882a593Smuzhiyun * Check that the heartbeat value is within it's range.
397*4882a593Smuzhiyun * If not, reset to the default.
398*4882a593Smuzhiyun */
399*4882a593Smuzhiyun if (tco_timer_set_heartbeat(heartbeat)) {
400*4882a593Smuzhiyun heartbeat = WATCHDOG_HEARTBEAT;
401*4882a593Smuzhiyun tco_timer_set_heartbeat(heartbeat);
402*4882a593Smuzhiyun pr_info("heartbeat value must be 2<heartbeat<39, using %d\n",
403*4882a593Smuzhiyun heartbeat);
404*4882a593Smuzhiyun }
405*4882a593Smuzhiyun
406*4882a593Smuzhiyun ret = misc_register(&nv_tco_miscdev);
407*4882a593Smuzhiyun if (ret != 0) {
408*4882a593Smuzhiyun pr_err("cannot register miscdev on minor=%d (err=%d)\n",
409*4882a593Smuzhiyun WATCHDOG_MINOR, ret);
410*4882a593Smuzhiyun goto unreg_region;
411*4882a593Smuzhiyun }
412*4882a593Smuzhiyun
413*4882a593Smuzhiyun clear_bit(0, &timer_alive);
414*4882a593Smuzhiyun
415*4882a593Smuzhiyun tco_timer_stop();
416*4882a593Smuzhiyun
417*4882a593Smuzhiyun pr_info("initialized (0x%04x). heartbeat=%d sec (nowayout=%d)\n",
418*4882a593Smuzhiyun tcobase, heartbeat, nowayout);
419*4882a593Smuzhiyun
420*4882a593Smuzhiyun return 0;
421*4882a593Smuzhiyun
422*4882a593Smuzhiyun unreg_region:
423*4882a593Smuzhiyun release_region(tcobase, 0x10);
424*4882a593Smuzhiyun return ret;
425*4882a593Smuzhiyun }
426*4882a593Smuzhiyun
nv_tco_cleanup(void)427*4882a593Smuzhiyun static void nv_tco_cleanup(void)
428*4882a593Smuzhiyun {
429*4882a593Smuzhiyun u32 val;
430*4882a593Smuzhiyun
431*4882a593Smuzhiyun /* Stop the timer before we leave */
432*4882a593Smuzhiyun if (!nowayout)
433*4882a593Smuzhiyun tco_timer_stop();
434*4882a593Smuzhiyun
435*4882a593Smuzhiyun /* Set the NO_REBOOT bit to prevent later reboots, just for sure */
436*4882a593Smuzhiyun pci_read_config_dword(tco_pci, MCP51_SMBUS_SETUP_B, &val);
437*4882a593Smuzhiyun val &= ~MCP51_SMBUS_SETUP_B_TCO_REBOOT;
438*4882a593Smuzhiyun pci_write_config_dword(tco_pci, MCP51_SMBUS_SETUP_B, val);
439*4882a593Smuzhiyun pci_read_config_dword(tco_pci, MCP51_SMBUS_SETUP_B, &val);
440*4882a593Smuzhiyun if (val & MCP51_SMBUS_SETUP_B_TCO_REBOOT) {
441*4882a593Smuzhiyun pr_crit("Couldn't unset REBOOT bit. Machine may soon reset\n");
442*4882a593Smuzhiyun }
443*4882a593Smuzhiyun
444*4882a593Smuzhiyun /* Deregister */
445*4882a593Smuzhiyun misc_deregister(&nv_tco_miscdev);
446*4882a593Smuzhiyun release_region(tcobase, 0x10);
447*4882a593Smuzhiyun }
448*4882a593Smuzhiyun
nv_tco_remove(struct platform_device * dev)449*4882a593Smuzhiyun static int nv_tco_remove(struct platform_device *dev)
450*4882a593Smuzhiyun {
451*4882a593Smuzhiyun if (tcobase)
452*4882a593Smuzhiyun nv_tco_cleanup();
453*4882a593Smuzhiyun
454*4882a593Smuzhiyun return 0;
455*4882a593Smuzhiyun }
456*4882a593Smuzhiyun
nv_tco_shutdown(struct platform_device * dev)457*4882a593Smuzhiyun static void nv_tco_shutdown(struct platform_device *dev)
458*4882a593Smuzhiyun {
459*4882a593Smuzhiyun u32 val;
460*4882a593Smuzhiyun
461*4882a593Smuzhiyun tco_timer_stop();
462*4882a593Smuzhiyun
463*4882a593Smuzhiyun /* Some BIOSes fail the POST (once) if the NO_REBOOT flag is not
464*4882a593Smuzhiyun * unset during shutdown. */
465*4882a593Smuzhiyun pci_read_config_dword(tco_pci, MCP51_SMBUS_SETUP_B, &val);
466*4882a593Smuzhiyun val &= ~MCP51_SMBUS_SETUP_B_TCO_REBOOT;
467*4882a593Smuzhiyun pci_write_config_dword(tco_pci, MCP51_SMBUS_SETUP_B, val);
468*4882a593Smuzhiyun }
469*4882a593Smuzhiyun
470*4882a593Smuzhiyun static struct platform_driver nv_tco_driver = {
471*4882a593Smuzhiyun .probe = nv_tco_init,
472*4882a593Smuzhiyun .remove = nv_tco_remove,
473*4882a593Smuzhiyun .shutdown = nv_tco_shutdown,
474*4882a593Smuzhiyun .driver = {
475*4882a593Smuzhiyun .name = TCO_MODULE_NAME,
476*4882a593Smuzhiyun },
477*4882a593Smuzhiyun };
478*4882a593Smuzhiyun
nv_tco_init_module(void)479*4882a593Smuzhiyun static int __init nv_tco_init_module(void)
480*4882a593Smuzhiyun {
481*4882a593Smuzhiyun int err;
482*4882a593Smuzhiyun
483*4882a593Smuzhiyun pr_info("NV TCO WatchDog Timer Driver v%s\n", TCO_VERSION);
484*4882a593Smuzhiyun
485*4882a593Smuzhiyun err = platform_driver_register(&nv_tco_driver);
486*4882a593Smuzhiyun if (err)
487*4882a593Smuzhiyun return err;
488*4882a593Smuzhiyun
489*4882a593Smuzhiyun nv_tco_platform_device = platform_device_register_simple(
490*4882a593Smuzhiyun TCO_MODULE_NAME, -1, NULL, 0);
491*4882a593Smuzhiyun if (IS_ERR(nv_tco_platform_device)) {
492*4882a593Smuzhiyun err = PTR_ERR(nv_tco_platform_device);
493*4882a593Smuzhiyun goto unreg_platform_driver;
494*4882a593Smuzhiyun }
495*4882a593Smuzhiyun
496*4882a593Smuzhiyun return 0;
497*4882a593Smuzhiyun
498*4882a593Smuzhiyun unreg_platform_driver:
499*4882a593Smuzhiyun platform_driver_unregister(&nv_tco_driver);
500*4882a593Smuzhiyun return err;
501*4882a593Smuzhiyun }
502*4882a593Smuzhiyun
nv_tco_cleanup_module(void)503*4882a593Smuzhiyun static void __exit nv_tco_cleanup_module(void)
504*4882a593Smuzhiyun {
505*4882a593Smuzhiyun platform_device_unregister(nv_tco_platform_device);
506*4882a593Smuzhiyun platform_driver_unregister(&nv_tco_driver);
507*4882a593Smuzhiyun pr_info("NV TCO Watchdog Module Unloaded\n");
508*4882a593Smuzhiyun }
509*4882a593Smuzhiyun
510*4882a593Smuzhiyun module_init(nv_tco_init_module);
511*4882a593Smuzhiyun module_exit(nv_tco_cleanup_module);
512*4882a593Smuzhiyun
513*4882a593Smuzhiyun MODULE_AUTHOR("Mike Waychison");
514*4882a593Smuzhiyun MODULE_DESCRIPTION("TCO timer driver for NV chipsets");
515*4882a593Smuzhiyun MODULE_LICENSE("GPL");
516