1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * MOXA ART SoCs watchdog driver.
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * Copyright (C) 2013 Jonas Jensen
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * Jonas Jensen <jonas.jensen@gmail.com>
7*4882a593Smuzhiyun *
8*4882a593Smuzhiyun * This file is licensed under the terms of the GNU General Public
9*4882a593Smuzhiyun * License version 2. This program is licensed "as is" without any
10*4882a593Smuzhiyun * warranty of any kind, whether express or implied.
11*4882a593Smuzhiyun */
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun #include <linux/clk.h>
14*4882a593Smuzhiyun #include <linux/io.h>
15*4882a593Smuzhiyun #include <linux/module.h>
16*4882a593Smuzhiyun #include <linux/mod_devicetable.h>
17*4882a593Smuzhiyun #include <linux/err.h>
18*4882a593Smuzhiyun #include <linux/kernel.h>
19*4882a593Smuzhiyun #include <linux/platform_device.h>
20*4882a593Smuzhiyun #include <linux/watchdog.h>
21*4882a593Smuzhiyun #include <linux/moduleparam.h>
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun #define REG_COUNT 0x4
24*4882a593Smuzhiyun #define REG_MODE 0x8
25*4882a593Smuzhiyun #define REG_ENABLE 0xC
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun struct moxart_wdt_dev {
28*4882a593Smuzhiyun struct watchdog_device dev;
29*4882a593Smuzhiyun void __iomem *base;
30*4882a593Smuzhiyun unsigned int clock_frequency;
31*4882a593Smuzhiyun };
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun static int heartbeat;
34*4882a593Smuzhiyun
moxart_wdt_restart(struct watchdog_device * wdt_dev,unsigned long action,void * data)35*4882a593Smuzhiyun static int moxart_wdt_restart(struct watchdog_device *wdt_dev,
36*4882a593Smuzhiyun unsigned long action, void *data)
37*4882a593Smuzhiyun {
38*4882a593Smuzhiyun struct moxart_wdt_dev *moxart_wdt = watchdog_get_drvdata(wdt_dev);
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun writel(1, moxart_wdt->base + REG_COUNT);
41*4882a593Smuzhiyun writel(0x5ab9, moxart_wdt->base + REG_MODE);
42*4882a593Smuzhiyun writel(0x03, moxart_wdt->base + REG_ENABLE);
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun return 0;
45*4882a593Smuzhiyun }
46*4882a593Smuzhiyun
moxart_wdt_stop(struct watchdog_device * wdt_dev)47*4882a593Smuzhiyun static int moxart_wdt_stop(struct watchdog_device *wdt_dev)
48*4882a593Smuzhiyun {
49*4882a593Smuzhiyun struct moxart_wdt_dev *moxart_wdt = watchdog_get_drvdata(wdt_dev);
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun writel(0, moxart_wdt->base + REG_ENABLE);
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun return 0;
54*4882a593Smuzhiyun }
55*4882a593Smuzhiyun
moxart_wdt_start(struct watchdog_device * wdt_dev)56*4882a593Smuzhiyun static int moxart_wdt_start(struct watchdog_device *wdt_dev)
57*4882a593Smuzhiyun {
58*4882a593Smuzhiyun struct moxart_wdt_dev *moxart_wdt = watchdog_get_drvdata(wdt_dev);
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun writel(moxart_wdt->clock_frequency * wdt_dev->timeout,
61*4882a593Smuzhiyun moxart_wdt->base + REG_COUNT);
62*4882a593Smuzhiyun writel(0x5ab9, moxart_wdt->base + REG_MODE);
63*4882a593Smuzhiyun writel(0x03, moxart_wdt->base + REG_ENABLE);
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun return 0;
66*4882a593Smuzhiyun }
67*4882a593Smuzhiyun
moxart_wdt_set_timeout(struct watchdog_device * wdt_dev,unsigned int timeout)68*4882a593Smuzhiyun static int moxart_wdt_set_timeout(struct watchdog_device *wdt_dev,
69*4882a593Smuzhiyun unsigned int timeout)
70*4882a593Smuzhiyun {
71*4882a593Smuzhiyun wdt_dev->timeout = timeout;
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun return 0;
74*4882a593Smuzhiyun }
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun static const struct watchdog_info moxart_wdt_info = {
77*4882a593Smuzhiyun .identity = "moxart-wdt",
78*4882a593Smuzhiyun .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING |
79*4882a593Smuzhiyun WDIOF_MAGICCLOSE,
80*4882a593Smuzhiyun };
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun static const struct watchdog_ops moxart_wdt_ops = {
83*4882a593Smuzhiyun .owner = THIS_MODULE,
84*4882a593Smuzhiyun .start = moxart_wdt_start,
85*4882a593Smuzhiyun .stop = moxart_wdt_stop,
86*4882a593Smuzhiyun .set_timeout = moxart_wdt_set_timeout,
87*4882a593Smuzhiyun .restart = moxart_wdt_restart,
88*4882a593Smuzhiyun };
89*4882a593Smuzhiyun
moxart_wdt_probe(struct platform_device * pdev)90*4882a593Smuzhiyun static int moxart_wdt_probe(struct platform_device *pdev)
91*4882a593Smuzhiyun {
92*4882a593Smuzhiyun struct moxart_wdt_dev *moxart_wdt;
93*4882a593Smuzhiyun struct device *dev = &pdev->dev;
94*4882a593Smuzhiyun struct clk *clk;
95*4882a593Smuzhiyun int err;
96*4882a593Smuzhiyun unsigned int max_timeout;
97*4882a593Smuzhiyun bool nowayout = WATCHDOG_NOWAYOUT;
98*4882a593Smuzhiyun
99*4882a593Smuzhiyun moxart_wdt = devm_kzalloc(dev, sizeof(*moxart_wdt), GFP_KERNEL);
100*4882a593Smuzhiyun if (!moxart_wdt)
101*4882a593Smuzhiyun return -ENOMEM;
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun platform_set_drvdata(pdev, moxart_wdt);
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun moxart_wdt->base = devm_platform_ioremap_resource(pdev, 0);
106*4882a593Smuzhiyun if (IS_ERR(moxart_wdt->base))
107*4882a593Smuzhiyun return PTR_ERR(moxart_wdt->base);
108*4882a593Smuzhiyun
109*4882a593Smuzhiyun clk = devm_clk_get(dev, NULL);
110*4882a593Smuzhiyun if (IS_ERR(clk)) {
111*4882a593Smuzhiyun pr_err("%s: of_clk_get failed\n", __func__);
112*4882a593Smuzhiyun return PTR_ERR(clk);
113*4882a593Smuzhiyun }
114*4882a593Smuzhiyun
115*4882a593Smuzhiyun moxart_wdt->clock_frequency = clk_get_rate(clk);
116*4882a593Smuzhiyun if (moxart_wdt->clock_frequency == 0) {
117*4882a593Smuzhiyun pr_err("%s: incorrect clock frequency\n", __func__);
118*4882a593Smuzhiyun return -EINVAL;
119*4882a593Smuzhiyun }
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun max_timeout = UINT_MAX / moxart_wdt->clock_frequency;
122*4882a593Smuzhiyun
123*4882a593Smuzhiyun moxart_wdt->dev.info = &moxart_wdt_info;
124*4882a593Smuzhiyun moxart_wdt->dev.ops = &moxart_wdt_ops;
125*4882a593Smuzhiyun moxart_wdt->dev.timeout = max_timeout;
126*4882a593Smuzhiyun moxart_wdt->dev.min_timeout = 1;
127*4882a593Smuzhiyun moxart_wdt->dev.max_timeout = max_timeout;
128*4882a593Smuzhiyun moxart_wdt->dev.parent = dev;
129*4882a593Smuzhiyun
130*4882a593Smuzhiyun watchdog_init_timeout(&moxart_wdt->dev, heartbeat, dev);
131*4882a593Smuzhiyun watchdog_set_nowayout(&moxart_wdt->dev, nowayout);
132*4882a593Smuzhiyun watchdog_set_restart_priority(&moxart_wdt->dev, 128);
133*4882a593Smuzhiyun
134*4882a593Smuzhiyun watchdog_set_drvdata(&moxart_wdt->dev, moxart_wdt);
135*4882a593Smuzhiyun
136*4882a593Smuzhiyun watchdog_stop_on_unregister(&moxart_wdt->dev);
137*4882a593Smuzhiyun err = devm_watchdog_register_device(dev, &moxart_wdt->dev);
138*4882a593Smuzhiyun if (err)
139*4882a593Smuzhiyun return err;
140*4882a593Smuzhiyun
141*4882a593Smuzhiyun dev_dbg(dev, "Watchdog enabled (heartbeat=%d sec, nowayout=%d)\n",
142*4882a593Smuzhiyun moxart_wdt->dev.timeout, nowayout);
143*4882a593Smuzhiyun
144*4882a593Smuzhiyun return 0;
145*4882a593Smuzhiyun }
146*4882a593Smuzhiyun
147*4882a593Smuzhiyun static const struct of_device_id moxart_watchdog_match[] = {
148*4882a593Smuzhiyun { .compatible = "moxa,moxart-watchdog" },
149*4882a593Smuzhiyun { },
150*4882a593Smuzhiyun };
151*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, moxart_watchdog_match);
152*4882a593Smuzhiyun
153*4882a593Smuzhiyun static struct platform_driver moxart_wdt_driver = {
154*4882a593Smuzhiyun .probe = moxart_wdt_probe,
155*4882a593Smuzhiyun .driver = {
156*4882a593Smuzhiyun .name = "moxart-watchdog",
157*4882a593Smuzhiyun .of_match_table = moxart_watchdog_match,
158*4882a593Smuzhiyun },
159*4882a593Smuzhiyun };
160*4882a593Smuzhiyun module_platform_driver(moxart_wdt_driver);
161*4882a593Smuzhiyun
162*4882a593Smuzhiyun module_param(heartbeat, int, 0);
163*4882a593Smuzhiyun MODULE_PARM_DESC(heartbeat, "Watchdog heartbeat in seconds");
164*4882a593Smuzhiyun
165*4882a593Smuzhiyun MODULE_DESCRIPTION("MOXART watchdog driver");
166*4882a593Smuzhiyun MODULE_LICENSE("GPL");
167*4882a593Smuzhiyun MODULE_AUTHOR("Jonas Jensen <jonas.jensen@gmail.com>");
168