1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (c) 2016 BayLibre, SAS.
4*4882a593Smuzhiyun * Author: Neil Armstrong <narmstrong@baylibre.com>
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun #include <linux/clk.h>
8*4882a593Smuzhiyun #include <linux/err.h>
9*4882a593Smuzhiyun #include <linux/io.h>
10*4882a593Smuzhiyun #include <linux/module.h>
11*4882a593Smuzhiyun #include <linux/of.h>
12*4882a593Smuzhiyun #include <linux/platform_device.h>
13*4882a593Smuzhiyun #include <linux/slab.h>
14*4882a593Smuzhiyun #include <linux/types.h>
15*4882a593Smuzhiyun #include <linux/watchdog.h>
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun #define DEFAULT_TIMEOUT 30 /* seconds */
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun #define GXBB_WDT_CTRL_REG 0x0
20*4882a593Smuzhiyun #define GXBB_WDT_TCNT_REG 0x8
21*4882a593Smuzhiyun #define GXBB_WDT_RSET_REG 0xc
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun #define GXBB_WDT_CTRL_CLKDIV_EN BIT(25)
24*4882a593Smuzhiyun #define GXBB_WDT_CTRL_CLK_EN BIT(24)
25*4882a593Smuzhiyun #define GXBB_WDT_CTRL_EE_RESET BIT(21)
26*4882a593Smuzhiyun #define GXBB_WDT_CTRL_EN BIT(18)
27*4882a593Smuzhiyun #define GXBB_WDT_CTRL_DIV_MASK (BIT(18) - 1)
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun #define GXBB_WDT_TCNT_SETUP_MASK (BIT(16) - 1)
30*4882a593Smuzhiyun #define GXBB_WDT_TCNT_CNT_SHIFT 16
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun struct meson_gxbb_wdt {
33*4882a593Smuzhiyun void __iomem *reg_base;
34*4882a593Smuzhiyun struct watchdog_device wdt_dev;
35*4882a593Smuzhiyun struct clk *clk;
36*4882a593Smuzhiyun };
37*4882a593Smuzhiyun
meson_gxbb_wdt_start(struct watchdog_device * wdt_dev)38*4882a593Smuzhiyun static int meson_gxbb_wdt_start(struct watchdog_device *wdt_dev)
39*4882a593Smuzhiyun {
40*4882a593Smuzhiyun struct meson_gxbb_wdt *data = watchdog_get_drvdata(wdt_dev);
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun writel(readl(data->reg_base + GXBB_WDT_CTRL_REG) | GXBB_WDT_CTRL_EN,
43*4882a593Smuzhiyun data->reg_base + GXBB_WDT_CTRL_REG);
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun return 0;
46*4882a593Smuzhiyun }
47*4882a593Smuzhiyun
meson_gxbb_wdt_stop(struct watchdog_device * wdt_dev)48*4882a593Smuzhiyun static int meson_gxbb_wdt_stop(struct watchdog_device *wdt_dev)
49*4882a593Smuzhiyun {
50*4882a593Smuzhiyun struct meson_gxbb_wdt *data = watchdog_get_drvdata(wdt_dev);
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun writel(readl(data->reg_base + GXBB_WDT_CTRL_REG) & ~GXBB_WDT_CTRL_EN,
53*4882a593Smuzhiyun data->reg_base + GXBB_WDT_CTRL_REG);
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun return 0;
56*4882a593Smuzhiyun }
57*4882a593Smuzhiyun
meson_gxbb_wdt_ping(struct watchdog_device * wdt_dev)58*4882a593Smuzhiyun static int meson_gxbb_wdt_ping(struct watchdog_device *wdt_dev)
59*4882a593Smuzhiyun {
60*4882a593Smuzhiyun struct meson_gxbb_wdt *data = watchdog_get_drvdata(wdt_dev);
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun writel(0, data->reg_base + GXBB_WDT_RSET_REG);
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun return 0;
65*4882a593Smuzhiyun }
66*4882a593Smuzhiyun
meson_gxbb_wdt_set_timeout(struct watchdog_device * wdt_dev,unsigned int timeout)67*4882a593Smuzhiyun static int meson_gxbb_wdt_set_timeout(struct watchdog_device *wdt_dev,
68*4882a593Smuzhiyun unsigned int timeout)
69*4882a593Smuzhiyun {
70*4882a593Smuzhiyun struct meson_gxbb_wdt *data = watchdog_get_drvdata(wdt_dev);
71*4882a593Smuzhiyun unsigned long tcnt = timeout * 1000;
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun if (tcnt > GXBB_WDT_TCNT_SETUP_MASK)
74*4882a593Smuzhiyun tcnt = GXBB_WDT_TCNT_SETUP_MASK;
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun wdt_dev->timeout = timeout;
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun meson_gxbb_wdt_ping(wdt_dev);
79*4882a593Smuzhiyun
80*4882a593Smuzhiyun writel(tcnt, data->reg_base + GXBB_WDT_TCNT_REG);
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun return 0;
83*4882a593Smuzhiyun }
84*4882a593Smuzhiyun
meson_gxbb_wdt_get_timeleft(struct watchdog_device * wdt_dev)85*4882a593Smuzhiyun static unsigned int meson_gxbb_wdt_get_timeleft(struct watchdog_device *wdt_dev)
86*4882a593Smuzhiyun {
87*4882a593Smuzhiyun struct meson_gxbb_wdt *data = watchdog_get_drvdata(wdt_dev);
88*4882a593Smuzhiyun unsigned long reg;
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun reg = readl(data->reg_base + GXBB_WDT_TCNT_REG);
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun return ((reg & GXBB_WDT_TCNT_SETUP_MASK) -
93*4882a593Smuzhiyun (reg >> GXBB_WDT_TCNT_CNT_SHIFT)) / 1000;
94*4882a593Smuzhiyun }
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun static const struct watchdog_ops meson_gxbb_wdt_ops = {
97*4882a593Smuzhiyun .start = meson_gxbb_wdt_start,
98*4882a593Smuzhiyun .stop = meson_gxbb_wdt_stop,
99*4882a593Smuzhiyun .ping = meson_gxbb_wdt_ping,
100*4882a593Smuzhiyun .set_timeout = meson_gxbb_wdt_set_timeout,
101*4882a593Smuzhiyun .get_timeleft = meson_gxbb_wdt_get_timeleft,
102*4882a593Smuzhiyun };
103*4882a593Smuzhiyun
104*4882a593Smuzhiyun static const struct watchdog_info meson_gxbb_wdt_info = {
105*4882a593Smuzhiyun .identity = "Meson GXBB Watchdog",
106*4882a593Smuzhiyun .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE,
107*4882a593Smuzhiyun };
108*4882a593Smuzhiyun
meson_gxbb_wdt_resume(struct device * dev)109*4882a593Smuzhiyun static int __maybe_unused meson_gxbb_wdt_resume(struct device *dev)
110*4882a593Smuzhiyun {
111*4882a593Smuzhiyun struct meson_gxbb_wdt *data = dev_get_drvdata(dev);
112*4882a593Smuzhiyun
113*4882a593Smuzhiyun if (watchdog_active(&data->wdt_dev))
114*4882a593Smuzhiyun meson_gxbb_wdt_start(&data->wdt_dev);
115*4882a593Smuzhiyun
116*4882a593Smuzhiyun return 0;
117*4882a593Smuzhiyun }
118*4882a593Smuzhiyun
meson_gxbb_wdt_suspend(struct device * dev)119*4882a593Smuzhiyun static int __maybe_unused meson_gxbb_wdt_suspend(struct device *dev)
120*4882a593Smuzhiyun {
121*4882a593Smuzhiyun struct meson_gxbb_wdt *data = dev_get_drvdata(dev);
122*4882a593Smuzhiyun
123*4882a593Smuzhiyun if (watchdog_active(&data->wdt_dev))
124*4882a593Smuzhiyun meson_gxbb_wdt_stop(&data->wdt_dev);
125*4882a593Smuzhiyun
126*4882a593Smuzhiyun return 0;
127*4882a593Smuzhiyun }
128*4882a593Smuzhiyun
129*4882a593Smuzhiyun static const struct dev_pm_ops meson_gxbb_wdt_pm_ops = {
130*4882a593Smuzhiyun SET_SYSTEM_SLEEP_PM_OPS(meson_gxbb_wdt_suspend, meson_gxbb_wdt_resume)
131*4882a593Smuzhiyun };
132*4882a593Smuzhiyun
133*4882a593Smuzhiyun static const struct of_device_id meson_gxbb_wdt_dt_ids[] = {
134*4882a593Smuzhiyun { .compatible = "amlogic,meson-gxbb-wdt", },
135*4882a593Smuzhiyun { /* sentinel */ },
136*4882a593Smuzhiyun };
137*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, meson_gxbb_wdt_dt_ids);
138*4882a593Smuzhiyun
meson_clk_disable_unprepare(void * data)139*4882a593Smuzhiyun static void meson_clk_disable_unprepare(void *data)
140*4882a593Smuzhiyun {
141*4882a593Smuzhiyun clk_disable_unprepare(data);
142*4882a593Smuzhiyun }
143*4882a593Smuzhiyun
meson_gxbb_wdt_probe(struct platform_device * pdev)144*4882a593Smuzhiyun static int meson_gxbb_wdt_probe(struct platform_device *pdev)
145*4882a593Smuzhiyun {
146*4882a593Smuzhiyun struct device *dev = &pdev->dev;
147*4882a593Smuzhiyun struct meson_gxbb_wdt *data;
148*4882a593Smuzhiyun int ret;
149*4882a593Smuzhiyun
150*4882a593Smuzhiyun data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
151*4882a593Smuzhiyun if (!data)
152*4882a593Smuzhiyun return -ENOMEM;
153*4882a593Smuzhiyun
154*4882a593Smuzhiyun data->reg_base = devm_platform_ioremap_resource(pdev, 0);
155*4882a593Smuzhiyun if (IS_ERR(data->reg_base))
156*4882a593Smuzhiyun return PTR_ERR(data->reg_base);
157*4882a593Smuzhiyun
158*4882a593Smuzhiyun data->clk = devm_clk_get(dev, NULL);
159*4882a593Smuzhiyun if (IS_ERR(data->clk))
160*4882a593Smuzhiyun return PTR_ERR(data->clk);
161*4882a593Smuzhiyun
162*4882a593Smuzhiyun ret = clk_prepare_enable(data->clk);
163*4882a593Smuzhiyun if (ret)
164*4882a593Smuzhiyun return ret;
165*4882a593Smuzhiyun ret = devm_add_action_or_reset(dev, meson_clk_disable_unprepare,
166*4882a593Smuzhiyun data->clk);
167*4882a593Smuzhiyun if (ret)
168*4882a593Smuzhiyun return ret;
169*4882a593Smuzhiyun
170*4882a593Smuzhiyun platform_set_drvdata(pdev, data);
171*4882a593Smuzhiyun
172*4882a593Smuzhiyun data->wdt_dev.parent = dev;
173*4882a593Smuzhiyun data->wdt_dev.info = &meson_gxbb_wdt_info;
174*4882a593Smuzhiyun data->wdt_dev.ops = &meson_gxbb_wdt_ops;
175*4882a593Smuzhiyun data->wdt_dev.max_hw_heartbeat_ms = GXBB_WDT_TCNT_SETUP_MASK;
176*4882a593Smuzhiyun data->wdt_dev.min_timeout = 1;
177*4882a593Smuzhiyun data->wdt_dev.timeout = DEFAULT_TIMEOUT;
178*4882a593Smuzhiyun watchdog_set_drvdata(&data->wdt_dev, data);
179*4882a593Smuzhiyun
180*4882a593Smuzhiyun /* Setup with 1ms timebase */
181*4882a593Smuzhiyun writel(((clk_get_rate(data->clk) / 1000) & GXBB_WDT_CTRL_DIV_MASK) |
182*4882a593Smuzhiyun GXBB_WDT_CTRL_EE_RESET |
183*4882a593Smuzhiyun GXBB_WDT_CTRL_CLK_EN |
184*4882a593Smuzhiyun GXBB_WDT_CTRL_CLKDIV_EN,
185*4882a593Smuzhiyun data->reg_base + GXBB_WDT_CTRL_REG);
186*4882a593Smuzhiyun
187*4882a593Smuzhiyun meson_gxbb_wdt_set_timeout(&data->wdt_dev, data->wdt_dev.timeout);
188*4882a593Smuzhiyun
189*4882a593Smuzhiyun watchdog_stop_on_reboot(&data->wdt_dev);
190*4882a593Smuzhiyun return devm_watchdog_register_device(dev, &data->wdt_dev);
191*4882a593Smuzhiyun }
192*4882a593Smuzhiyun
193*4882a593Smuzhiyun static struct platform_driver meson_gxbb_wdt_driver = {
194*4882a593Smuzhiyun .probe = meson_gxbb_wdt_probe,
195*4882a593Smuzhiyun .driver = {
196*4882a593Smuzhiyun .name = "meson-gxbb-wdt",
197*4882a593Smuzhiyun .pm = &meson_gxbb_wdt_pm_ops,
198*4882a593Smuzhiyun .of_match_table = meson_gxbb_wdt_dt_ids,
199*4882a593Smuzhiyun },
200*4882a593Smuzhiyun };
201*4882a593Smuzhiyun
202*4882a593Smuzhiyun module_platform_driver(meson_gxbb_wdt_driver);
203*4882a593Smuzhiyun
204*4882a593Smuzhiyun MODULE_AUTHOR("Neil Armstrong <narmstrong@baylibre.com>");
205*4882a593Smuzhiyun MODULE_DESCRIPTION("Amlogic Meson GXBB Watchdog timer driver");
206*4882a593Smuzhiyun MODULE_LICENSE("Dual BSD/GPL");
207