xref: /OK3568_Linux_fs/kernel/drivers/watchdog/max63xx_wdt.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun  * drivers/char/watchdog/max63xx_wdt.c
3*4882a593Smuzhiyun  *
4*4882a593Smuzhiyun  * Driver for max63{69,70,71,72,73,74} watchdog timers
5*4882a593Smuzhiyun  *
6*4882a593Smuzhiyun  * Copyright (C) 2009 Marc Zyngier <maz@misterjones.org>
7*4882a593Smuzhiyun  *
8*4882a593Smuzhiyun  * This file is licensed under the terms of the GNU General Public
9*4882a593Smuzhiyun  * License version 2. This program is licensed "as is" without any
10*4882a593Smuzhiyun  * warranty of any kind, whether express or implied.
11*4882a593Smuzhiyun  *
12*4882a593Smuzhiyun  * This driver assumes the watchdog pins are memory mapped (as it is
13*4882a593Smuzhiyun  * the case for the Arcom Zeus). Should it be connected over GPIOs or
14*4882a593Smuzhiyun  * another interface, some abstraction will have to be introduced.
15*4882a593Smuzhiyun  */
16*4882a593Smuzhiyun 
17*4882a593Smuzhiyun #include <linux/err.h>
18*4882a593Smuzhiyun #include <linux/module.h>
19*4882a593Smuzhiyun #include <linux/moduleparam.h>
20*4882a593Smuzhiyun #include <linux/mod_devicetable.h>
21*4882a593Smuzhiyun #include <linux/types.h>
22*4882a593Smuzhiyun #include <linux/kernel.h>
23*4882a593Smuzhiyun #include <linux/watchdog.h>
24*4882a593Smuzhiyun #include <linux/bitops.h>
25*4882a593Smuzhiyun #include <linux/platform_device.h>
26*4882a593Smuzhiyun #include <linux/spinlock.h>
27*4882a593Smuzhiyun #include <linux/io.h>
28*4882a593Smuzhiyun #include <linux/slab.h>
29*4882a593Smuzhiyun 
30*4882a593Smuzhiyun #define DEFAULT_HEARTBEAT 60
31*4882a593Smuzhiyun #define MAX_HEARTBEAT     60
32*4882a593Smuzhiyun 
33*4882a593Smuzhiyun static unsigned int heartbeat = DEFAULT_HEARTBEAT;
34*4882a593Smuzhiyun static bool nowayout  = WATCHDOG_NOWAYOUT;
35*4882a593Smuzhiyun 
36*4882a593Smuzhiyun /*
37*4882a593Smuzhiyun  * Memory mapping: a single byte, 3 first lower bits to select bit 3
38*4882a593Smuzhiyun  * to ping the watchdog.
39*4882a593Smuzhiyun  */
40*4882a593Smuzhiyun #define MAX6369_WDSET	(7 << 0)
41*4882a593Smuzhiyun #define MAX6369_WDI	(1 << 3)
42*4882a593Smuzhiyun 
43*4882a593Smuzhiyun #define MAX6369_WDSET_DISABLED	3
44*4882a593Smuzhiyun 
45*4882a593Smuzhiyun static int nodelay;
46*4882a593Smuzhiyun 
47*4882a593Smuzhiyun struct max63xx_wdt {
48*4882a593Smuzhiyun 	struct watchdog_device wdd;
49*4882a593Smuzhiyun 	const struct max63xx_timeout *timeout;
50*4882a593Smuzhiyun 
51*4882a593Smuzhiyun 	/* memory mapping */
52*4882a593Smuzhiyun 	void __iomem *base;
53*4882a593Smuzhiyun 	spinlock_t lock;
54*4882a593Smuzhiyun 
55*4882a593Smuzhiyun 	/* WDI and WSET bits write access routines */
56*4882a593Smuzhiyun 	void (*ping)(struct max63xx_wdt *wdt);
57*4882a593Smuzhiyun 	void (*set)(struct max63xx_wdt *wdt, u8 set);
58*4882a593Smuzhiyun };
59*4882a593Smuzhiyun 
60*4882a593Smuzhiyun /*
61*4882a593Smuzhiyun  * The timeout values used are actually the absolute minimum the chip
62*4882a593Smuzhiyun  * offers. Typical values on my board are slightly over twice as long
63*4882a593Smuzhiyun  * (10s setting ends up with a 25s timeout), and can be up to 3 times
64*4882a593Smuzhiyun  * the nominal setting (according to the datasheet). So please take
65*4882a593Smuzhiyun  * these values with a grain of salt. Same goes for the initial delay
66*4882a593Smuzhiyun  * "feature". Only max6373/74 have a few settings without this initial
67*4882a593Smuzhiyun  * delay (selected with the "nodelay" parameter).
68*4882a593Smuzhiyun  *
69*4882a593Smuzhiyun  * I also decided to remove from the tables any timeout smaller than a
70*4882a593Smuzhiyun  * second, as it looked completly overkill...
71*4882a593Smuzhiyun  */
72*4882a593Smuzhiyun 
73*4882a593Smuzhiyun /* Timeouts in second */
74*4882a593Smuzhiyun struct max63xx_timeout {
75*4882a593Smuzhiyun 	const u8 wdset;
76*4882a593Smuzhiyun 	const u8 tdelay;
77*4882a593Smuzhiyun 	const u8 twd;
78*4882a593Smuzhiyun };
79*4882a593Smuzhiyun 
80*4882a593Smuzhiyun static const struct max63xx_timeout max6369_table[] = {
81*4882a593Smuzhiyun 	{ 5,  1,  1 },
82*4882a593Smuzhiyun 	{ 6, 10, 10 },
83*4882a593Smuzhiyun 	{ 7, 60, 60 },
84*4882a593Smuzhiyun 	{ },
85*4882a593Smuzhiyun };
86*4882a593Smuzhiyun 
87*4882a593Smuzhiyun static const struct max63xx_timeout max6371_table[] = {
88*4882a593Smuzhiyun 	{ 6, 60,  3 },
89*4882a593Smuzhiyun 	{ 7, 60, 60 },
90*4882a593Smuzhiyun 	{ },
91*4882a593Smuzhiyun };
92*4882a593Smuzhiyun 
93*4882a593Smuzhiyun static const struct max63xx_timeout max6373_table[] = {
94*4882a593Smuzhiyun 	{ 2, 60,  1 },
95*4882a593Smuzhiyun 	{ 5,  0,  1 },
96*4882a593Smuzhiyun 	{ 1,  3,  3 },
97*4882a593Smuzhiyun 	{ 7, 60, 10 },
98*4882a593Smuzhiyun 	{ 6,  0, 10 },
99*4882a593Smuzhiyun 	{ },
100*4882a593Smuzhiyun };
101*4882a593Smuzhiyun 
102*4882a593Smuzhiyun static struct max63xx_timeout *
max63xx_select_timeout(struct max63xx_timeout * table,int value)103*4882a593Smuzhiyun max63xx_select_timeout(struct max63xx_timeout *table, int value)
104*4882a593Smuzhiyun {
105*4882a593Smuzhiyun 	while (table->twd) {
106*4882a593Smuzhiyun 		if (value <= table->twd) {
107*4882a593Smuzhiyun 			if (nodelay && table->tdelay == 0)
108*4882a593Smuzhiyun 				return table;
109*4882a593Smuzhiyun 
110*4882a593Smuzhiyun 			if (!nodelay)
111*4882a593Smuzhiyun 				return table;
112*4882a593Smuzhiyun 		}
113*4882a593Smuzhiyun 
114*4882a593Smuzhiyun 		table++;
115*4882a593Smuzhiyun 	}
116*4882a593Smuzhiyun 
117*4882a593Smuzhiyun 	return NULL;
118*4882a593Smuzhiyun }
119*4882a593Smuzhiyun 
max63xx_wdt_ping(struct watchdog_device * wdd)120*4882a593Smuzhiyun static int max63xx_wdt_ping(struct watchdog_device *wdd)
121*4882a593Smuzhiyun {
122*4882a593Smuzhiyun 	struct max63xx_wdt *wdt = watchdog_get_drvdata(wdd);
123*4882a593Smuzhiyun 
124*4882a593Smuzhiyun 	wdt->ping(wdt);
125*4882a593Smuzhiyun 	return 0;
126*4882a593Smuzhiyun }
127*4882a593Smuzhiyun 
max63xx_wdt_start(struct watchdog_device * wdd)128*4882a593Smuzhiyun static int max63xx_wdt_start(struct watchdog_device *wdd)
129*4882a593Smuzhiyun {
130*4882a593Smuzhiyun 	struct max63xx_wdt *wdt = watchdog_get_drvdata(wdd);
131*4882a593Smuzhiyun 
132*4882a593Smuzhiyun 	wdt->set(wdt, wdt->timeout->wdset);
133*4882a593Smuzhiyun 
134*4882a593Smuzhiyun 	/* check for a edge triggered startup */
135*4882a593Smuzhiyun 	if (wdt->timeout->tdelay == 0)
136*4882a593Smuzhiyun 		wdt->ping(wdt);
137*4882a593Smuzhiyun 	return 0;
138*4882a593Smuzhiyun }
139*4882a593Smuzhiyun 
max63xx_wdt_stop(struct watchdog_device * wdd)140*4882a593Smuzhiyun static int max63xx_wdt_stop(struct watchdog_device *wdd)
141*4882a593Smuzhiyun {
142*4882a593Smuzhiyun 	struct max63xx_wdt *wdt = watchdog_get_drvdata(wdd);
143*4882a593Smuzhiyun 
144*4882a593Smuzhiyun 	wdt->set(wdt, MAX6369_WDSET_DISABLED);
145*4882a593Smuzhiyun 	return 0;
146*4882a593Smuzhiyun }
147*4882a593Smuzhiyun 
148*4882a593Smuzhiyun static const struct watchdog_ops max63xx_wdt_ops = {
149*4882a593Smuzhiyun 	.owner = THIS_MODULE,
150*4882a593Smuzhiyun 	.start = max63xx_wdt_start,
151*4882a593Smuzhiyun 	.stop = max63xx_wdt_stop,
152*4882a593Smuzhiyun 	.ping = max63xx_wdt_ping,
153*4882a593Smuzhiyun };
154*4882a593Smuzhiyun 
155*4882a593Smuzhiyun static const struct watchdog_info max63xx_wdt_info = {
156*4882a593Smuzhiyun 	.options = WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE,
157*4882a593Smuzhiyun 	.identity = "max63xx Watchdog",
158*4882a593Smuzhiyun };
159*4882a593Smuzhiyun 
max63xx_mmap_ping(struct max63xx_wdt * wdt)160*4882a593Smuzhiyun static void max63xx_mmap_ping(struct max63xx_wdt *wdt)
161*4882a593Smuzhiyun {
162*4882a593Smuzhiyun 	u8 val;
163*4882a593Smuzhiyun 
164*4882a593Smuzhiyun 	spin_lock(&wdt->lock);
165*4882a593Smuzhiyun 
166*4882a593Smuzhiyun 	val = __raw_readb(wdt->base);
167*4882a593Smuzhiyun 
168*4882a593Smuzhiyun 	__raw_writeb(val | MAX6369_WDI, wdt->base);
169*4882a593Smuzhiyun 	__raw_writeb(val & ~MAX6369_WDI, wdt->base);
170*4882a593Smuzhiyun 
171*4882a593Smuzhiyun 	spin_unlock(&wdt->lock);
172*4882a593Smuzhiyun }
173*4882a593Smuzhiyun 
max63xx_mmap_set(struct max63xx_wdt * wdt,u8 set)174*4882a593Smuzhiyun static void max63xx_mmap_set(struct max63xx_wdt *wdt, u8 set)
175*4882a593Smuzhiyun {
176*4882a593Smuzhiyun 	u8 val;
177*4882a593Smuzhiyun 
178*4882a593Smuzhiyun 	spin_lock(&wdt->lock);
179*4882a593Smuzhiyun 
180*4882a593Smuzhiyun 	val = __raw_readb(wdt->base);
181*4882a593Smuzhiyun 	val &= ~MAX6369_WDSET;
182*4882a593Smuzhiyun 	val |= set & MAX6369_WDSET;
183*4882a593Smuzhiyun 	__raw_writeb(val, wdt->base);
184*4882a593Smuzhiyun 
185*4882a593Smuzhiyun 	spin_unlock(&wdt->lock);
186*4882a593Smuzhiyun }
187*4882a593Smuzhiyun 
max63xx_mmap_init(struct platform_device * p,struct max63xx_wdt * wdt)188*4882a593Smuzhiyun static int max63xx_mmap_init(struct platform_device *p, struct max63xx_wdt *wdt)
189*4882a593Smuzhiyun {
190*4882a593Smuzhiyun 	wdt->base = devm_platform_ioremap_resource(p, 0);
191*4882a593Smuzhiyun 	if (IS_ERR(wdt->base))
192*4882a593Smuzhiyun 		return PTR_ERR(wdt->base);
193*4882a593Smuzhiyun 
194*4882a593Smuzhiyun 	spin_lock_init(&wdt->lock);
195*4882a593Smuzhiyun 
196*4882a593Smuzhiyun 	wdt->ping = max63xx_mmap_ping;
197*4882a593Smuzhiyun 	wdt->set = max63xx_mmap_set;
198*4882a593Smuzhiyun 	return 0;
199*4882a593Smuzhiyun }
200*4882a593Smuzhiyun 
max63xx_wdt_probe(struct platform_device * pdev)201*4882a593Smuzhiyun static int max63xx_wdt_probe(struct platform_device *pdev)
202*4882a593Smuzhiyun {
203*4882a593Smuzhiyun 	struct device *dev = &pdev->dev;
204*4882a593Smuzhiyun 	struct max63xx_wdt *wdt;
205*4882a593Smuzhiyun 	struct max63xx_timeout *table;
206*4882a593Smuzhiyun 	int err;
207*4882a593Smuzhiyun 
208*4882a593Smuzhiyun 	wdt = devm_kzalloc(dev, sizeof(*wdt), GFP_KERNEL);
209*4882a593Smuzhiyun 	if (!wdt)
210*4882a593Smuzhiyun 		return -ENOMEM;
211*4882a593Smuzhiyun 
212*4882a593Smuzhiyun 	table = (struct max63xx_timeout *)pdev->id_entry->driver_data;
213*4882a593Smuzhiyun 
214*4882a593Smuzhiyun 	if (heartbeat < 1 || heartbeat > MAX_HEARTBEAT)
215*4882a593Smuzhiyun 		heartbeat = DEFAULT_HEARTBEAT;
216*4882a593Smuzhiyun 
217*4882a593Smuzhiyun 	wdt->timeout = max63xx_select_timeout(table, heartbeat);
218*4882a593Smuzhiyun 	if (!wdt->timeout) {
219*4882a593Smuzhiyun 		dev_err(dev, "unable to satisfy %ds heartbeat request\n",
220*4882a593Smuzhiyun 			heartbeat);
221*4882a593Smuzhiyun 		return -EINVAL;
222*4882a593Smuzhiyun 	}
223*4882a593Smuzhiyun 
224*4882a593Smuzhiyun 	err = max63xx_mmap_init(pdev, wdt);
225*4882a593Smuzhiyun 	if (err)
226*4882a593Smuzhiyun 		return err;
227*4882a593Smuzhiyun 
228*4882a593Smuzhiyun 	platform_set_drvdata(pdev, &wdt->wdd);
229*4882a593Smuzhiyun 	watchdog_set_drvdata(&wdt->wdd, wdt);
230*4882a593Smuzhiyun 
231*4882a593Smuzhiyun 	wdt->wdd.parent = dev;
232*4882a593Smuzhiyun 	wdt->wdd.timeout = wdt->timeout->twd;
233*4882a593Smuzhiyun 	wdt->wdd.info = &max63xx_wdt_info;
234*4882a593Smuzhiyun 	wdt->wdd.ops = &max63xx_wdt_ops;
235*4882a593Smuzhiyun 
236*4882a593Smuzhiyun 	watchdog_set_nowayout(&wdt->wdd, nowayout);
237*4882a593Smuzhiyun 
238*4882a593Smuzhiyun 	err = devm_watchdog_register_device(dev, &wdt->wdd);
239*4882a593Smuzhiyun 	if (err)
240*4882a593Smuzhiyun 		return err;
241*4882a593Smuzhiyun 
242*4882a593Smuzhiyun 	dev_info(dev, "using %ds heartbeat with %ds initial delay\n",
243*4882a593Smuzhiyun 		 wdt->timeout->twd, wdt->timeout->tdelay);
244*4882a593Smuzhiyun 	return 0;
245*4882a593Smuzhiyun }
246*4882a593Smuzhiyun 
247*4882a593Smuzhiyun static const struct platform_device_id max63xx_id_table[] = {
248*4882a593Smuzhiyun 	{ "max6369_wdt", (kernel_ulong_t)max6369_table, },
249*4882a593Smuzhiyun 	{ "max6370_wdt", (kernel_ulong_t)max6369_table, },
250*4882a593Smuzhiyun 	{ "max6371_wdt", (kernel_ulong_t)max6371_table, },
251*4882a593Smuzhiyun 	{ "max6372_wdt", (kernel_ulong_t)max6371_table, },
252*4882a593Smuzhiyun 	{ "max6373_wdt", (kernel_ulong_t)max6373_table, },
253*4882a593Smuzhiyun 	{ "max6374_wdt", (kernel_ulong_t)max6373_table, },
254*4882a593Smuzhiyun 	{ },
255*4882a593Smuzhiyun };
256*4882a593Smuzhiyun MODULE_DEVICE_TABLE(platform, max63xx_id_table);
257*4882a593Smuzhiyun 
258*4882a593Smuzhiyun static struct platform_driver max63xx_wdt_driver = {
259*4882a593Smuzhiyun 	.probe		= max63xx_wdt_probe,
260*4882a593Smuzhiyun 	.id_table	= max63xx_id_table,
261*4882a593Smuzhiyun 	.driver		= {
262*4882a593Smuzhiyun 		.name	= "max63xx_wdt",
263*4882a593Smuzhiyun 	},
264*4882a593Smuzhiyun };
265*4882a593Smuzhiyun 
266*4882a593Smuzhiyun module_platform_driver(max63xx_wdt_driver);
267*4882a593Smuzhiyun 
268*4882a593Smuzhiyun MODULE_AUTHOR("Marc Zyngier <maz@misterjones.org>");
269*4882a593Smuzhiyun MODULE_DESCRIPTION("max63xx Watchdog Driver");
270*4882a593Smuzhiyun 
271*4882a593Smuzhiyun module_param(heartbeat, int, 0);
272*4882a593Smuzhiyun MODULE_PARM_DESC(heartbeat,
273*4882a593Smuzhiyun 		 "Watchdog heartbeat period in seconds from 1 to "
274*4882a593Smuzhiyun 		 __MODULE_STRING(MAX_HEARTBEAT) ", default "
275*4882a593Smuzhiyun 		 __MODULE_STRING(DEFAULT_HEARTBEAT));
276*4882a593Smuzhiyun 
277*4882a593Smuzhiyun module_param(nowayout, bool, 0);
278*4882a593Smuzhiyun MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
279*4882a593Smuzhiyun 		 __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
280*4882a593Smuzhiyun 
281*4882a593Smuzhiyun module_param(nodelay, int, 0);
282*4882a593Smuzhiyun MODULE_PARM_DESC(nodelay,
283*4882a593Smuzhiyun 		 "Force selection of a timeout setting without initial delay "
284*4882a593Smuzhiyun 		 "(max6373/74 only, default=0)");
285*4882a593Smuzhiyun 
286*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
287