1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Intel_SCU 0.2: An Intel SCU IOH Based Watchdog Device 4*4882a593Smuzhiyun * for Intel part #(s): 5*4882a593Smuzhiyun * - AF82MP20 PCH 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * Copyright (C) 2009-2010 Intel Corporation. All rights reserved. 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #ifndef __INTEL_SCU_WATCHDOG_H 11*4882a593Smuzhiyun #define __INTEL_SCU_WATCHDOG_H 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #define WDT_VER "0.3" 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun /* minimum time between interrupts */ 16*4882a593Smuzhiyun #define MIN_TIME_CYCLE 1 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun /* Time from warning to reboot is 2 seconds */ 19*4882a593Smuzhiyun #define DEFAULT_SOFT_TO_HARD_MARGIN 2 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun #define MAX_TIME 170 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun #define DEFAULT_TIME 5 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun #define MAX_SOFT_TO_HARD_MARGIN (MAX_TIME-MIN_TIME_CYCLE) 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun /* Ajustment to clock tick frequency to make timing come out right */ 28*4882a593Smuzhiyun #define FREQ_ADJUSTMENT 8 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun struct intel_scu_watchdog_dev { 31*4882a593Smuzhiyun ulong driver_open; 32*4882a593Smuzhiyun ulong driver_closed; 33*4882a593Smuzhiyun u32 timer_started; 34*4882a593Smuzhiyun u32 timer_set; 35*4882a593Smuzhiyun u32 threshold; 36*4882a593Smuzhiyun u32 soft_threshold; 37*4882a593Smuzhiyun u32 __iomem *timer_load_count_addr; 38*4882a593Smuzhiyun u32 __iomem *timer_current_value_addr; 39*4882a593Smuzhiyun u32 __iomem *timer_control_addr; 40*4882a593Smuzhiyun u32 __iomem *timer_clear_interrupt_addr; 41*4882a593Smuzhiyun u32 __iomem *timer_interrupt_status_addr; 42*4882a593Smuzhiyun struct sfi_timer_table_entry *timer_tbl_ptr; 43*4882a593Smuzhiyun struct notifier_block intel_scu_notifier; 44*4882a593Smuzhiyun struct miscdevice miscdev; 45*4882a593Smuzhiyun }; 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun extern int sfi_mtimer_num; 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun /* extern struct sfi_timer_table_entry *sfi_get_mtmr(int hint); */ 50*4882a593Smuzhiyun #endif /* __INTEL_SCU_WATCHDOG_H */ 51