1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Intel_SCU 0.2: An Intel SCU IOH Based Watchdog Device
4*4882a593Smuzhiyun * for Intel part #(s):
5*4882a593Smuzhiyun * - AF82MP20 PCH
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Copyright (C) 2009-2010 Intel Corporation. All rights reserved.
8*4882a593Smuzhiyun */
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun #include <linux/compiler.h>
13*4882a593Smuzhiyun #include <linux/kernel.h>
14*4882a593Smuzhiyun #include <linux/moduleparam.h>
15*4882a593Smuzhiyun #include <linux/types.h>
16*4882a593Smuzhiyun #include <linux/miscdevice.h>
17*4882a593Smuzhiyun #include <linux/watchdog.h>
18*4882a593Smuzhiyun #include <linux/fs.h>
19*4882a593Smuzhiyun #include <linux/notifier.h>
20*4882a593Smuzhiyun #include <linux/reboot.h>
21*4882a593Smuzhiyun #include <linux/init.h>
22*4882a593Smuzhiyun #include <linux/jiffies.h>
23*4882a593Smuzhiyun #include <linux/uaccess.h>
24*4882a593Smuzhiyun #include <linux/slab.h>
25*4882a593Smuzhiyun #include <linux/io.h>
26*4882a593Smuzhiyun #include <linux/interrupt.h>
27*4882a593Smuzhiyun #include <linux/delay.h>
28*4882a593Smuzhiyun #include <linux/sched.h>
29*4882a593Smuzhiyun #include <linux/signal.h>
30*4882a593Smuzhiyun #include <linux/sfi.h>
31*4882a593Smuzhiyun #include <asm/irq.h>
32*4882a593Smuzhiyun #include <linux/atomic.h>
33*4882a593Smuzhiyun #include <asm/intel_scu_ipc.h>
34*4882a593Smuzhiyun #include <asm/apb_timer.h>
35*4882a593Smuzhiyun #include <asm/intel-mid.h>
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun #include "intel_scu_watchdog.h"
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun /* Bounds number of times we will retry loading time count */
40*4882a593Smuzhiyun /* This retry is a work around for a silicon bug. */
41*4882a593Smuzhiyun #define MAX_RETRY 16
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun #define IPC_SET_WATCHDOG_TIMER 0xF8
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun static int timer_margin = DEFAULT_SOFT_TO_HARD_MARGIN;
46*4882a593Smuzhiyun module_param(timer_margin, int, 0);
47*4882a593Smuzhiyun MODULE_PARM_DESC(timer_margin,
48*4882a593Smuzhiyun "Watchdog timer margin"
49*4882a593Smuzhiyun "Time between interrupt and resetting the system"
50*4882a593Smuzhiyun "The range is from 1 to 160"
51*4882a593Smuzhiyun "This is the time for all keep alives to arrive");
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun static int timer_set = DEFAULT_TIME;
54*4882a593Smuzhiyun module_param(timer_set, int, 0);
55*4882a593Smuzhiyun MODULE_PARM_DESC(timer_set,
56*4882a593Smuzhiyun "Default Watchdog timer setting"
57*4882a593Smuzhiyun "Complete cycle time"
58*4882a593Smuzhiyun "The range is from 1 to 170"
59*4882a593Smuzhiyun "This is the time for all keep alives to arrive");
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun /* After watchdog device is closed, check force_boot. If:
62*4882a593Smuzhiyun * force_boot == 0, then force boot on next watchdog interrupt after close,
63*4882a593Smuzhiyun * force_boot == 1, then force boot immediately when device is closed.
64*4882a593Smuzhiyun */
65*4882a593Smuzhiyun static int force_boot;
66*4882a593Smuzhiyun module_param(force_boot, int, 0);
67*4882a593Smuzhiyun MODULE_PARM_DESC(force_boot,
68*4882a593Smuzhiyun "A value of 1 means that the driver will reboot"
69*4882a593Smuzhiyun "the system immediately if the /dev/watchdog device is closed"
70*4882a593Smuzhiyun "A value of 0 means that when /dev/watchdog device is closed"
71*4882a593Smuzhiyun "the watchdog timer will be refreshed for one more interval"
72*4882a593Smuzhiyun "of length: timer_set. At the end of this interval, the"
73*4882a593Smuzhiyun "watchdog timer will reset the system."
74*4882a593Smuzhiyun );
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun /* there is only one device in the system now; this can be made into
77*4882a593Smuzhiyun * an array in the future if we have more than one device */
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun static struct intel_scu_watchdog_dev watchdog_device;
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun /* Forces restart, if force_reboot is set */
watchdog_fire(void)82*4882a593Smuzhiyun static void watchdog_fire(void)
83*4882a593Smuzhiyun {
84*4882a593Smuzhiyun if (force_boot) {
85*4882a593Smuzhiyun pr_crit("Initiating system reboot\n");
86*4882a593Smuzhiyun emergency_restart();
87*4882a593Smuzhiyun pr_crit("Reboot didn't ?????\n");
88*4882a593Smuzhiyun }
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun else {
91*4882a593Smuzhiyun pr_crit("Immediate Reboot Disabled\n");
92*4882a593Smuzhiyun pr_crit("System will reset when watchdog timer times out!\n");
93*4882a593Smuzhiyun }
94*4882a593Smuzhiyun }
95*4882a593Smuzhiyun
check_timer_margin(int new_margin)96*4882a593Smuzhiyun static int check_timer_margin(int new_margin)
97*4882a593Smuzhiyun {
98*4882a593Smuzhiyun if ((new_margin < MIN_TIME_CYCLE) ||
99*4882a593Smuzhiyun (new_margin > MAX_TIME - timer_set)) {
100*4882a593Smuzhiyun pr_debug("value of new_margin %d is out of the range %d to %d\n",
101*4882a593Smuzhiyun new_margin, MIN_TIME_CYCLE, MAX_TIME - timer_set);
102*4882a593Smuzhiyun return -EINVAL;
103*4882a593Smuzhiyun }
104*4882a593Smuzhiyun return 0;
105*4882a593Smuzhiyun }
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun /*
108*4882a593Smuzhiyun * IPC operations
109*4882a593Smuzhiyun */
watchdog_set_ipc(int soft_threshold,int threshold)110*4882a593Smuzhiyun static int watchdog_set_ipc(int soft_threshold, int threshold)
111*4882a593Smuzhiyun {
112*4882a593Smuzhiyun u32 *ipc_wbuf;
113*4882a593Smuzhiyun u8 cbuf[16] = { '\0' };
114*4882a593Smuzhiyun int ipc_ret = 0;
115*4882a593Smuzhiyun
116*4882a593Smuzhiyun ipc_wbuf = (u32 *)&cbuf;
117*4882a593Smuzhiyun ipc_wbuf[0] = soft_threshold;
118*4882a593Smuzhiyun ipc_wbuf[1] = threshold;
119*4882a593Smuzhiyun
120*4882a593Smuzhiyun ipc_ret = intel_scu_ipc_command(
121*4882a593Smuzhiyun IPC_SET_WATCHDOG_TIMER,
122*4882a593Smuzhiyun 0,
123*4882a593Smuzhiyun ipc_wbuf,
124*4882a593Smuzhiyun 2,
125*4882a593Smuzhiyun NULL,
126*4882a593Smuzhiyun 0);
127*4882a593Smuzhiyun
128*4882a593Smuzhiyun if (ipc_ret != 0)
129*4882a593Smuzhiyun pr_err("Error setting SCU watchdog timer: %x\n", ipc_ret);
130*4882a593Smuzhiyun
131*4882a593Smuzhiyun return ipc_ret;
132*4882a593Smuzhiyun };
133*4882a593Smuzhiyun
134*4882a593Smuzhiyun /*
135*4882a593Smuzhiyun * Intel_SCU operations
136*4882a593Smuzhiyun */
137*4882a593Smuzhiyun
138*4882a593Smuzhiyun /* timer interrupt handler */
watchdog_timer_interrupt(int irq,void * dev_id)139*4882a593Smuzhiyun static irqreturn_t watchdog_timer_interrupt(int irq, void *dev_id)
140*4882a593Smuzhiyun {
141*4882a593Smuzhiyun int int_status;
142*4882a593Smuzhiyun int_status = ioread32(watchdog_device.timer_interrupt_status_addr);
143*4882a593Smuzhiyun
144*4882a593Smuzhiyun pr_debug("irq, int_status: %x\n", int_status);
145*4882a593Smuzhiyun
146*4882a593Smuzhiyun if (int_status != 0)
147*4882a593Smuzhiyun return IRQ_NONE;
148*4882a593Smuzhiyun
149*4882a593Smuzhiyun /* has the timer been started? If not, then this is spurious */
150*4882a593Smuzhiyun if (watchdog_device.timer_started == 0) {
151*4882a593Smuzhiyun pr_debug("spurious interrupt received\n");
152*4882a593Smuzhiyun return IRQ_HANDLED;
153*4882a593Smuzhiyun }
154*4882a593Smuzhiyun
155*4882a593Smuzhiyun /* temporarily disable the timer */
156*4882a593Smuzhiyun iowrite32(0x00000002, watchdog_device.timer_control_addr);
157*4882a593Smuzhiyun
158*4882a593Smuzhiyun /* set the timer to the threshold */
159*4882a593Smuzhiyun iowrite32(watchdog_device.threshold,
160*4882a593Smuzhiyun watchdog_device.timer_load_count_addr);
161*4882a593Smuzhiyun
162*4882a593Smuzhiyun /* allow the timer to run */
163*4882a593Smuzhiyun iowrite32(0x00000003, watchdog_device.timer_control_addr);
164*4882a593Smuzhiyun
165*4882a593Smuzhiyun return IRQ_HANDLED;
166*4882a593Smuzhiyun }
167*4882a593Smuzhiyun
intel_scu_keepalive(void)168*4882a593Smuzhiyun static int intel_scu_keepalive(void)
169*4882a593Smuzhiyun {
170*4882a593Smuzhiyun
171*4882a593Smuzhiyun /* read eoi register - clears interrupt */
172*4882a593Smuzhiyun ioread32(watchdog_device.timer_clear_interrupt_addr);
173*4882a593Smuzhiyun
174*4882a593Smuzhiyun /* temporarily disable the timer */
175*4882a593Smuzhiyun iowrite32(0x00000002, watchdog_device.timer_control_addr);
176*4882a593Smuzhiyun
177*4882a593Smuzhiyun /* set the timer to the soft_threshold */
178*4882a593Smuzhiyun iowrite32(watchdog_device.soft_threshold,
179*4882a593Smuzhiyun watchdog_device.timer_load_count_addr);
180*4882a593Smuzhiyun
181*4882a593Smuzhiyun /* allow the timer to run */
182*4882a593Smuzhiyun iowrite32(0x00000003, watchdog_device.timer_control_addr);
183*4882a593Smuzhiyun
184*4882a593Smuzhiyun return 0;
185*4882a593Smuzhiyun }
186*4882a593Smuzhiyun
intel_scu_stop(void)187*4882a593Smuzhiyun static int intel_scu_stop(void)
188*4882a593Smuzhiyun {
189*4882a593Smuzhiyun iowrite32(0, watchdog_device.timer_control_addr);
190*4882a593Smuzhiyun return 0;
191*4882a593Smuzhiyun }
192*4882a593Smuzhiyun
intel_scu_set_heartbeat(u32 t)193*4882a593Smuzhiyun static int intel_scu_set_heartbeat(u32 t)
194*4882a593Smuzhiyun {
195*4882a593Smuzhiyun int ipc_ret;
196*4882a593Smuzhiyun int retry_count;
197*4882a593Smuzhiyun u32 soft_value;
198*4882a593Smuzhiyun u32 hw_value;
199*4882a593Smuzhiyun
200*4882a593Smuzhiyun watchdog_device.timer_set = t;
201*4882a593Smuzhiyun watchdog_device.threshold =
202*4882a593Smuzhiyun timer_margin * watchdog_device.timer_tbl_ptr->freq_hz;
203*4882a593Smuzhiyun watchdog_device.soft_threshold =
204*4882a593Smuzhiyun (watchdog_device.timer_set - timer_margin)
205*4882a593Smuzhiyun * watchdog_device.timer_tbl_ptr->freq_hz;
206*4882a593Smuzhiyun
207*4882a593Smuzhiyun pr_debug("set_heartbeat: timer freq is %d\n",
208*4882a593Smuzhiyun watchdog_device.timer_tbl_ptr->freq_hz);
209*4882a593Smuzhiyun pr_debug("set_heartbeat: timer_set is %x (hex)\n",
210*4882a593Smuzhiyun watchdog_device.timer_set);
211*4882a593Smuzhiyun pr_debug("set_heartbeat: timer_margin is %x (hex)\n", timer_margin);
212*4882a593Smuzhiyun pr_debug("set_heartbeat: threshold is %x (hex)\n",
213*4882a593Smuzhiyun watchdog_device.threshold);
214*4882a593Smuzhiyun pr_debug("set_heartbeat: soft_threshold is %x (hex)\n",
215*4882a593Smuzhiyun watchdog_device.soft_threshold);
216*4882a593Smuzhiyun
217*4882a593Smuzhiyun /* Adjust thresholds by FREQ_ADJUSTMENT factor, to make the */
218*4882a593Smuzhiyun /* watchdog timing come out right. */
219*4882a593Smuzhiyun watchdog_device.threshold =
220*4882a593Smuzhiyun watchdog_device.threshold / FREQ_ADJUSTMENT;
221*4882a593Smuzhiyun watchdog_device.soft_threshold =
222*4882a593Smuzhiyun watchdog_device.soft_threshold / FREQ_ADJUSTMENT;
223*4882a593Smuzhiyun
224*4882a593Smuzhiyun /* temporarily disable the timer */
225*4882a593Smuzhiyun iowrite32(0x00000002, watchdog_device.timer_control_addr);
226*4882a593Smuzhiyun
227*4882a593Smuzhiyun /* send the threshold and soft_threshold via IPC to the processor */
228*4882a593Smuzhiyun ipc_ret = watchdog_set_ipc(watchdog_device.soft_threshold,
229*4882a593Smuzhiyun watchdog_device.threshold);
230*4882a593Smuzhiyun
231*4882a593Smuzhiyun if (ipc_ret != 0) {
232*4882a593Smuzhiyun /* Make sure the watchdog timer is stopped */
233*4882a593Smuzhiyun intel_scu_stop();
234*4882a593Smuzhiyun return ipc_ret;
235*4882a593Smuzhiyun }
236*4882a593Smuzhiyun
237*4882a593Smuzhiyun /* Soft Threshold set loop. Early versions of silicon did */
238*4882a593Smuzhiyun /* not always set this count correctly. This loop checks */
239*4882a593Smuzhiyun /* the value and retries if it was not set correctly. */
240*4882a593Smuzhiyun
241*4882a593Smuzhiyun retry_count = 0;
242*4882a593Smuzhiyun soft_value = watchdog_device.soft_threshold & 0xFFFF0000;
243*4882a593Smuzhiyun do {
244*4882a593Smuzhiyun
245*4882a593Smuzhiyun /* Make sure timer is stopped */
246*4882a593Smuzhiyun intel_scu_stop();
247*4882a593Smuzhiyun
248*4882a593Smuzhiyun if (MAX_RETRY < retry_count++) {
249*4882a593Smuzhiyun /* Unable to set timer value */
250*4882a593Smuzhiyun pr_err("Unable to set timer\n");
251*4882a593Smuzhiyun return -ENODEV;
252*4882a593Smuzhiyun }
253*4882a593Smuzhiyun
254*4882a593Smuzhiyun /* set the timer to the soft threshold */
255*4882a593Smuzhiyun iowrite32(watchdog_device.soft_threshold,
256*4882a593Smuzhiyun watchdog_device.timer_load_count_addr);
257*4882a593Smuzhiyun
258*4882a593Smuzhiyun /* read count value before starting timer */
259*4882a593Smuzhiyun ioread32(watchdog_device.timer_load_count_addr);
260*4882a593Smuzhiyun
261*4882a593Smuzhiyun /* Start the timer */
262*4882a593Smuzhiyun iowrite32(0x00000003, watchdog_device.timer_control_addr);
263*4882a593Smuzhiyun
264*4882a593Smuzhiyun /* read the value the time loaded into its count reg */
265*4882a593Smuzhiyun hw_value = ioread32(watchdog_device.timer_load_count_addr);
266*4882a593Smuzhiyun hw_value = hw_value & 0xFFFF0000;
267*4882a593Smuzhiyun
268*4882a593Smuzhiyun
269*4882a593Smuzhiyun } while (soft_value != hw_value);
270*4882a593Smuzhiyun
271*4882a593Smuzhiyun watchdog_device.timer_started = 1;
272*4882a593Smuzhiyun
273*4882a593Smuzhiyun return 0;
274*4882a593Smuzhiyun }
275*4882a593Smuzhiyun
276*4882a593Smuzhiyun /*
277*4882a593Smuzhiyun * /dev/watchdog handling
278*4882a593Smuzhiyun */
279*4882a593Smuzhiyun
intel_scu_open(struct inode * inode,struct file * file)280*4882a593Smuzhiyun static int intel_scu_open(struct inode *inode, struct file *file)
281*4882a593Smuzhiyun {
282*4882a593Smuzhiyun
283*4882a593Smuzhiyun /* Set flag to indicate that watchdog device is open */
284*4882a593Smuzhiyun if (test_and_set_bit(0, &watchdog_device.driver_open))
285*4882a593Smuzhiyun return -EBUSY;
286*4882a593Smuzhiyun
287*4882a593Smuzhiyun /* Check for reopen of driver. Reopens are not allowed */
288*4882a593Smuzhiyun if (watchdog_device.driver_closed)
289*4882a593Smuzhiyun return -EPERM;
290*4882a593Smuzhiyun
291*4882a593Smuzhiyun return stream_open(inode, file);
292*4882a593Smuzhiyun }
293*4882a593Smuzhiyun
intel_scu_release(struct inode * inode,struct file * file)294*4882a593Smuzhiyun static int intel_scu_release(struct inode *inode, struct file *file)
295*4882a593Smuzhiyun {
296*4882a593Smuzhiyun /*
297*4882a593Smuzhiyun * This watchdog should not be closed, after the timer
298*4882a593Smuzhiyun * is started with the WDIPC_SETTIMEOUT ioctl
299*4882a593Smuzhiyun * If force_boot is set watchdog_fire() will cause an
300*4882a593Smuzhiyun * immediate reset. If force_boot is not set, the watchdog
301*4882a593Smuzhiyun * timer is refreshed for one more interval. At the end
302*4882a593Smuzhiyun * of that interval, the watchdog timer will reset the system.
303*4882a593Smuzhiyun */
304*4882a593Smuzhiyun
305*4882a593Smuzhiyun if (!test_and_clear_bit(0, &watchdog_device.driver_open)) {
306*4882a593Smuzhiyun pr_debug("intel_scu_release, without open\n");
307*4882a593Smuzhiyun return -ENOTTY;
308*4882a593Smuzhiyun }
309*4882a593Smuzhiyun
310*4882a593Smuzhiyun if (!watchdog_device.timer_started) {
311*4882a593Smuzhiyun /* Just close, since timer has not been started */
312*4882a593Smuzhiyun pr_debug("closed, without starting timer\n");
313*4882a593Smuzhiyun return 0;
314*4882a593Smuzhiyun }
315*4882a593Smuzhiyun
316*4882a593Smuzhiyun pr_crit("Unexpected close of /dev/watchdog!\n");
317*4882a593Smuzhiyun
318*4882a593Smuzhiyun /* Since the timer was started, prevent future reopens */
319*4882a593Smuzhiyun watchdog_device.driver_closed = 1;
320*4882a593Smuzhiyun
321*4882a593Smuzhiyun /* Refresh the timer for one more interval */
322*4882a593Smuzhiyun intel_scu_keepalive();
323*4882a593Smuzhiyun
324*4882a593Smuzhiyun /* Reboot system (if force_boot is set) */
325*4882a593Smuzhiyun watchdog_fire();
326*4882a593Smuzhiyun
327*4882a593Smuzhiyun /* We should only reach this point if force_boot is not set */
328*4882a593Smuzhiyun return 0;
329*4882a593Smuzhiyun }
330*4882a593Smuzhiyun
intel_scu_write(struct file * file,char const * data,size_t len,loff_t * ppos)331*4882a593Smuzhiyun static ssize_t intel_scu_write(struct file *file,
332*4882a593Smuzhiyun char const *data,
333*4882a593Smuzhiyun size_t len,
334*4882a593Smuzhiyun loff_t *ppos)
335*4882a593Smuzhiyun {
336*4882a593Smuzhiyun
337*4882a593Smuzhiyun if (watchdog_device.timer_started)
338*4882a593Smuzhiyun /* Watchdog already started, keep it alive */
339*4882a593Smuzhiyun intel_scu_keepalive();
340*4882a593Smuzhiyun else
341*4882a593Smuzhiyun /* Start watchdog with timer value set by init */
342*4882a593Smuzhiyun intel_scu_set_heartbeat(watchdog_device.timer_set);
343*4882a593Smuzhiyun
344*4882a593Smuzhiyun return len;
345*4882a593Smuzhiyun }
346*4882a593Smuzhiyun
intel_scu_ioctl(struct file * file,unsigned int cmd,unsigned long arg)347*4882a593Smuzhiyun static long intel_scu_ioctl(struct file *file,
348*4882a593Smuzhiyun unsigned int cmd,
349*4882a593Smuzhiyun unsigned long arg)
350*4882a593Smuzhiyun {
351*4882a593Smuzhiyun void __user *argp = (void __user *)arg;
352*4882a593Smuzhiyun u32 __user *p = argp;
353*4882a593Smuzhiyun u32 new_margin;
354*4882a593Smuzhiyun
355*4882a593Smuzhiyun
356*4882a593Smuzhiyun static const struct watchdog_info ident = {
357*4882a593Smuzhiyun .options = WDIOF_SETTIMEOUT
358*4882a593Smuzhiyun | WDIOF_KEEPALIVEPING,
359*4882a593Smuzhiyun .firmware_version = 0, /* @todo Get from SCU via
360*4882a593Smuzhiyun ipc_get_scu_fw_version()? */
361*4882a593Smuzhiyun .identity = "Intel_SCU IOH Watchdog" /* len < 32 */
362*4882a593Smuzhiyun };
363*4882a593Smuzhiyun
364*4882a593Smuzhiyun switch (cmd) {
365*4882a593Smuzhiyun case WDIOC_GETSUPPORT:
366*4882a593Smuzhiyun return copy_to_user(argp,
367*4882a593Smuzhiyun &ident,
368*4882a593Smuzhiyun sizeof(ident)) ? -EFAULT : 0;
369*4882a593Smuzhiyun case WDIOC_GETSTATUS:
370*4882a593Smuzhiyun case WDIOC_GETBOOTSTATUS:
371*4882a593Smuzhiyun return put_user(0, p);
372*4882a593Smuzhiyun case WDIOC_KEEPALIVE:
373*4882a593Smuzhiyun intel_scu_keepalive();
374*4882a593Smuzhiyun
375*4882a593Smuzhiyun return 0;
376*4882a593Smuzhiyun case WDIOC_SETTIMEOUT:
377*4882a593Smuzhiyun if (get_user(new_margin, p))
378*4882a593Smuzhiyun return -EFAULT;
379*4882a593Smuzhiyun
380*4882a593Smuzhiyun if (check_timer_margin(new_margin))
381*4882a593Smuzhiyun return -EINVAL;
382*4882a593Smuzhiyun
383*4882a593Smuzhiyun if (intel_scu_set_heartbeat(new_margin))
384*4882a593Smuzhiyun return -EINVAL;
385*4882a593Smuzhiyun return 0;
386*4882a593Smuzhiyun case WDIOC_GETTIMEOUT:
387*4882a593Smuzhiyun return put_user(watchdog_device.soft_threshold, p);
388*4882a593Smuzhiyun
389*4882a593Smuzhiyun default:
390*4882a593Smuzhiyun return -ENOTTY;
391*4882a593Smuzhiyun }
392*4882a593Smuzhiyun }
393*4882a593Smuzhiyun
394*4882a593Smuzhiyun /*
395*4882a593Smuzhiyun * Notifier for system down
396*4882a593Smuzhiyun */
intel_scu_notify_sys(struct notifier_block * this,unsigned long code,void * another_unused)397*4882a593Smuzhiyun static int intel_scu_notify_sys(struct notifier_block *this,
398*4882a593Smuzhiyun unsigned long code,
399*4882a593Smuzhiyun void *another_unused)
400*4882a593Smuzhiyun {
401*4882a593Smuzhiyun if (code == SYS_DOWN || code == SYS_HALT)
402*4882a593Smuzhiyun /* Turn off the watchdog timer. */
403*4882a593Smuzhiyun intel_scu_stop();
404*4882a593Smuzhiyun return NOTIFY_DONE;
405*4882a593Smuzhiyun }
406*4882a593Smuzhiyun
407*4882a593Smuzhiyun /*
408*4882a593Smuzhiyun * Kernel Interfaces
409*4882a593Smuzhiyun */
410*4882a593Smuzhiyun static const struct file_operations intel_scu_fops = {
411*4882a593Smuzhiyun .owner = THIS_MODULE,
412*4882a593Smuzhiyun .llseek = no_llseek,
413*4882a593Smuzhiyun .write = intel_scu_write,
414*4882a593Smuzhiyun .unlocked_ioctl = intel_scu_ioctl,
415*4882a593Smuzhiyun .compat_ioctl = compat_ptr_ioctl,
416*4882a593Smuzhiyun .open = intel_scu_open,
417*4882a593Smuzhiyun .release = intel_scu_release,
418*4882a593Smuzhiyun };
419*4882a593Smuzhiyun
intel_scu_watchdog_init(void)420*4882a593Smuzhiyun static int __init intel_scu_watchdog_init(void)
421*4882a593Smuzhiyun {
422*4882a593Smuzhiyun int ret;
423*4882a593Smuzhiyun u32 __iomem *tmp_addr;
424*4882a593Smuzhiyun
425*4882a593Smuzhiyun /*
426*4882a593Smuzhiyun * We don't really need to check this as the SFI timer get will fail
427*4882a593Smuzhiyun * but if we do so we can exit with a clearer reason and no noise.
428*4882a593Smuzhiyun *
429*4882a593Smuzhiyun * If it isn't an intel MID device then it doesn't have this watchdog
430*4882a593Smuzhiyun */
431*4882a593Smuzhiyun if (!intel_mid_identify_cpu())
432*4882a593Smuzhiyun return -ENODEV;
433*4882a593Smuzhiyun
434*4882a593Smuzhiyun /* Check boot parameters to verify that their initial values */
435*4882a593Smuzhiyun /* are in range. */
436*4882a593Smuzhiyun /* Check value of timer_set boot parameter */
437*4882a593Smuzhiyun if ((timer_set < MIN_TIME_CYCLE) ||
438*4882a593Smuzhiyun (timer_set > MAX_TIME - MIN_TIME_CYCLE)) {
439*4882a593Smuzhiyun pr_err("value of timer_set %x (hex) is out of range from %x to %x (hex)\n",
440*4882a593Smuzhiyun timer_set, MIN_TIME_CYCLE, MAX_TIME - MIN_TIME_CYCLE);
441*4882a593Smuzhiyun return -EINVAL;
442*4882a593Smuzhiyun }
443*4882a593Smuzhiyun
444*4882a593Smuzhiyun /* Check value of timer_margin boot parameter */
445*4882a593Smuzhiyun if (check_timer_margin(timer_margin))
446*4882a593Smuzhiyun return -EINVAL;
447*4882a593Smuzhiyun
448*4882a593Smuzhiyun watchdog_device.timer_tbl_ptr = sfi_get_mtmr(sfi_mtimer_num-1);
449*4882a593Smuzhiyun
450*4882a593Smuzhiyun if (watchdog_device.timer_tbl_ptr == NULL) {
451*4882a593Smuzhiyun pr_debug("timer is not available\n");
452*4882a593Smuzhiyun return -ENODEV;
453*4882a593Smuzhiyun }
454*4882a593Smuzhiyun /* make sure the timer exists */
455*4882a593Smuzhiyun if (watchdog_device.timer_tbl_ptr->phys_addr == 0) {
456*4882a593Smuzhiyun pr_debug("timer %d does not have valid physical memory\n",
457*4882a593Smuzhiyun sfi_mtimer_num);
458*4882a593Smuzhiyun return -ENODEV;
459*4882a593Smuzhiyun }
460*4882a593Smuzhiyun
461*4882a593Smuzhiyun if (watchdog_device.timer_tbl_ptr->irq == 0) {
462*4882a593Smuzhiyun pr_debug("timer %d invalid irq\n", sfi_mtimer_num);
463*4882a593Smuzhiyun return -ENODEV;
464*4882a593Smuzhiyun }
465*4882a593Smuzhiyun
466*4882a593Smuzhiyun tmp_addr = ioremap(watchdog_device.timer_tbl_ptr->phys_addr,
467*4882a593Smuzhiyun 20);
468*4882a593Smuzhiyun
469*4882a593Smuzhiyun if (tmp_addr == NULL) {
470*4882a593Smuzhiyun pr_debug("timer unable to ioremap\n");
471*4882a593Smuzhiyun return -ENOMEM;
472*4882a593Smuzhiyun }
473*4882a593Smuzhiyun
474*4882a593Smuzhiyun watchdog_device.timer_load_count_addr = tmp_addr++;
475*4882a593Smuzhiyun watchdog_device.timer_current_value_addr = tmp_addr++;
476*4882a593Smuzhiyun watchdog_device.timer_control_addr = tmp_addr++;
477*4882a593Smuzhiyun watchdog_device.timer_clear_interrupt_addr = tmp_addr++;
478*4882a593Smuzhiyun watchdog_device.timer_interrupt_status_addr = tmp_addr++;
479*4882a593Smuzhiyun
480*4882a593Smuzhiyun /* Set the default time values in device structure */
481*4882a593Smuzhiyun
482*4882a593Smuzhiyun watchdog_device.timer_set = timer_set;
483*4882a593Smuzhiyun watchdog_device.threshold =
484*4882a593Smuzhiyun timer_margin * watchdog_device.timer_tbl_ptr->freq_hz;
485*4882a593Smuzhiyun watchdog_device.soft_threshold =
486*4882a593Smuzhiyun (watchdog_device.timer_set - timer_margin)
487*4882a593Smuzhiyun * watchdog_device.timer_tbl_ptr->freq_hz;
488*4882a593Smuzhiyun
489*4882a593Smuzhiyun
490*4882a593Smuzhiyun watchdog_device.intel_scu_notifier.notifier_call =
491*4882a593Smuzhiyun intel_scu_notify_sys;
492*4882a593Smuzhiyun
493*4882a593Smuzhiyun ret = register_reboot_notifier(&watchdog_device.intel_scu_notifier);
494*4882a593Smuzhiyun if (ret) {
495*4882a593Smuzhiyun pr_err("cannot register notifier %d)\n", ret);
496*4882a593Smuzhiyun goto register_reboot_error;
497*4882a593Smuzhiyun }
498*4882a593Smuzhiyun
499*4882a593Smuzhiyun watchdog_device.miscdev.minor = WATCHDOG_MINOR;
500*4882a593Smuzhiyun watchdog_device.miscdev.name = "watchdog";
501*4882a593Smuzhiyun watchdog_device.miscdev.fops = &intel_scu_fops;
502*4882a593Smuzhiyun
503*4882a593Smuzhiyun ret = misc_register(&watchdog_device.miscdev);
504*4882a593Smuzhiyun if (ret) {
505*4882a593Smuzhiyun pr_err("cannot register miscdev %d err =%d\n",
506*4882a593Smuzhiyun WATCHDOG_MINOR, ret);
507*4882a593Smuzhiyun goto misc_register_error;
508*4882a593Smuzhiyun }
509*4882a593Smuzhiyun
510*4882a593Smuzhiyun ret = request_irq((unsigned int)watchdog_device.timer_tbl_ptr->irq,
511*4882a593Smuzhiyun watchdog_timer_interrupt,
512*4882a593Smuzhiyun IRQF_SHARED, "watchdog",
513*4882a593Smuzhiyun &watchdog_device.timer_load_count_addr);
514*4882a593Smuzhiyun if (ret) {
515*4882a593Smuzhiyun pr_err("error requesting irq %d\n", ret);
516*4882a593Smuzhiyun goto request_irq_error;
517*4882a593Smuzhiyun }
518*4882a593Smuzhiyun /* Make sure timer is disabled before returning */
519*4882a593Smuzhiyun intel_scu_stop();
520*4882a593Smuzhiyun return 0;
521*4882a593Smuzhiyun
522*4882a593Smuzhiyun /* error cleanup */
523*4882a593Smuzhiyun
524*4882a593Smuzhiyun request_irq_error:
525*4882a593Smuzhiyun misc_deregister(&watchdog_device.miscdev);
526*4882a593Smuzhiyun misc_register_error:
527*4882a593Smuzhiyun unregister_reboot_notifier(&watchdog_device.intel_scu_notifier);
528*4882a593Smuzhiyun register_reboot_error:
529*4882a593Smuzhiyun intel_scu_stop();
530*4882a593Smuzhiyun iounmap(watchdog_device.timer_load_count_addr);
531*4882a593Smuzhiyun return ret;
532*4882a593Smuzhiyun }
533*4882a593Smuzhiyun late_initcall(intel_scu_watchdog_init);
534