1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0+
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Watchdog driver for Broadcom BCM2835
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * "bcm2708_wdog" driver written by Luke Diamand that was obtained from
6*4882a593Smuzhiyun * branch "rpi-3.6.y" of git://github.com/raspberrypi/linux.git was used
7*4882a593Smuzhiyun * as a hardware reference for the Broadcom BCM2835 watchdog timer.
8*4882a593Smuzhiyun *
9*4882a593Smuzhiyun * Copyright (C) 2013 Lubomir Rintel <lkundrak@v3.sk>
10*4882a593Smuzhiyun *
11*4882a593Smuzhiyun */
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun #include <linux/delay.h>
14*4882a593Smuzhiyun #include <linux/types.h>
15*4882a593Smuzhiyun #include <linux/mfd/bcm2835-pm.h>
16*4882a593Smuzhiyun #include <linux/module.h>
17*4882a593Smuzhiyun #include <linux/io.h>
18*4882a593Smuzhiyun #include <linux/watchdog.h>
19*4882a593Smuzhiyun #include <linux/platform_device.h>
20*4882a593Smuzhiyun #include <linux/of_address.h>
21*4882a593Smuzhiyun #include <linux/of_platform.h>
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun #define PM_RSTC 0x1c
24*4882a593Smuzhiyun #define PM_RSTS 0x20
25*4882a593Smuzhiyun #define PM_WDOG 0x24
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun #define PM_PASSWORD 0x5a000000
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun #define PM_WDOG_TIME_SET 0x000fffff
30*4882a593Smuzhiyun #define PM_RSTC_WRCFG_CLR 0xffffffcf
31*4882a593Smuzhiyun #define PM_RSTS_HADWRH_SET 0x00000040
32*4882a593Smuzhiyun #define PM_RSTC_WRCFG_SET 0x00000030
33*4882a593Smuzhiyun #define PM_RSTC_WRCFG_FULL_RESET 0x00000020
34*4882a593Smuzhiyun #define PM_RSTC_RESET 0x00000102
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun /*
37*4882a593Smuzhiyun * The Raspberry Pi firmware uses the RSTS register to know which partition
38*4882a593Smuzhiyun * to boot from. The partition value is spread into bits 0, 2, 4, 6, 8, 10.
39*4882a593Smuzhiyun * Partition 63 is a special partition used by the firmware to indicate halt.
40*4882a593Smuzhiyun */
41*4882a593Smuzhiyun #define PM_RSTS_RASPBERRYPI_HALT 0x555
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun #define SECS_TO_WDOG_TICKS(x) ((x) << 16)
44*4882a593Smuzhiyun #define WDOG_TICKS_TO_SECS(x) ((x) >> 16)
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun struct bcm2835_wdt {
47*4882a593Smuzhiyun void __iomem *base;
48*4882a593Smuzhiyun spinlock_t lock;
49*4882a593Smuzhiyun };
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun static struct bcm2835_wdt *bcm2835_power_off_wdt;
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun static unsigned int heartbeat;
54*4882a593Smuzhiyun static bool nowayout = WATCHDOG_NOWAYOUT;
55*4882a593Smuzhiyun
bcm2835_wdt_is_running(struct bcm2835_wdt * wdt)56*4882a593Smuzhiyun static bool bcm2835_wdt_is_running(struct bcm2835_wdt *wdt)
57*4882a593Smuzhiyun {
58*4882a593Smuzhiyun uint32_t cur;
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun cur = readl(wdt->base + PM_RSTC);
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun return !!(cur & PM_RSTC_WRCFG_FULL_RESET);
63*4882a593Smuzhiyun }
64*4882a593Smuzhiyun
bcm2835_wdt_start(struct watchdog_device * wdog)65*4882a593Smuzhiyun static int bcm2835_wdt_start(struct watchdog_device *wdog)
66*4882a593Smuzhiyun {
67*4882a593Smuzhiyun struct bcm2835_wdt *wdt = watchdog_get_drvdata(wdog);
68*4882a593Smuzhiyun uint32_t cur;
69*4882a593Smuzhiyun unsigned long flags;
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun spin_lock_irqsave(&wdt->lock, flags);
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun writel_relaxed(PM_PASSWORD | (SECS_TO_WDOG_TICKS(wdog->timeout) &
74*4882a593Smuzhiyun PM_WDOG_TIME_SET), wdt->base + PM_WDOG);
75*4882a593Smuzhiyun cur = readl_relaxed(wdt->base + PM_RSTC);
76*4882a593Smuzhiyun writel_relaxed(PM_PASSWORD | (cur & PM_RSTC_WRCFG_CLR) |
77*4882a593Smuzhiyun PM_RSTC_WRCFG_FULL_RESET, wdt->base + PM_RSTC);
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun spin_unlock_irqrestore(&wdt->lock, flags);
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun return 0;
82*4882a593Smuzhiyun }
83*4882a593Smuzhiyun
bcm2835_wdt_stop(struct watchdog_device * wdog)84*4882a593Smuzhiyun static int bcm2835_wdt_stop(struct watchdog_device *wdog)
85*4882a593Smuzhiyun {
86*4882a593Smuzhiyun struct bcm2835_wdt *wdt = watchdog_get_drvdata(wdog);
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun writel_relaxed(PM_PASSWORD | PM_RSTC_RESET, wdt->base + PM_RSTC);
89*4882a593Smuzhiyun return 0;
90*4882a593Smuzhiyun }
91*4882a593Smuzhiyun
bcm2835_wdt_get_timeleft(struct watchdog_device * wdog)92*4882a593Smuzhiyun static unsigned int bcm2835_wdt_get_timeleft(struct watchdog_device *wdog)
93*4882a593Smuzhiyun {
94*4882a593Smuzhiyun struct bcm2835_wdt *wdt = watchdog_get_drvdata(wdog);
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun uint32_t ret = readl_relaxed(wdt->base + PM_WDOG);
97*4882a593Smuzhiyun return WDOG_TICKS_TO_SECS(ret & PM_WDOG_TIME_SET);
98*4882a593Smuzhiyun }
99*4882a593Smuzhiyun
__bcm2835_restart(struct bcm2835_wdt * wdt)100*4882a593Smuzhiyun static void __bcm2835_restart(struct bcm2835_wdt *wdt)
101*4882a593Smuzhiyun {
102*4882a593Smuzhiyun u32 val;
103*4882a593Smuzhiyun
104*4882a593Smuzhiyun /* use a timeout of 10 ticks (~150us) */
105*4882a593Smuzhiyun writel_relaxed(10 | PM_PASSWORD, wdt->base + PM_WDOG);
106*4882a593Smuzhiyun val = readl_relaxed(wdt->base + PM_RSTC);
107*4882a593Smuzhiyun val &= PM_RSTC_WRCFG_CLR;
108*4882a593Smuzhiyun val |= PM_PASSWORD | PM_RSTC_WRCFG_FULL_RESET;
109*4882a593Smuzhiyun writel_relaxed(val, wdt->base + PM_RSTC);
110*4882a593Smuzhiyun
111*4882a593Smuzhiyun /* No sleeping, possibly atomic. */
112*4882a593Smuzhiyun mdelay(1);
113*4882a593Smuzhiyun }
114*4882a593Smuzhiyun
bcm2835_restart(struct watchdog_device * wdog,unsigned long action,void * data)115*4882a593Smuzhiyun static int bcm2835_restart(struct watchdog_device *wdog,
116*4882a593Smuzhiyun unsigned long action, void *data)
117*4882a593Smuzhiyun {
118*4882a593Smuzhiyun struct bcm2835_wdt *wdt = watchdog_get_drvdata(wdog);
119*4882a593Smuzhiyun
120*4882a593Smuzhiyun __bcm2835_restart(wdt);
121*4882a593Smuzhiyun
122*4882a593Smuzhiyun return 0;
123*4882a593Smuzhiyun }
124*4882a593Smuzhiyun
125*4882a593Smuzhiyun static const struct watchdog_ops bcm2835_wdt_ops = {
126*4882a593Smuzhiyun .owner = THIS_MODULE,
127*4882a593Smuzhiyun .start = bcm2835_wdt_start,
128*4882a593Smuzhiyun .stop = bcm2835_wdt_stop,
129*4882a593Smuzhiyun .get_timeleft = bcm2835_wdt_get_timeleft,
130*4882a593Smuzhiyun .restart = bcm2835_restart,
131*4882a593Smuzhiyun };
132*4882a593Smuzhiyun
133*4882a593Smuzhiyun static const struct watchdog_info bcm2835_wdt_info = {
134*4882a593Smuzhiyun .options = WDIOF_SETTIMEOUT | WDIOF_MAGICCLOSE |
135*4882a593Smuzhiyun WDIOF_KEEPALIVEPING,
136*4882a593Smuzhiyun .identity = "Broadcom BCM2835 Watchdog timer",
137*4882a593Smuzhiyun };
138*4882a593Smuzhiyun
139*4882a593Smuzhiyun static struct watchdog_device bcm2835_wdt_wdd = {
140*4882a593Smuzhiyun .info = &bcm2835_wdt_info,
141*4882a593Smuzhiyun .ops = &bcm2835_wdt_ops,
142*4882a593Smuzhiyun .min_timeout = 1,
143*4882a593Smuzhiyun .max_timeout = WDOG_TICKS_TO_SECS(PM_WDOG_TIME_SET),
144*4882a593Smuzhiyun .timeout = WDOG_TICKS_TO_SECS(PM_WDOG_TIME_SET),
145*4882a593Smuzhiyun };
146*4882a593Smuzhiyun
147*4882a593Smuzhiyun /*
148*4882a593Smuzhiyun * We can't really power off, but if we do the normal reset scheme, and
149*4882a593Smuzhiyun * indicate to bootcode.bin not to reboot, then most of the chip will be
150*4882a593Smuzhiyun * powered off.
151*4882a593Smuzhiyun */
bcm2835_power_off(void)152*4882a593Smuzhiyun static void bcm2835_power_off(void)
153*4882a593Smuzhiyun {
154*4882a593Smuzhiyun struct bcm2835_wdt *wdt = bcm2835_power_off_wdt;
155*4882a593Smuzhiyun u32 val;
156*4882a593Smuzhiyun
157*4882a593Smuzhiyun /*
158*4882a593Smuzhiyun * We set the watchdog hard reset bit here to distinguish this reset
159*4882a593Smuzhiyun * from the normal (full) reset. bootcode.bin will not reboot after a
160*4882a593Smuzhiyun * hard reset.
161*4882a593Smuzhiyun */
162*4882a593Smuzhiyun val = readl_relaxed(wdt->base + PM_RSTS);
163*4882a593Smuzhiyun val |= PM_PASSWORD | PM_RSTS_RASPBERRYPI_HALT;
164*4882a593Smuzhiyun writel_relaxed(val, wdt->base + PM_RSTS);
165*4882a593Smuzhiyun
166*4882a593Smuzhiyun /* Continue with normal reset mechanism */
167*4882a593Smuzhiyun __bcm2835_restart(wdt);
168*4882a593Smuzhiyun }
169*4882a593Smuzhiyun
bcm2835_wdt_probe(struct platform_device * pdev)170*4882a593Smuzhiyun static int bcm2835_wdt_probe(struct platform_device *pdev)
171*4882a593Smuzhiyun {
172*4882a593Smuzhiyun struct bcm2835_pm *pm = dev_get_drvdata(pdev->dev.parent);
173*4882a593Smuzhiyun struct device *dev = &pdev->dev;
174*4882a593Smuzhiyun struct bcm2835_wdt *wdt;
175*4882a593Smuzhiyun int err;
176*4882a593Smuzhiyun
177*4882a593Smuzhiyun wdt = devm_kzalloc(dev, sizeof(struct bcm2835_wdt), GFP_KERNEL);
178*4882a593Smuzhiyun if (!wdt)
179*4882a593Smuzhiyun return -ENOMEM;
180*4882a593Smuzhiyun
181*4882a593Smuzhiyun spin_lock_init(&wdt->lock);
182*4882a593Smuzhiyun
183*4882a593Smuzhiyun wdt->base = pm->base;
184*4882a593Smuzhiyun
185*4882a593Smuzhiyun watchdog_set_drvdata(&bcm2835_wdt_wdd, wdt);
186*4882a593Smuzhiyun watchdog_init_timeout(&bcm2835_wdt_wdd, heartbeat, dev);
187*4882a593Smuzhiyun watchdog_set_nowayout(&bcm2835_wdt_wdd, nowayout);
188*4882a593Smuzhiyun bcm2835_wdt_wdd.parent = dev;
189*4882a593Smuzhiyun if (bcm2835_wdt_is_running(wdt)) {
190*4882a593Smuzhiyun /*
191*4882a593Smuzhiyun * The currently active timeout value (set by the
192*4882a593Smuzhiyun * bootloader) may be different from the module
193*4882a593Smuzhiyun * heartbeat parameter or the value in device
194*4882a593Smuzhiyun * tree. But we just need to set WDOG_HW_RUNNING,
195*4882a593Smuzhiyun * because then the framework will "immediately" ping
196*4882a593Smuzhiyun * the device, updating the timeout.
197*4882a593Smuzhiyun */
198*4882a593Smuzhiyun set_bit(WDOG_HW_RUNNING, &bcm2835_wdt_wdd.status);
199*4882a593Smuzhiyun }
200*4882a593Smuzhiyun
201*4882a593Smuzhiyun watchdog_set_restart_priority(&bcm2835_wdt_wdd, 128);
202*4882a593Smuzhiyun
203*4882a593Smuzhiyun watchdog_stop_on_reboot(&bcm2835_wdt_wdd);
204*4882a593Smuzhiyun err = devm_watchdog_register_device(dev, &bcm2835_wdt_wdd);
205*4882a593Smuzhiyun if (err)
206*4882a593Smuzhiyun return err;
207*4882a593Smuzhiyun
208*4882a593Smuzhiyun if (pm_power_off == NULL) {
209*4882a593Smuzhiyun pm_power_off = bcm2835_power_off;
210*4882a593Smuzhiyun bcm2835_power_off_wdt = wdt;
211*4882a593Smuzhiyun }
212*4882a593Smuzhiyun
213*4882a593Smuzhiyun dev_info(dev, "Broadcom BCM2835 watchdog timer");
214*4882a593Smuzhiyun return 0;
215*4882a593Smuzhiyun }
216*4882a593Smuzhiyun
bcm2835_wdt_remove(struct platform_device * pdev)217*4882a593Smuzhiyun static int bcm2835_wdt_remove(struct platform_device *pdev)
218*4882a593Smuzhiyun {
219*4882a593Smuzhiyun if (pm_power_off == bcm2835_power_off)
220*4882a593Smuzhiyun pm_power_off = NULL;
221*4882a593Smuzhiyun
222*4882a593Smuzhiyun return 0;
223*4882a593Smuzhiyun }
224*4882a593Smuzhiyun
225*4882a593Smuzhiyun static struct platform_driver bcm2835_wdt_driver = {
226*4882a593Smuzhiyun .probe = bcm2835_wdt_probe,
227*4882a593Smuzhiyun .remove = bcm2835_wdt_remove,
228*4882a593Smuzhiyun .driver = {
229*4882a593Smuzhiyun .name = "bcm2835-wdt",
230*4882a593Smuzhiyun },
231*4882a593Smuzhiyun };
232*4882a593Smuzhiyun module_platform_driver(bcm2835_wdt_driver);
233*4882a593Smuzhiyun
234*4882a593Smuzhiyun module_param(heartbeat, uint, 0);
235*4882a593Smuzhiyun MODULE_PARM_DESC(heartbeat, "Initial watchdog heartbeat in seconds");
236*4882a593Smuzhiyun
237*4882a593Smuzhiyun module_param(nowayout, bool, 0);
238*4882a593Smuzhiyun MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
239*4882a593Smuzhiyun __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
240*4882a593Smuzhiyun
241*4882a593Smuzhiyun MODULE_ALIAS("platform:bcm2835-wdt");
242*4882a593Smuzhiyun MODULE_AUTHOR("Lubomir Rintel <lkundrak@v3.sk>");
243*4882a593Smuzhiyun MODULE_DESCRIPTION("Driver for Broadcom BCM2835 watchdog timer");
244*4882a593Smuzhiyun MODULE_LICENSE("GPL");
245