1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Watchdog driver for CSR Atlas7
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (c) 2015 Cambridge Silicon Radio Limited, a CSR plc group company.
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #include <linux/clk.h>
9*4882a593Smuzhiyun #include <linux/io.h>
10*4882a593Smuzhiyun #include <linux/module.h>
11*4882a593Smuzhiyun #include <linux/moduleparam.h>
12*4882a593Smuzhiyun #include <linux/of.h>
13*4882a593Smuzhiyun #include <linux/platform_device.h>
14*4882a593Smuzhiyun #include <linux/watchdog.h>
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun #define ATLAS7_TIMER_WDT_INDEX 5
17*4882a593Smuzhiyun #define ATLAS7_WDT_DEFAULT_TIMEOUT 20
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun #define ATLAS7_WDT_CNT_CTRL (0 + 4 * ATLAS7_TIMER_WDT_INDEX)
20*4882a593Smuzhiyun #define ATLAS7_WDT_CNT_MATCH (0x18 + 4 * ATLAS7_TIMER_WDT_INDEX)
21*4882a593Smuzhiyun #define ATLAS7_WDT_CNT (0x48 + 4 * ATLAS7_TIMER_WDT_INDEX)
22*4882a593Smuzhiyun #define ATLAS7_WDT_CNT_EN (BIT(0) | BIT(1))
23*4882a593Smuzhiyun #define ATLAS7_WDT_EN 0x64
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun static unsigned int timeout = ATLAS7_WDT_DEFAULT_TIMEOUT;
26*4882a593Smuzhiyun static bool nowayout = WATCHDOG_NOWAYOUT;
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun module_param(timeout, uint, 0);
29*4882a593Smuzhiyun module_param(nowayout, bool, 0);
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun MODULE_PARM_DESC(timeout, "Default watchdog timeout (in seconds)");
32*4882a593Smuzhiyun MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
33*4882a593Smuzhiyun __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun struct atlas7_wdog {
36*4882a593Smuzhiyun struct device *dev;
37*4882a593Smuzhiyun void __iomem *base;
38*4882a593Smuzhiyun unsigned long tick_rate;
39*4882a593Smuzhiyun struct clk *clk;
40*4882a593Smuzhiyun };
41*4882a593Smuzhiyun
atlas7_wdt_gettimeleft(struct watchdog_device * wdd)42*4882a593Smuzhiyun static unsigned int atlas7_wdt_gettimeleft(struct watchdog_device *wdd)
43*4882a593Smuzhiyun {
44*4882a593Smuzhiyun struct atlas7_wdog *wdt = watchdog_get_drvdata(wdd);
45*4882a593Smuzhiyun u32 counter, match, delta;
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun counter = readl(wdt->base + ATLAS7_WDT_CNT);
48*4882a593Smuzhiyun match = readl(wdt->base + ATLAS7_WDT_CNT_MATCH);
49*4882a593Smuzhiyun delta = match - counter;
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun return delta / wdt->tick_rate;
52*4882a593Smuzhiyun }
53*4882a593Smuzhiyun
atlas7_wdt_ping(struct watchdog_device * wdd)54*4882a593Smuzhiyun static int atlas7_wdt_ping(struct watchdog_device *wdd)
55*4882a593Smuzhiyun {
56*4882a593Smuzhiyun struct atlas7_wdog *wdt = watchdog_get_drvdata(wdd);
57*4882a593Smuzhiyun u32 counter, match, delta;
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun counter = readl(wdt->base + ATLAS7_WDT_CNT);
60*4882a593Smuzhiyun delta = wdd->timeout * wdt->tick_rate;
61*4882a593Smuzhiyun match = counter + delta;
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun writel(match, wdt->base + ATLAS7_WDT_CNT_MATCH);
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun return 0;
66*4882a593Smuzhiyun }
67*4882a593Smuzhiyun
atlas7_wdt_enable(struct watchdog_device * wdd)68*4882a593Smuzhiyun static int atlas7_wdt_enable(struct watchdog_device *wdd)
69*4882a593Smuzhiyun {
70*4882a593Smuzhiyun struct atlas7_wdog *wdt = watchdog_get_drvdata(wdd);
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun atlas7_wdt_ping(wdd);
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun writel(readl(wdt->base + ATLAS7_WDT_CNT_CTRL) | ATLAS7_WDT_CNT_EN,
75*4882a593Smuzhiyun wdt->base + ATLAS7_WDT_CNT_CTRL);
76*4882a593Smuzhiyun writel(1, wdt->base + ATLAS7_WDT_EN);
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun return 0;
79*4882a593Smuzhiyun }
80*4882a593Smuzhiyun
atlas7_wdt_disable(struct watchdog_device * wdd)81*4882a593Smuzhiyun static int atlas7_wdt_disable(struct watchdog_device *wdd)
82*4882a593Smuzhiyun {
83*4882a593Smuzhiyun struct atlas7_wdog *wdt = watchdog_get_drvdata(wdd);
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun writel(0, wdt->base + ATLAS7_WDT_EN);
86*4882a593Smuzhiyun writel(readl(wdt->base + ATLAS7_WDT_CNT_CTRL) & ~ATLAS7_WDT_CNT_EN,
87*4882a593Smuzhiyun wdt->base + ATLAS7_WDT_CNT_CTRL);
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun return 0;
90*4882a593Smuzhiyun }
91*4882a593Smuzhiyun
atlas7_wdt_settimeout(struct watchdog_device * wdd,unsigned int to)92*4882a593Smuzhiyun static int atlas7_wdt_settimeout(struct watchdog_device *wdd, unsigned int to)
93*4882a593Smuzhiyun {
94*4882a593Smuzhiyun wdd->timeout = to;
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun return 0;
97*4882a593Smuzhiyun }
98*4882a593Smuzhiyun
99*4882a593Smuzhiyun #define OPTIONS (WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE)
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun static const struct watchdog_info atlas7_wdt_ident = {
102*4882a593Smuzhiyun .options = OPTIONS,
103*4882a593Smuzhiyun .firmware_version = 0,
104*4882a593Smuzhiyun .identity = "atlas7 Watchdog",
105*4882a593Smuzhiyun };
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun static const struct watchdog_ops atlas7_wdt_ops = {
108*4882a593Smuzhiyun .owner = THIS_MODULE,
109*4882a593Smuzhiyun .start = atlas7_wdt_enable,
110*4882a593Smuzhiyun .stop = atlas7_wdt_disable,
111*4882a593Smuzhiyun .get_timeleft = atlas7_wdt_gettimeleft,
112*4882a593Smuzhiyun .ping = atlas7_wdt_ping,
113*4882a593Smuzhiyun .set_timeout = atlas7_wdt_settimeout,
114*4882a593Smuzhiyun };
115*4882a593Smuzhiyun
116*4882a593Smuzhiyun static struct watchdog_device atlas7_wdd = {
117*4882a593Smuzhiyun .info = &atlas7_wdt_ident,
118*4882a593Smuzhiyun .ops = &atlas7_wdt_ops,
119*4882a593Smuzhiyun .timeout = ATLAS7_WDT_DEFAULT_TIMEOUT,
120*4882a593Smuzhiyun };
121*4882a593Smuzhiyun
122*4882a593Smuzhiyun static const struct of_device_id atlas7_wdt_ids[] = {
123*4882a593Smuzhiyun { .compatible = "sirf,atlas7-tick"},
124*4882a593Smuzhiyun {}
125*4882a593Smuzhiyun };
126*4882a593Smuzhiyun
atlas7_clk_disable_unprepare(void * data)127*4882a593Smuzhiyun static void atlas7_clk_disable_unprepare(void *data)
128*4882a593Smuzhiyun {
129*4882a593Smuzhiyun clk_disable_unprepare(data);
130*4882a593Smuzhiyun }
131*4882a593Smuzhiyun
atlas7_wdt_probe(struct platform_device * pdev)132*4882a593Smuzhiyun static int atlas7_wdt_probe(struct platform_device *pdev)
133*4882a593Smuzhiyun {
134*4882a593Smuzhiyun struct device *dev = &pdev->dev;
135*4882a593Smuzhiyun struct atlas7_wdog *wdt;
136*4882a593Smuzhiyun struct clk *clk;
137*4882a593Smuzhiyun int ret;
138*4882a593Smuzhiyun
139*4882a593Smuzhiyun wdt = devm_kzalloc(dev, sizeof(*wdt), GFP_KERNEL);
140*4882a593Smuzhiyun if (!wdt)
141*4882a593Smuzhiyun return -ENOMEM;
142*4882a593Smuzhiyun wdt->base = devm_platform_ioremap_resource(pdev, 0);
143*4882a593Smuzhiyun if (IS_ERR(wdt->base))
144*4882a593Smuzhiyun return PTR_ERR(wdt->base);
145*4882a593Smuzhiyun
146*4882a593Smuzhiyun clk = devm_clk_get(dev, NULL);
147*4882a593Smuzhiyun if (IS_ERR(clk))
148*4882a593Smuzhiyun return PTR_ERR(clk);
149*4882a593Smuzhiyun ret = clk_prepare_enable(clk);
150*4882a593Smuzhiyun if (ret) {
151*4882a593Smuzhiyun dev_err(dev, "clk enable failed\n");
152*4882a593Smuzhiyun return ret;
153*4882a593Smuzhiyun }
154*4882a593Smuzhiyun ret = devm_add_action_or_reset(dev, atlas7_clk_disable_unprepare, clk);
155*4882a593Smuzhiyun if (ret)
156*4882a593Smuzhiyun return ret;
157*4882a593Smuzhiyun
158*4882a593Smuzhiyun /* disable watchdog hardware */
159*4882a593Smuzhiyun writel(0, wdt->base + ATLAS7_WDT_CNT_CTRL);
160*4882a593Smuzhiyun
161*4882a593Smuzhiyun wdt->tick_rate = clk_get_rate(clk);
162*4882a593Smuzhiyun if (!wdt->tick_rate)
163*4882a593Smuzhiyun return -EINVAL;
164*4882a593Smuzhiyun
165*4882a593Smuzhiyun wdt->clk = clk;
166*4882a593Smuzhiyun atlas7_wdd.min_timeout = 1;
167*4882a593Smuzhiyun atlas7_wdd.max_timeout = UINT_MAX / wdt->tick_rate;
168*4882a593Smuzhiyun
169*4882a593Smuzhiyun watchdog_init_timeout(&atlas7_wdd, 0, dev);
170*4882a593Smuzhiyun watchdog_set_nowayout(&atlas7_wdd, nowayout);
171*4882a593Smuzhiyun
172*4882a593Smuzhiyun watchdog_set_drvdata(&atlas7_wdd, wdt);
173*4882a593Smuzhiyun platform_set_drvdata(pdev, &atlas7_wdd);
174*4882a593Smuzhiyun
175*4882a593Smuzhiyun watchdog_stop_on_reboot(&atlas7_wdd);
176*4882a593Smuzhiyun watchdog_stop_on_unregister(&atlas7_wdd);
177*4882a593Smuzhiyun return devm_watchdog_register_device(dev, &atlas7_wdd);
178*4882a593Smuzhiyun }
179*4882a593Smuzhiyun
atlas7_wdt_suspend(struct device * dev)180*4882a593Smuzhiyun static int __maybe_unused atlas7_wdt_suspend(struct device *dev)
181*4882a593Smuzhiyun {
182*4882a593Smuzhiyun /*
183*4882a593Smuzhiyun * NOTE:timer controller registers settings are saved
184*4882a593Smuzhiyun * and restored back by the timer-atlas7.c
185*4882a593Smuzhiyun */
186*4882a593Smuzhiyun return 0;
187*4882a593Smuzhiyun }
188*4882a593Smuzhiyun
atlas7_wdt_resume(struct device * dev)189*4882a593Smuzhiyun static int __maybe_unused atlas7_wdt_resume(struct device *dev)
190*4882a593Smuzhiyun {
191*4882a593Smuzhiyun struct watchdog_device *wdd = dev_get_drvdata(dev);
192*4882a593Smuzhiyun
193*4882a593Smuzhiyun /*
194*4882a593Smuzhiyun * NOTE: Since timer controller registers settings are saved
195*4882a593Smuzhiyun * and restored back by the timer-atlas7.c, so we need not
196*4882a593Smuzhiyun * update WD settings except refreshing timeout.
197*4882a593Smuzhiyun */
198*4882a593Smuzhiyun atlas7_wdt_ping(wdd);
199*4882a593Smuzhiyun
200*4882a593Smuzhiyun return 0;
201*4882a593Smuzhiyun }
202*4882a593Smuzhiyun
203*4882a593Smuzhiyun static SIMPLE_DEV_PM_OPS(atlas7_wdt_pm_ops,
204*4882a593Smuzhiyun atlas7_wdt_suspend, atlas7_wdt_resume);
205*4882a593Smuzhiyun
206*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, atlas7_wdt_ids);
207*4882a593Smuzhiyun
208*4882a593Smuzhiyun static struct platform_driver atlas7_wdt_driver = {
209*4882a593Smuzhiyun .driver = {
210*4882a593Smuzhiyun .name = "atlas7-wdt",
211*4882a593Smuzhiyun .pm = &atlas7_wdt_pm_ops,
212*4882a593Smuzhiyun .of_match_table = atlas7_wdt_ids,
213*4882a593Smuzhiyun },
214*4882a593Smuzhiyun .probe = atlas7_wdt_probe,
215*4882a593Smuzhiyun };
216*4882a593Smuzhiyun module_platform_driver(atlas7_wdt_driver);
217*4882a593Smuzhiyun
218*4882a593Smuzhiyun MODULE_DESCRIPTION("CSRatlas7 watchdog driver");
219*4882a593Smuzhiyun MODULE_AUTHOR("Guo Zeng <Guo.Zeng@csr.com>");
220*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
221*4882a593Smuzhiyun MODULE_ALIAS("platform:atlas7-wdt");
222