1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0+ */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * drivers/watchdog/at91sam9_wdt.h 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2007 Andrew Victor 6*4882a593Smuzhiyun * Copyright (C) 2007 Atmel Corporation. 7*4882a593Smuzhiyun * Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries 8*4882a593Smuzhiyun * 9*4882a593Smuzhiyun * Watchdog Timer (WDT) - System peripherals regsters. 10*4882a593Smuzhiyun * Based on AT91SAM9261 datasheet revision D. 11*4882a593Smuzhiyun * Based on SAM9X60 datasheet. 12*4882a593Smuzhiyun * 13*4882a593Smuzhiyun */ 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #ifndef AT91_WDT_H 16*4882a593Smuzhiyun #define AT91_WDT_H 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun #include <linux/bits.h> 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun #define AT91_WDT_CR 0x00 /* Watchdog Control Register */ 21*4882a593Smuzhiyun #define AT91_WDT_WDRSTT BIT(0) /* Restart */ 22*4882a593Smuzhiyun #define AT91_WDT_KEY (0xa5UL << 24) /* KEY Password */ 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun #define AT91_WDT_MR 0x04 /* Watchdog Mode Register */ 25*4882a593Smuzhiyun #define AT91_WDT_WDV (0xfffUL << 0) /* Counter Value */ 26*4882a593Smuzhiyun #define AT91_WDT_SET_WDV(x) ((x) & AT91_WDT_WDV) 27*4882a593Smuzhiyun #define AT91_SAM9X60_PERIODRST BIT(4) /* Period Reset */ 28*4882a593Smuzhiyun #define AT91_SAM9X60_RPTHRST BIT(5) /* Minimum Restart Period */ 29*4882a593Smuzhiyun #define AT91_WDT_WDFIEN BIT(12) /* Fault Interrupt Enable */ 30*4882a593Smuzhiyun #define AT91_SAM9X60_WDDIS BIT(12) /* Watchdog Disable */ 31*4882a593Smuzhiyun #define AT91_WDT_WDRSTEN BIT(13) /* Reset Processor */ 32*4882a593Smuzhiyun #define AT91_WDT_WDRPROC BIT(14) /* Timer Restart */ 33*4882a593Smuzhiyun #define AT91_WDT_WDDIS BIT(15) /* Watchdog Disable */ 34*4882a593Smuzhiyun #define AT91_WDT_WDD (0xfffUL << 16) /* Delta Value */ 35*4882a593Smuzhiyun #define AT91_WDT_SET_WDD(x) (((x) << 16) & AT91_WDT_WDD) 36*4882a593Smuzhiyun #define AT91_WDT_WDDBGHLT BIT(28) /* Debug Halt */ 37*4882a593Smuzhiyun #define AT91_WDT_WDIDLEHLT BIT(29) /* Idle Halt */ 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun #define AT91_WDT_SR 0x08 /* Watchdog Status Register */ 40*4882a593Smuzhiyun #define AT91_WDT_WDUNF BIT(0) /* Watchdog Underflow */ 41*4882a593Smuzhiyun #define AT91_WDT_WDERR BIT(1) /* Watchdog Error */ 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun /* Watchdog Timer Value Register */ 44*4882a593Smuzhiyun #define AT91_SAM9X60_VR 0x08 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun /* Watchdog Window Level Register */ 47*4882a593Smuzhiyun #define AT91_SAM9X60_WLR 0x0c 48*4882a593Smuzhiyun /* Watchdog Period Value */ 49*4882a593Smuzhiyun #define AT91_SAM9X60_COUNTER (0xfffUL << 0) 50*4882a593Smuzhiyun #define AT91_SAM9X60_SET_COUNTER(x) ((x) & AT91_SAM9X60_COUNTER) 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun /* Interrupt Enable Register */ 53*4882a593Smuzhiyun #define AT91_SAM9X60_IER 0x14 54*4882a593Smuzhiyun /* Period Interrupt Enable */ 55*4882a593Smuzhiyun #define AT91_SAM9X60_PERINT BIT(0) 56*4882a593Smuzhiyun /* Interrupt Disable Register */ 57*4882a593Smuzhiyun #define AT91_SAM9X60_IDR 0x18 58*4882a593Smuzhiyun /* Interrupt Status Register */ 59*4882a593Smuzhiyun #define AT91_SAM9X60_ISR 0x1c 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun #endif 62