xref: /OK3568_Linux_fs/kernel/drivers/watchdog/at91sam9_wdt.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0+
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * Watchdog driver for Atmel AT91SAM9x processors.
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Copyright (C) 2008 Renaud CERRATO r.cerrato@til-technologies.fr
6*4882a593Smuzhiyun  *
7*4882a593Smuzhiyun  */
8*4882a593Smuzhiyun 
9*4882a593Smuzhiyun /*
10*4882a593Smuzhiyun  * The Watchdog Timer Mode Register can be only written to once. If the
11*4882a593Smuzhiyun  * timeout need to be set from Linux, be sure that the bootstrap or the
12*4882a593Smuzhiyun  * bootloader doesn't write to this register.
13*4882a593Smuzhiyun  */
14*4882a593Smuzhiyun 
15*4882a593Smuzhiyun #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
16*4882a593Smuzhiyun 
17*4882a593Smuzhiyun #include <linux/clk.h>
18*4882a593Smuzhiyun #include <linux/errno.h>
19*4882a593Smuzhiyun #include <linux/init.h>
20*4882a593Smuzhiyun #include <linux/interrupt.h>
21*4882a593Smuzhiyun #include <linux/io.h>
22*4882a593Smuzhiyun #include <linux/kernel.h>
23*4882a593Smuzhiyun #include <linux/module.h>
24*4882a593Smuzhiyun #include <linux/moduleparam.h>
25*4882a593Smuzhiyun #include <linux/platform_device.h>
26*4882a593Smuzhiyun #include <linux/reboot.h>
27*4882a593Smuzhiyun #include <linux/types.h>
28*4882a593Smuzhiyun #include <linux/watchdog.h>
29*4882a593Smuzhiyun #include <linux/jiffies.h>
30*4882a593Smuzhiyun #include <linux/timer.h>
31*4882a593Smuzhiyun #include <linux/bitops.h>
32*4882a593Smuzhiyun #include <linux/uaccess.h>
33*4882a593Smuzhiyun #include <linux/of.h>
34*4882a593Smuzhiyun #include <linux/of_irq.h>
35*4882a593Smuzhiyun 
36*4882a593Smuzhiyun #include "at91sam9_wdt.h"
37*4882a593Smuzhiyun 
38*4882a593Smuzhiyun #define DRV_NAME "AT91SAM9 Watchdog"
39*4882a593Smuzhiyun 
40*4882a593Smuzhiyun #define wdt_read(wdt, field) \
41*4882a593Smuzhiyun 	readl_relaxed((wdt)->base + (field))
42*4882a593Smuzhiyun #define wdt_write(wtd, field, val) \
43*4882a593Smuzhiyun 	writel_relaxed((val), (wdt)->base + (field))
44*4882a593Smuzhiyun 
45*4882a593Smuzhiyun /* AT91SAM9 watchdog runs a 12bit counter @ 256Hz,
46*4882a593Smuzhiyun  * use this to convert a watchdog
47*4882a593Smuzhiyun  * value from/to milliseconds.
48*4882a593Smuzhiyun  */
49*4882a593Smuzhiyun #define ticks_to_hz_rounddown(t)	((((t) + 1) * HZ) >> 8)
50*4882a593Smuzhiyun #define ticks_to_hz_roundup(t)		(((((t) + 1) * HZ) + 255) >> 8)
51*4882a593Smuzhiyun #define ticks_to_secs(t)		(((t) + 1) >> 8)
52*4882a593Smuzhiyun #define secs_to_ticks(s)		((s) ? (((s) << 8) - 1) : 0)
53*4882a593Smuzhiyun 
54*4882a593Smuzhiyun #define WDT_MR_RESET	0x3FFF2FFF
55*4882a593Smuzhiyun 
56*4882a593Smuzhiyun /* Watchdog max counter value in ticks */
57*4882a593Smuzhiyun #define WDT_COUNTER_MAX_TICKS	0xFFF
58*4882a593Smuzhiyun 
59*4882a593Smuzhiyun /* Watchdog max delta/value in secs */
60*4882a593Smuzhiyun #define WDT_COUNTER_MAX_SECS	ticks_to_secs(WDT_COUNTER_MAX_TICKS)
61*4882a593Smuzhiyun 
62*4882a593Smuzhiyun /* Hardware timeout in seconds */
63*4882a593Smuzhiyun #define WDT_HW_TIMEOUT 2
64*4882a593Smuzhiyun 
65*4882a593Smuzhiyun /* Timer heartbeat (500ms) */
66*4882a593Smuzhiyun #define WDT_TIMEOUT	(HZ/2)
67*4882a593Smuzhiyun 
68*4882a593Smuzhiyun /* User land timeout */
69*4882a593Smuzhiyun #define WDT_HEARTBEAT 15
70*4882a593Smuzhiyun static int heartbeat;
71*4882a593Smuzhiyun module_param(heartbeat, int, 0);
72*4882a593Smuzhiyun MODULE_PARM_DESC(heartbeat, "Watchdog heartbeats in seconds. "
73*4882a593Smuzhiyun 	"(default = " __MODULE_STRING(WDT_HEARTBEAT) ")");
74*4882a593Smuzhiyun 
75*4882a593Smuzhiyun static bool nowayout = WATCHDOG_NOWAYOUT;
76*4882a593Smuzhiyun module_param(nowayout, bool, 0);
77*4882a593Smuzhiyun MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started "
78*4882a593Smuzhiyun 	"(default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
79*4882a593Smuzhiyun 
80*4882a593Smuzhiyun #define to_wdt(wdd) container_of(wdd, struct at91wdt, wdd)
81*4882a593Smuzhiyun struct at91wdt {
82*4882a593Smuzhiyun 	struct watchdog_device wdd;
83*4882a593Smuzhiyun 	void __iomem *base;
84*4882a593Smuzhiyun 	unsigned long next_heartbeat;	/* the next_heartbeat for the timer */
85*4882a593Smuzhiyun 	struct timer_list timer;	/* The timer that pings the watchdog */
86*4882a593Smuzhiyun 	u32 mr;
87*4882a593Smuzhiyun 	u32 mr_mask;
88*4882a593Smuzhiyun 	unsigned long heartbeat;	/* WDT heartbeat in jiffies */
89*4882a593Smuzhiyun 	bool nowayout;
90*4882a593Smuzhiyun 	unsigned int irq;
91*4882a593Smuzhiyun 	struct clk *sclk;
92*4882a593Smuzhiyun };
93*4882a593Smuzhiyun 
94*4882a593Smuzhiyun /* ......................................................................... */
95*4882a593Smuzhiyun 
wdt_interrupt(int irq,void * dev_id)96*4882a593Smuzhiyun static irqreturn_t wdt_interrupt(int irq, void *dev_id)
97*4882a593Smuzhiyun {
98*4882a593Smuzhiyun 	struct at91wdt *wdt = (struct at91wdt *)dev_id;
99*4882a593Smuzhiyun 
100*4882a593Smuzhiyun 	if (wdt_read(wdt, AT91_WDT_SR)) {
101*4882a593Smuzhiyun 		pr_crit("at91sam9 WDT software reset\n");
102*4882a593Smuzhiyun 		emergency_restart();
103*4882a593Smuzhiyun 		pr_crit("Reboot didn't ?????\n");
104*4882a593Smuzhiyun 	}
105*4882a593Smuzhiyun 
106*4882a593Smuzhiyun 	return IRQ_HANDLED;
107*4882a593Smuzhiyun }
108*4882a593Smuzhiyun 
109*4882a593Smuzhiyun /*
110*4882a593Smuzhiyun  * Reload the watchdog timer.  (ie, pat the watchdog)
111*4882a593Smuzhiyun  */
at91_wdt_reset(struct at91wdt * wdt)112*4882a593Smuzhiyun static inline void at91_wdt_reset(struct at91wdt *wdt)
113*4882a593Smuzhiyun {
114*4882a593Smuzhiyun 	wdt_write(wdt, AT91_WDT_CR, AT91_WDT_KEY | AT91_WDT_WDRSTT);
115*4882a593Smuzhiyun }
116*4882a593Smuzhiyun 
117*4882a593Smuzhiyun /*
118*4882a593Smuzhiyun  * Timer tick
119*4882a593Smuzhiyun  */
at91_ping(struct timer_list * t)120*4882a593Smuzhiyun static void at91_ping(struct timer_list *t)
121*4882a593Smuzhiyun {
122*4882a593Smuzhiyun 	struct at91wdt *wdt = from_timer(wdt, t, timer);
123*4882a593Smuzhiyun 	if (time_before(jiffies, wdt->next_heartbeat) ||
124*4882a593Smuzhiyun 	    !watchdog_active(&wdt->wdd)) {
125*4882a593Smuzhiyun 		at91_wdt_reset(wdt);
126*4882a593Smuzhiyun 		mod_timer(&wdt->timer, jiffies + wdt->heartbeat);
127*4882a593Smuzhiyun 	} else {
128*4882a593Smuzhiyun 		pr_crit("I will reset your machine !\n");
129*4882a593Smuzhiyun 	}
130*4882a593Smuzhiyun }
131*4882a593Smuzhiyun 
at91_wdt_start(struct watchdog_device * wdd)132*4882a593Smuzhiyun static int at91_wdt_start(struct watchdog_device *wdd)
133*4882a593Smuzhiyun {
134*4882a593Smuzhiyun 	struct at91wdt *wdt = to_wdt(wdd);
135*4882a593Smuzhiyun 	/* calculate when the next userspace timeout will be */
136*4882a593Smuzhiyun 	wdt->next_heartbeat = jiffies + wdd->timeout * HZ;
137*4882a593Smuzhiyun 	return 0;
138*4882a593Smuzhiyun }
139*4882a593Smuzhiyun 
at91_wdt_stop(struct watchdog_device * wdd)140*4882a593Smuzhiyun static int at91_wdt_stop(struct watchdog_device *wdd)
141*4882a593Smuzhiyun {
142*4882a593Smuzhiyun 	/* The watchdog timer hardware can not be stopped... */
143*4882a593Smuzhiyun 	return 0;
144*4882a593Smuzhiyun }
145*4882a593Smuzhiyun 
at91_wdt_set_timeout(struct watchdog_device * wdd,unsigned int new_timeout)146*4882a593Smuzhiyun static int at91_wdt_set_timeout(struct watchdog_device *wdd, unsigned int new_timeout)
147*4882a593Smuzhiyun {
148*4882a593Smuzhiyun 	wdd->timeout = new_timeout;
149*4882a593Smuzhiyun 	return at91_wdt_start(wdd);
150*4882a593Smuzhiyun }
151*4882a593Smuzhiyun 
at91_wdt_init(struct platform_device * pdev,struct at91wdt * wdt)152*4882a593Smuzhiyun static int at91_wdt_init(struct platform_device *pdev, struct at91wdt *wdt)
153*4882a593Smuzhiyun {
154*4882a593Smuzhiyun 	u32 tmp;
155*4882a593Smuzhiyun 	u32 delta;
156*4882a593Smuzhiyun 	u32 value;
157*4882a593Smuzhiyun 	int err;
158*4882a593Smuzhiyun 	u32 mask = wdt->mr_mask;
159*4882a593Smuzhiyun 	unsigned long min_heartbeat = 1;
160*4882a593Smuzhiyun 	unsigned long max_heartbeat;
161*4882a593Smuzhiyun 	struct device *dev = &pdev->dev;
162*4882a593Smuzhiyun 
163*4882a593Smuzhiyun 	tmp = wdt_read(wdt, AT91_WDT_MR);
164*4882a593Smuzhiyun 	if ((tmp & mask) != (wdt->mr & mask)) {
165*4882a593Smuzhiyun 		if (tmp == WDT_MR_RESET) {
166*4882a593Smuzhiyun 			wdt_write(wdt, AT91_WDT_MR, wdt->mr);
167*4882a593Smuzhiyun 			tmp = wdt_read(wdt, AT91_WDT_MR);
168*4882a593Smuzhiyun 		}
169*4882a593Smuzhiyun 	}
170*4882a593Smuzhiyun 
171*4882a593Smuzhiyun 	if (tmp & AT91_WDT_WDDIS) {
172*4882a593Smuzhiyun 		if (wdt->mr & AT91_WDT_WDDIS)
173*4882a593Smuzhiyun 			return 0;
174*4882a593Smuzhiyun 		dev_err(dev, "watchdog is disabled\n");
175*4882a593Smuzhiyun 		return -EINVAL;
176*4882a593Smuzhiyun 	}
177*4882a593Smuzhiyun 
178*4882a593Smuzhiyun 	value = tmp & AT91_WDT_WDV;
179*4882a593Smuzhiyun 	delta = (tmp & AT91_WDT_WDD) >> 16;
180*4882a593Smuzhiyun 
181*4882a593Smuzhiyun 	if (delta < value)
182*4882a593Smuzhiyun 		min_heartbeat = ticks_to_hz_roundup(value - delta);
183*4882a593Smuzhiyun 
184*4882a593Smuzhiyun 	max_heartbeat = ticks_to_hz_rounddown(value);
185*4882a593Smuzhiyun 	if (!max_heartbeat) {
186*4882a593Smuzhiyun 		dev_err(dev,
187*4882a593Smuzhiyun 			"heartbeat is too small for the system to handle it correctly\n");
188*4882a593Smuzhiyun 		return -EINVAL;
189*4882a593Smuzhiyun 	}
190*4882a593Smuzhiyun 
191*4882a593Smuzhiyun 	/*
192*4882a593Smuzhiyun 	 * Try to reset the watchdog counter 4 or 2 times more often than
193*4882a593Smuzhiyun 	 * actually requested, to avoid spurious watchdog reset.
194*4882a593Smuzhiyun 	 * If this is not possible because of the min_heartbeat value, reset
195*4882a593Smuzhiyun 	 * it at the min_heartbeat period.
196*4882a593Smuzhiyun 	 */
197*4882a593Smuzhiyun 	if ((max_heartbeat / 4) >= min_heartbeat)
198*4882a593Smuzhiyun 		wdt->heartbeat = max_heartbeat / 4;
199*4882a593Smuzhiyun 	else if ((max_heartbeat / 2) >= min_heartbeat)
200*4882a593Smuzhiyun 		wdt->heartbeat = max_heartbeat / 2;
201*4882a593Smuzhiyun 	else
202*4882a593Smuzhiyun 		wdt->heartbeat = min_heartbeat;
203*4882a593Smuzhiyun 
204*4882a593Smuzhiyun 	if (max_heartbeat < min_heartbeat + 4)
205*4882a593Smuzhiyun 		dev_warn(dev,
206*4882a593Smuzhiyun 			 "min heartbeat and max heartbeat might be too close for the system to handle it correctly\n");
207*4882a593Smuzhiyun 
208*4882a593Smuzhiyun 	if ((tmp & AT91_WDT_WDFIEN) && wdt->irq) {
209*4882a593Smuzhiyun 		err = request_irq(wdt->irq, wdt_interrupt,
210*4882a593Smuzhiyun 				  IRQF_SHARED | IRQF_IRQPOLL |
211*4882a593Smuzhiyun 				  IRQF_NO_SUSPEND,
212*4882a593Smuzhiyun 				  pdev->name, wdt);
213*4882a593Smuzhiyun 		if (err)
214*4882a593Smuzhiyun 			return err;
215*4882a593Smuzhiyun 	}
216*4882a593Smuzhiyun 
217*4882a593Smuzhiyun 	if ((tmp & wdt->mr_mask) != (wdt->mr & wdt->mr_mask))
218*4882a593Smuzhiyun 		dev_warn(dev,
219*4882a593Smuzhiyun 			 "watchdog already configured differently (mr = %x expecting %x)\n",
220*4882a593Smuzhiyun 			 tmp & wdt->mr_mask, wdt->mr & wdt->mr_mask);
221*4882a593Smuzhiyun 
222*4882a593Smuzhiyun 	timer_setup(&wdt->timer, at91_ping, 0);
223*4882a593Smuzhiyun 
224*4882a593Smuzhiyun 	/*
225*4882a593Smuzhiyun 	 * Use min_heartbeat the first time to avoid spurious watchdog reset:
226*4882a593Smuzhiyun 	 * we don't know for how long the watchdog counter is running, and
227*4882a593Smuzhiyun 	 *  - resetting it right now might trigger a watchdog fault reset
228*4882a593Smuzhiyun 	 *  - waiting for heartbeat time might lead to a watchdog timeout
229*4882a593Smuzhiyun 	 *    reset
230*4882a593Smuzhiyun 	 */
231*4882a593Smuzhiyun 	mod_timer(&wdt->timer, jiffies + min_heartbeat);
232*4882a593Smuzhiyun 
233*4882a593Smuzhiyun 	/* Try to set timeout from device tree first */
234*4882a593Smuzhiyun 	if (watchdog_init_timeout(&wdt->wdd, 0, dev))
235*4882a593Smuzhiyun 		watchdog_init_timeout(&wdt->wdd, heartbeat, dev);
236*4882a593Smuzhiyun 	watchdog_set_nowayout(&wdt->wdd, wdt->nowayout);
237*4882a593Smuzhiyun 	err = watchdog_register_device(&wdt->wdd);
238*4882a593Smuzhiyun 	if (err)
239*4882a593Smuzhiyun 		goto out_stop_timer;
240*4882a593Smuzhiyun 
241*4882a593Smuzhiyun 	wdt->next_heartbeat = jiffies + wdt->wdd.timeout * HZ;
242*4882a593Smuzhiyun 
243*4882a593Smuzhiyun 	return 0;
244*4882a593Smuzhiyun 
245*4882a593Smuzhiyun out_stop_timer:
246*4882a593Smuzhiyun 	del_timer(&wdt->timer);
247*4882a593Smuzhiyun 	return err;
248*4882a593Smuzhiyun }
249*4882a593Smuzhiyun 
250*4882a593Smuzhiyun /* ......................................................................... */
251*4882a593Smuzhiyun 
252*4882a593Smuzhiyun static const struct watchdog_info at91_wdt_info = {
253*4882a593Smuzhiyun 	.identity	= DRV_NAME,
254*4882a593Smuzhiyun 	.options	= WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING |
255*4882a593Smuzhiyun 						WDIOF_MAGICCLOSE,
256*4882a593Smuzhiyun };
257*4882a593Smuzhiyun 
258*4882a593Smuzhiyun static const struct watchdog_ops at91_wdt_ops = {
259*4882a593Smuzhiyun 	.owner =	THIS_MODULE,
260*4882a593Smuzhiyun 	.start =	at91_wdt_start,
261*4882a593Smuzhiyun 	.stop =		at91_wdt_stop,
262*4882a593Smuzhiyun 	.set_timeout =	at91_wdt_set_timeout,
263*4882a593Smuzhiyun };
264*4882a593Smuzhiyun 
265*4882a593Smuzhiyun #if defined(CONFIG_OF)
of_at91wdt_init(struct device_node * np,struct at91wdt * wdt)266*4882a593Smuzhiyun static int of_at91wdt_init(struct device_node *np, struct at91wdt *wdt)
267*4882a593Smuzhiyun {
268*4882a593Smuzhiyun 	u32 min = 0;
269*4882a593Smuzhiyun 	u32 max = WDT_COUNTER_MAX_SECS;
270*4882a593Smuzhiyun 	const char *tmp;
271*4882a593Smuzhiyun 
272*4882a593Smuzhiyun 	/* Get the interrupts property */
273*4882a593Smuzhiyun 	wdt->irq = irq_of_parse_and_map(np, 0);
274*4882a593Smuzhiyun 	if (!wdt->irq)
275*4882a593Smuzhiyun 		dev_warn(wdt->wdd.parent, "failed to get IRQ from DT\n");
276*4882a593Smuzhiyun 
277*4882a593Smuzhiyun 	if (!of_property_read_u32_index(np, "atmel,max-heartbeat-sec", 0,
278*4882a593Smuzhiyun 					&max)) {
279*4882a593Smuzhiyun 		if (!max || max > WDT_COUNTER_MAX_SECS)
280*4882a593Smuzhiyun 			max = WDT_COUNTER_MAX_SECS;
281*4882a593Smuzhiyun 
282*4882a593Smuzhiyun 		if (!of_property_read_u32_index(np, "atmel,min-heartbeat-sec",
283*4882a593Smuzhiyun 						0, &min)) {
284*4882a593Smuzhiyun 			if (min >= max)
285*4882a593Smuzhiyun 				min = max - 1;
286*4882a593Smuzhiyun 		}
287*4882a593Smuzhiyun 	}
288*4882a593Smuzhiyun 
289*4882a593Smuzhiyun 	min = secs_to_ticks(min);
290*4882a593Smuzhiyun 	max = secs_to_ticks(max);
291*4882a593Smuzhiyun 
292*4882a593Smuzhiyun 	wdt->mr_mask = 0x3FFFFFFF;
293*4882a593Smuzhiyun 	wdt->mr = 0;
294*4882a593Smuzhiyun 	if (!of_property_read_string(np, "atmel,watchdog-type", &tmp) &&
295*4882a593Smuzhiyun 	    !strcmp(tmp, "software")) {
296*4882a593Smuzhiyun 		wdt->mr |= AT91_WDT_WDFIEN;
297*4882a593Smuzhiyun 		wdt->mr_mask &= ~AT91_WDT_WDRPROC;
298*4882a593Smuzhiyun 	} else {
299*4882a593Smuzhiyun 		wdt->mr |= AT91_WDT_WDRSTEN;
300*4882a593Smuzhiyun 	}
301*4882a593Smuzhiyun 
302*4882a593Smuzhiyun 	if (!of_property_read_string(np, "atmel,reset-type", &tmp) &&
303*4882a593Smuzhiyun 	    !strcmp(tmp, "proc"))
304*4882a593Smuzhiyun 		wdt->mr |= AT91_WDT_WDRPROC;
305*4882a593Smuzhiyun 
306*4882a593Smuzhiyun 	if (of_property_read_bool(np, "atmel,disable")) {
307*4882a593Smuzhiyun 		wdt->mr |= AT91_WDT_WDDIS;
308*4882a593Smuzhiyun 		wdt->mr_mask &= AT91_WDT_WDDIS;
309*4882a593Smuzhiyun 	}
310*4882a593Smuzhiyun 
311*4882a593Smuzhiyun 	if (of_property_read_bool(np, "atmel,idle-halt"))
312*4882a593Smuzhiyun 		wdt->mr |= AT91_WDT_WDIDLEHLT;
313*4882a593Smuzhiyun 
314*4882a593Smuzhiyun 	if (of_property_read_bool(np, "atmel,dbg-halt"))
315*4882a593Smuzhiyun 		wdt->mr |= AT91_WDT_WDDBGHLT;
316*4882a593Smuzhiyun 
317*4882a593Smuzhiyun 	wdt->mr |= max | ((max - min) << 16);
318*4882a593Smuzhiyun 
319*4882a593Smuzhiyun 	return 0;
320*4882a593Smuzhiyun }
321*4882a593Smuzhiyun #else
of_at91wdt_init(struct device_node * np,struct at91wdt * wdt)322*4882a593Smuzhiyun static inline int of_at91wdt_init(struct device_node *np, struct at91wdt *wdt)
323*4882a593Smuzhiyun {
324*4882a593Smuzhiyun 	return 0;
325*4882a593Smuzhiyun }
326*4882a593Smuzhiyun #endif
327*4882a593Smuzhiyun 
at91wdt_probe(struct platform_device * pdev)328*4882a593Smuzhiyun static int __init at91wdt_probe(struct platform_device *pdev)
329*4882a593Smuzhiyun {
330*4882a593Smuzhiyun 	int err;
331*4882a593Smuzhiyun 	struct at91wdt *wdt;
332*4882a593Smuzhiyun 
333*4882a593Smuzhiyun 	wdt = devm_kzalloc(&pdev->dev, sizeof(*wdt), GFP_KERNEL);
334*4882a593Smuzhiyun 	if (!wdt)
335*4882a593Smuzhiyun 		return -ENOMEM;
336*4882a593Smuzhiyun 
337*4882a593Smuzhiyun 	wdt->mr = (WDT_HW_TIMEOUT * 256) | AT91_WDT_WDRSTEN | AT91_WDT_WDD |
338*4882a593Smuzhiyun 		  AT91_WDT_WDDBGHLT | AT91_WDT_WDIDLEHLT;
339*4882a593Smuzhiyun 	wdt->mr_mask = 0x3FFFFFFF;
340*4882a593Smuzhiyun 	wdt->nowayout = nowayout;
341*4882a593Smuzhiyun 	wdt->wdd.parent = &pdev->dev;
342*4882a593Smuzhiyun 	wdt->wdd.info = &at91_wdt_info;
343*4882a593Smuzhiyun 	wdt->wdd.ops = &at91_wdt_ops;
344*4882a593Smuzhiyun 	wdt->wdd.timeout = WDT_HEARTBEAT;
345*4882a593Smuzhiyun 	wdt->wdd.min_timeout = 1;
346*4882a593Smuzhiyun 	wdt->wdd.max_timeout = 0xFFFF;
347*4882a593Smuzhiyun 
348*4882a593Smuzhiyun 	wdt->base = devm_platform_ioremap_resource(pdev, 0);
349*4882a593Smuzhiyun 	if (IS_ERR(wdt->base))
350*4882a593Smuzhiyun 		return PTR_ERR(wdt->base);
351*4882a593Smuzhiyun 
352*4882a593Smuzhiyun 	wdt->sclk = devm_clk_get(&pdev->dev, NULL);
353*4882a593Smuzhiyun 	if (IS_ERR(wdt->sclk))
354*4882a593Smuzhiyun 		return PTR_ERR(wdt->sclk);
355*4882a593Smuzhiyun 
356*4882a593Smuzhiyun 	err = clk_prepare_enable(wdt->sclk);
357*4882a593Smuzhiyun 	if (err) {
358*4882a593Smuzhiyun 		dev_err(&pdev->dev, "Could not enable slow clock\n");
359*4882a593Smuzhiyun 		return err;
360*4882a593Smuzhiyun 	}
361*4882a593Smuzhiyun 
362*4882a593Smuzhiyun 	if (pdev->dev.of_node) {
363*4882a593Smuzhiyun 		err = of_at91wdt_init(pdev->dev.of_node, wdt);
364*4882a593Smuzhiyun 		if (err)
365*4882a593Smuzhiyun 			goto err_clk;
366*4882a593Smuzhiyun 	}
367*4882a593Smuzhiyun 
368*4882a593Smuzhiyun 	err = at91_wdt_init(pdev, wdt);
369*4882a593Smuzhiyun 	if (err)
370*4882a593Smuzhiyun 		goto err_clk;
371*4882a593Smuzhiyun 
372*4882a593Smuzhiyun 	platform_set_drvdata(pdev, wdt);
373*4882a593Smuzhiyun 
374*4882a593Smuzhiyun 	pr_info("enabled (heartbeat=%d sec, nowayout=%d)\n",
375*4882a593Smuzhiyun 		wdt->wdd.timeout, wdt->nowayout);
376*4882a593Smuzhiyun 
377*4882a593Smuzhiyun 	return 0;
378*4882a593Smuzhiyun 
379*4882a593Smuzhiyun err_clk:
380*4882a593Smuzhiyun 	clk_disable_unprepare(wdt->sclk);
381*4882a593Smuzhiyun 
382*4882a593Smuzhiyun 	return err;
383*4882a593Smuzhiyun }
384*4882a593Smuzhiyun 
at91wdt_remove(struct platform_device * pdev)385*4882a593Smuzhiyun static int __exit at91wdt_remove(struct platform_device *pdev)
386*4882a593Smuzhiyun {
387*4882a593Smuzhiyun 	struct at91wdt *wdt = platform_get_drvdata(pdev);
388*4882a593Smuzhiyun 	watchdog_unregister_device(&wdt->wdd);
389*4882a593Smuzhiyun 
390*4882a593Smuzhiyun 	pr_warn("I quit now, hardware will probably reboot!\n");
391*4882a593Smuzhiyun 	del_timer(&wdt->timer);
392*4882a593Smuzhiyun 	clk_disable_unprepare(wdt->sclk);
393*4882a593Smuzhiyun 
394*4882a593Smuzhiyun 	return 0;
395*4882a593Smuzhiyun }
396*4882a593Smuzhiyun 
397*4882a593Smuzhiyun #if defined(CONFIG_OF)
398*4882a593Smuzhiyun static const struct of_device_id at91_wdt_dt_ids[] = {
399*4882a593Smuzhiyun 	{ .compatible = "atmel,at91sam9260-wdt" },
400*4882a593Smuzhiyun 	{ /* sentinel */ }
401*4882a593Smuzhiyun };
402*4882a593Smuzhiyun 
403*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, at91_wdt_dt_ids);
404*4882a593Smuzhiyun #endif
405*4882a593Smuzhiyun 
406*4882a593Smuzhiyun static struct platform_driver at91wdt_driver = {
407*4882a593Smuzhiyun 	.remove		= __exit_p(at91wdt_remove),
408*4882a593Smuzhiyun 	.driver		= {
409*4882a593Smuzhiyun 		.name	= "at91_wdt",
410*4882a593Smuzhiyun 		.of_match_table = of_match_ptr(at91_wdt_dt_ids),
411*4882a593Smuzhiyun 	},
412*4882a593Smuzhiyun };
413*4882a593Smuzhiyun 
414*4882a593Smuzhiyun module_platform_driver_probe(at91wdt_driver, at91wdt_probe);
415*4882a593Smuzhiyun 
416*4882a593Smuzhiyun MODULE_AUTHOR("Renaud CERRATO <r.cerrato@til-technologies.fr>");
417*4882a593Smuzhiyun MODULE_DESCRIPTION("Watchdog driver for Atmel AT91SAM9x processors");
418*4882a593Smuzhiyun MODULE_LICENSE("GPL");
419