xref: /OK3568_Linux_fs/kernel/drivers/w1/slaves/w1_ds28e17.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  *	w1_ds28e17.c - w1 family 19 (DS28E17) driver
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Copyright (c) 2016 Jan Kandziora <jjj@gmx.de>
6*4882a593Smuzhiyun  */
7*4882a593Smuzhiyun 
8*4882a593Smuzhiyun #include <linux/crc16.h>
9*4882a593Smuzhiyun #include <linux/delay.h>
10*4882a593Smuzhiyun #include <linux/device.h>
11*4882a593Smuzhiyun #include <linux/i2c.h>
12*4882a593Smuzhiyun #include <linux/kernel.h>
13*4882a593Smuzhiyun #include <linux/module.h>
14*4882a593Smuzhiyun #include <linux/moduleparam.h>
15*4882a593Smuzhiyun #include <linux/slab.h>
16*4882a593Smuzhiyun #include <linux/types.h>
17*4882a593Smuzhiyun #include <linux/uaccess.h>
18*4882a593Smuzhiyun 
19*4882a593Smuzhiyun #define CRC16_INIT 0
20*4882a593Smuzhiyun 
21*4882a593Smuzhiyun #include <linux/w1.h>
22*4882a593Smuzhiyun 
23*4882a593Smuzhiyun #define W1_FAMILY_DS28E17 0x19
24*4882a593Smuzhiyun 
25*4882a593Smuzhiyun /* Module setup. */
26*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
27*4882a593Smuzhiyun MODULE_AUTHOR("Jan Kandziora <jjj@gmx.de>");
28*4882a593Smuzhiyun MODULE_DESCRIPTION("w1 family 19 driver for DS28E17, 1-wire to I2C master bridge");
29*4882a593Smuzhiyun MODULE_ALIAS("w1-family-" __stringify(W1_FAMILY_DS28E17));
30*4882a593Smuzhiyun 
31*4882a593Smuzhiyun 
32*4882a593Smuzhiyun /* Default I2C speed to be set when a DS28E17 is detected. */
33*4882a593Smuzhiyun static int i2c_speed = 100;
34*4882a593Smuzhiyun module_param_named(speed, i2c_speed, int, (S_IRUSR | S_IWUSR));
35*4882a593Smuzhiyun MODULE_PARM_DESC(speed, "Default I2C speed to be set when a DS28E17 is detected");
36*4882a593Smuzhiyun 
37*4882a593Smuzhiyun /* Default I2C stretch value to be set when a DS28E17 is detected. */
38*4882a593Smuzhiyun static char i2c_stretch = 1;
39*4882a593Smuzhiyun module_param_named(stretch, i2c_stretch, byte, (S_IRUSR | S_IWUSR));
40*4882a593Smuzhiyun MODULE_PARM_DESC(stretch, "Default I2C stretch value to be set when a DS28E17 is detected");
41*4882a593Smuzhiyun 
42*4882a593Smuzhiyun /* DS28E17 device command codes. */
43*4882a593Smuzhiyun #define W1_F19_WRITE_DATA_WITH_STOP      0x4B
44*4882a593Smuzhiyun #define W1_F19_WRITE_DATA_NO_STOP        0x5A
45*4882a593Smuzhiyun #define W1_F19_WRITE_DATA_ONLY           0x69
46*4882a593Smuzhiyun #define W1_F19_WRITE_DATA_ONLY_WITH_STOP 0x78
47*4882a593Smuzhiyun #define W1_F19_READ_DATA_WITH_STOP       0x87
48*4882a593Smuzhiyun #define W1_F19_WRITE_READ_DATA_WITH_STOP 0x2D
49*4882a593Smuzhiyun #define W1_F19_WRITE_CONFIGURATION       0xD2
50*4882a593Smuzhiyun #define W1_F19_READ_CONFIGURATION        0xE1
51*4882a593Smuzhiyun #define W1_F19_ENABLE_SLEEP_MODE         0x1E
52*4882a593Smuzhiyun #define W1_F19_READ_DEVICE_REVISION      0xC4
53*4882a593Smuzhiyun 
54*4882a593Smuzhiyun /* DS28E17 status bits */
55*4882a593Smuzhiyun #define W1_F19_STATUS_CRC     0x01
56*4882a593Smuzhiyun #define W1_F19_STATUS_ADDRESS 0x02
57*4882a593Smuzhiyun #define W1_F19_STATUS_START   0x08
58*4882a593Smuzhiyun 
59*4882a593Smuzhiyun /*
60*4882a593Smuzhiyun  * Maximum number of I2C bytes to transfer within one CRC16 protected onewire
61*4882a593Smuzhiyun  * command.
62*4882a593Smuzhiyun  * */
63*4882a593Smuzhiyun #define W1_F19_WRITE_DATA_LIMIT 255
64*4882a593Smuzhiyun 
65*4882a593Smuzhiyun /* Maximum number of I2C bytes to read with one onewire command. */
66*4882a593Smuzhiyun #define W1_F19_READ_DATA_LIMIT 255
67*4882a593Smuzhiyun 
68*4882a593Smuzhiyun /* Constants for calculating the busy sleep. */
69*4882a593Smuzhiyun #define W1_F19_BUSY_TIMEBASES { 90, 23, 10 }
70*4882a593Smuzhiyun #define W1_F19_BUSY_GRATUITY  1000
71*4882a593Smuzhiyun 
72*4882a593Smuzhiyun /* Number of checks for the busy flag before timeout. */
73*4882a593Smuzhiyun #define W1_F19_BUSY_CHECKS 1000
74*4882a593Smuzhiyun 
75*4882a593Smuzhiyun 
76*4882a593Smuzhiyun /* Slave specific data. */
77*4882a593Smuzhiyun struct w1_f19_data {
78*4882a593Smuzhiyun 	u8 speed;
79*4882a593Smuzhiyun 	u8 stretch;
80*4882a593Smuzhiyun 	struct i2c_adapter adapter;
81*4882a593Smuzhiyun };
82*4882a593Smuzhiyun 
83*4882a593Smuzhiyun 
84*4882a593Smuzhiyun /* Wait a while until the busy flag clears. */
w1_f19_i2c_busy_wait(struct w1_slave * sl,size_t count)85*4882a593Smuzhiyun static int w1_f19_i2c_busy_wait(struct w1_slave *sl, size_t count)
86*4882a593Smuzhiyun {
87*4882a593Smuzhiyun 	const unsigned long timebases[3] = W1_F19_BUSY_TIMEBASES;
88*4882a593Smuzhiyun 	struct w1_f19_data *data = sl->family_data;
89*4882a593Smuzhiyun 	unsigned int checks;
90*4882a593Smuzhiyun 
91*4882a593Smuzhiyun 	/* Check the busy flag first in any case.*/
92*4882a593Smuzhiyun 	if (w1_touch_bit(sl->master, 1) == 0)
93*4882a593Smuzhiyun 		return 0;
94*4882a593Smuzhiyun 
95*4882a593Smuzhiyun 	/*
96*4882a593Smuzhiyun 	 * Do a generously long sleep in the beginning,
97*4882a593Smuzhiyun 	 * as we have to wait at least this time for all
98*4882a593Smuzhiyun 	 * the I2C bytes at the given speed to be transferred.
99*4882a593Smuzhiyun 	 */
100*4882a593Smuzhiyun 	usleep_range(timebases[data->speed] * (data->stretch) * count,
101*4882a593Smuzhiyun 		timebases[data->speed] * (data->stretch) * count
102*4882a593Smuzhiyun 		+ W1_F19_BUSY_GRATUITY);
103*4882a593Smuzhiyun 
104*4882a593Smuzhiyun 	/* Now continusly check the busy flag sent by the DS28E17. */
105*4882a593Smuzhiyun 	checks = W1_F19_BUSY_CHECKS;
106*4882a593Smuzhiyun 	while ((checks--) > 0) {
107*4882a593Smuzhiyun 		/* Return success if the busy flag is cleared. */
108*4882a593Smuzhiyun 		if (w1_touch_bit(sl->master, 1) == 0)
109*4882a593Smuzhiyun 			return 0;
110*4882a593Smuzhiyun 
111*4882a593Smuzhiyun 		/* Wait one non-streched byte timeslot. */
112*4882a593Smuzhiyun 		udelay(timebases[data->speed]);
113*4882a593Smuzhiyun 	}
114*4882a593Smuzhiyun 
115*4882a593Smuzhiyun 	/* Timeout. */
116*4882a593Smuzhiyun 	dev_warn(&sl->dev, "busy timeout\n");
117*4882a593Smuzhiyun 	return -ETIMEDOUT;
118*4882a593Smuzhiyun }
119*4882a593Smuzhiyun 
120*4882a593Smuzhiyun 
121*4882a593Smuzhiyun /* Utility function: result. */
w1_f19_error(struct w1_slave * sl,u8 w1_buf[])122*4882a593Smuzhiyun static size_t w1_f19_error(struct w1_slave *sl, u8 w1_buf[])
123*4882a593Smuzhiyun {
124*4882a593Smuzhiyun 	/* Warnings. */
125*4882a593Smuzhiyun 	if (w1_buf[0] & W1_F19_STATUS_CRC)
126*4882a593Smuzhiyun 		dev_warn(&sl->dev, "crc16 mismatch\n");
127*4882a593Smuzhiyun 	if (w1_buf[0] & W1_F19_STATUS_ADDRESS)
128*4882a593Smuzhiyun 		dev_warn(&sl->dev, "i2c device not responding\n");
129*4882a593Smuzhiyun 	if ((w1_buf[0] & (W1_F19_STATUS_CRC | W1_F19_STATUS_ADDRESS)) == 0
130*4882a593Smuzhiyun 			&& w1_buf[1] != 0) {
131*4882a593Smuzhiyun 		dev_warn(&sl->dev, "i2c short write, %d bytes not acknowledged\n",
132*4882a593Smuzhiyun 			w1_buf[1]);
133*4882a593Smuzhiyun 	}
134*4882a593Smuzhiyun 
135*4882a593Smuzhiyun 	/* Check error conditions. */
136*4882a593Smuzhiyun 	if (w1_buf[0] & W1_F19_STATUS_ADDRESS)
137*4882a593Smuzhiyun 		return -ENXIO;
138*4882a593Smuzhiyun 	if (w1_buf[0] & W1_F19_STATUS_START)
139*4882a593Smuzhiyun 		return -EAGAIN;
140*4882a593Smuzhiyun 	if (w1_buf[0] != 0 || w1_buf[1] != 0)
141*4882a593Smuzhiyun 		return -EIO;
142*4882a593Smuzhiyun 
143*4882a593Smuzhiyun 	/* All ok. */
144*4882a593Smuzhiyun 	return 0;
145*4882a593Smuzhiyun }
146*4882a593Smuzhiyun 
147*4882a593Smuzhiyun 
148*4882a593Smuzhiyun /* Utility function: write data to I2C slave, single chunk. */
__w1_f19_i2c_write(struct w1_slave * sl,const u8 * command,size_t command_count,const u8 * buffer,size_t count)149*4882a593Smuzhiyun static int __w1_f19_i2c_write(struct w1_slave *sl,
150*4882a593Smuzhiyun 	const u8 *command, size_t command_count,
151*4882a593Smuzhiyun 	const u8 *buffer, size_t count)
152*4882a593Smuzhiyun {
153*4882a593Smuzhiyun 	u16 crc;
154*4882a593Smuzhiyun 	int error;
155*4882a593Smuzhiyun 	u8 w1_buf[2];
156*4882a593Smuzhiyun 
157*4882a593Smuzhiyun 	/* Send command and I2C data to DS28E17. */
158*4882a593Smuzhiyun 	crc = crc16(CRC16_INIT, command, command_count);
159*4882a593Smuzhiyun 	w1_write_block(sl->master, command, command_count);
160*4882a593Smuzhiyun 
161*4882a593Smuzhiyun 	w1_buf[0] = count;
162*4882a593Smuzhiyun 	crc = crc16(crc, w1_buf, 1);
163*4882a593Smuzhiyun 	w1_write_8(sl->master, w1_buf[0]);
164*4882a593Smuzhiyun 
165*4882a593Smuzhiyun 	crc = crc16(crc, buffer, count);
166*4882a593Smuzhiyun 	w1_write_block(sl->master, buffer, count);
167*4882a593Smuzhiyun 
168*4882a593Smuzhiyun 	w1_buf[0] = ~(crc & 0xFF);
169*4882a593Smuzhiyun 	w1_buf[1] = ~((crc >> 8) & 0xFF);
170*4882a593Smuzhiyun 	w1_write_block(sl->master, w1_buf, 2);
171*4882a593Smuzhiyun 
172*4882a593Smuzhiyun 	/* Wait until busy flag clears (or timeout). */
173*4882a593Smuzhiyun 	if (w1_f19_i2c_busy_wait(sl, count + 1) < 0)
174*4882a593Smuzhiyun 		return -ETIMEDOUT;
175*4882a593Smuzhiyun 
176*4882a593Smuzhiyun 	/* Read status from DS28E17. */
177*4882a593Smuzhiyun 	w1_read_block(sl->master, w1_buf, 2);
178*4882a593Smuzhiyun 
179*4882a593Smuzhiyun 	/* Check error conditions. */
180*4882a593Smuzhiyun 	error = w1_f19_error(sl, w1_buf);
181*4882a593Smuzhiyun 	if (error < 0)
182*4882a593Smuzhiyun 		return error;
183*4882a593Smuzhiyun 
184*4882a593Smuzhiyun 	/* Return number of bytes written. */
185*4882a593Smuzhiyun 	return count;
186*4882a593Smuzhiyun }
187*4882a593Smuzhiyun 
188*4882a593Smuzhiyun 
189*4882a593Smuzhiyun /* Write data to I2C slave. */
w1_f19_i2c_write(struct w1_slave * sl,u16 i2c_address,const u8 * buffer,size_t count,bool stop)190*4882a593Smuzhiyun static int w1_f19_i2c_write(struct w1_slave *sl, u16 i2c_address,
191*4882a593Smuzhiyun 	const u8 *buffer, size_t count, bool stop)
192*4882a593Smuzhiyun {
193*4882a593Smuzhiyun 	int result;
194*4882a593Smuzhiyun 	int remaining = count;
195*4882a593Smuzhiyun 	const u8 *p;
196*4882a593Smuzhiyun 	u8 command[2];
197*4882a593Smuzhiyun 
198*4882a593Smuzhiyun 	/* Check input. */
199*4882a593Smuzhiyun 	if (count == 0)
200*4882a593Smuzhiyun 		return -EOPNOTSUPP;
201*4882a593Smuzhiyun 
202*4882a593Smuzhiyun 	/* Check whether we need multiple commands. */
203*4882a593Smuzhiyun 	if (count <= W1_F19_WRITE_DATA_LIMIT) {
204*4882a593Smuzhiyun 		/*
205*4882a593Smuzhiyun 		 * Small data amount. Data can be sent with
206*4882a593Smuzhiyun 		 * a single onewire command.
207*4882a593Smuzhiyun 		 */
208*4882a593Smuzhiyun 
209*4882a593Smuzhiyun 		/* Send all data to DS28E17. */
210*4882a593Smuzhiyun 		command[0] = (stop ? W1_F19_WRITE_DATA_WITH_STOP
211*4882a593Smuzhiyun 			: W1_F19_WRITE_DATA_NO_STOP);
212*4882a593Smuzhiyun 		command[1] = i2c_address << 1;
213*4882a593Smuzhiyun 		result = __w1_f19_i2c_write(sl, command, 2, buffer, count);
214*4882a593Smuzhiyun 	} else {
215*4882a593Smuzhiyun 		/* Large data amount. Data has to be sent in multiple chunks. */
216*4882a593Smuzhiyun 
217*4882a593Smuzhiyun 		/* Send first chunk to DS28E17. */
218*4882a593Smuzhiyun 		p = buffer;
219*4882a593Smuzhiyun 		command[0] = W1_F19_WRITE_DATA_NO_STOP;
220*4882a593Smuzhiyun 		command[1] = i2c_address << 1;
221*4882a593Smuzhiyun 		result = __w1_f19_i2c_write(sl, command, 2, p,
222*4882a593Smuzhiyun 			W1_F19_WRITE_DATA_LIMIT);
223*4882a593Smuzhiyun 		if (result < 0)
224*4882a593Smuzhiyun 			return result;
225*4882a593Smuzhiyun 
226*4882a593Smuzhiyun 		/* Resume to same DS28E17. */
227*4882a593Smuzhiyun 		if (w1_reset_resume_command(sl->master))
228*4882a593Smuzhiyun 			return -EIO;
229*4882a593Smuzhiyun 
230*4882a593Smuzhiyun 		/* Next data chunk. */
231*4882a593Smuzhiyun 		p += W1_F19_WRITE_DATA_LIMIT;
232*4882a593Smuzhiyun 		remaining -= W1_F19_WRITE_DATA_LIMIT;
233*4882a593Smuzhiyun 
234*4882a593Smuzhiyun 		while (remaining > W1_F19_WRITE_DATA_LIMIT) {
235*4882a593Smuzhiyun 			/* Send intermediate chunk to DS28E17. */
236*4882a593Smuzhiyun 			command[0] = W1_F19_WRITE_DATA_ONLY;
237*4882a593Smuzhiyun 			result = __w1_f19_i2c_write(sl, command, 1, p,
238*4882a593Smuzhiyun 					W1_F19_WRITE_DATA_LIMIT);
239*4882a593Smuzhiyun 			if (result < 0)
240*4882a593Smuzhiyun 				return result;
241*4882a593Smuzhiyun 
242*4882a593Smuzhiyun 			/* Resume to same DS28E17. */
243*4882a593Smuzhiyun 			if (w1_reset_resume_command(sl->master))
244*4882a593Smuzhiyun 				return -EIO;
245*4882a593Smuzhiyun 
246*4882a593Smuzhiyun 			/* Next data chunk. */
247*4882a593Smuzhiyun 			p += W1_F19_WRITE_DATA_LIMIT;
248*4882a593Smuzhiyun 			remaining -= W1_F19_WRITE_DATA_LIMIT;
249*4882a593Smuzhiyun 		}
250*4882a593Smuzhiyun 
251*4882a593Smuzhiyun 		/* Send final chunk to DS28E17. */
252*4882a593Smuzhiyun 		command[0] = (stop ? W1_F19_WRITE_DATA_ONLY_WITH_STOP
253*4882a593Smuzhiyun 			: W1_F19_WRITE_DATA_ONLY);
254*4882a593Smuzhiyun 		result = __w1_f19_i2c_write(sl, command, 1, p, remaining);
255*4882a593Smuzhiyun 	}
256*4882a593Smuzhiyun 
257*4882a593Smuzhiyun 	return result;
258*4882a593Smuzhiyun }
259*4882a593Smuzhiyun 
260*4882a593Smuzhiyun 
261*4882a593Smuzhiyun /* Read data from I2C slave. */
w1_f19_i2c_read(struct w1_slave * sl,u16 i2c_address,u8 * buffer,size_t count)262*4882a593Smuzhiyun static int w1_f19_i2c_read(struct w1_slave *sl, u16 i2c_address,
263*4882a593Smuzhiyun 	u8 *buffer, size_t count)
264*4882a593Smuzhiyun {
265*4882a593Smuzhiyun 	u16 crc;
266*4882a593Smuzhiyun 	int error;
267*4882a593Smuzhiyun 	u8 w1_buf[5];
268*4882a593Smuzhiyun 
269*4882a593Smuzhiyun 	/* Check input. */
270*4882a593Smuzhiyun 	if (count == 0)
271*4882a593Smuzhiyun 		return -EOPNOTSUPP;
272*4882a593Smuzhiyun 
273*4882a593Smuzhiyun 	/* Send command to DS28E17. */
274*4882a593Smuzhiyun 	w1_buf[0] = W1_F19_READ_DATA_WITH_STOP;
275*4882a593Smuzhiyun 	w1_buf[1] = i2c_address << 1 | 0x01;
276*4882a593Smuzhiyun 	w1_buf[2] = count;
277*4882a593Smuzhiyun 	crc = crc16(CRC16_INIT, w1_buf, 3);
278*4882a593Smuzhiyun 	w1_buf[3] = ~(crc & 0xFF);
279*4882a593Smuzhiyun 	w1_buf[4] = ~((crc >> 8) & 0xFF);
280*4882a593Smuzhiyun 	w1_write_block(sl->master, w1_buf, 5);
281*4882a593Smuzhiyun 
282*4882a593Smuzhiyun 	/* Wait until busy flag clears (or timeout). */
283*4882a593Smuzhiyun 	if (w1_f19_i2c_busy_wait(sl, count + 1) < 0)
284*4882a593Smuzhiyun 		return -ETIMEDOUT;
285*4882a593Smuzhiyun 
286*4882a593Smuzhiyun 	/* Read status from DS28E17. */
287*4882a593Smuzhiyun 	w1_buf[0] = w1_read_8(sl->master);
288*4882a593Smuzhiyun 	w1_buf[1] = 0;
289*4882a593Smuzhiyun 
290*4882a593Smuzhiyun 	/* Check error conditions. */
291*4882a593Smuzhiyun 	error = w1_f19_error(sl, w1_buf);
292*4882a593Smuzhiyun 	if (error < 0)
293*4882a593Smuzhiyun 		return error;
294*4882a593Smuzhiyun 
295*4882a593Smuzhiyun 	/* Read received I2C data from DS28E17. */
296*4882a593Smuzhiyun 	return w1_read_block(sl->master, buffer, count);
297*4882a593Smuzhiyun }
298*4882a593Smuzhiyun 
299*4882a593Smuzhiyun 
300*4882a593Smuzhiyun /* Write to, then read data from I2C slave. */
w1_f19_i2c_write_read(struct w1_slave * sl,u16 i2c_address,const u8 * wbuffer,size_t wcount,u8 * rbuffer,size_t rcount)301*4882a593Smuzhiyun static int w1_f19_i2c_write_read(struct w1_slave *sl, u16 i2c_address,
302*4882a593Smuzhiyun 	const u8 *wbuffer, size_t wcount, u8 *rbuffer, size_t rcount)
303*4882a593Smuzhiyun {
304*4882a593Smuzhiyun 	u16 crc;
305*4882a593Smuzhiyun 	int error;
306*4882a593Smuzhiyun 	u8 w1_buf[3];
307*4882a593Smuzhiyun 
308*4882a593Smuzhiyun 	/* Check input. */
309*4882a593Smuzhiyun 	if (wcount == 0 || rcount == 0)
310*4882a593Smuzhiyun 		return -EOPNOTSUPP;
311*4882a593Smuzhiyun 
312*4882a593Smuzhiyun 	/* Send command and I2C data to DS28E17. */
313*4882a593Smuzhiyun 	w1_buf[0] = W1_F19_WRITE_READ_DATA_WITH_STOP;
314*4882a593Smuzhiyun 	w1_buf[1] = i2c_address << 1;
315*4882a593Smuzhiyun 	w1_buf[2] = wcount;
316*4882a593Smuzhiyun 	crc = crc16(CRC16_INIT, w1_buf, 3);
317*4882a593Smuzhiyun 	w1_write_block(sl->master, w1_buf, 3);
318*4882a593Smuzhiyun 
319*4882a593Smuzhiyun 	crc = crc16(crc, wbuffer, wcount);
320*4882a593Smuzhiyun 	w1_write_block(sl->master, wbuffer, wcount);
321*4882a593Smuzhiyun 
322*4882a593Smuzhiyun 	w1_buf[0] = rcount;
323*4882a593Smuzhiyun 	crc = crc16(crc, w1_buf, 1);
324*4882a593Smuzhiyun 	w1_buf[1] = ~(crc & 0xFF);
325*4882a593Smuzhiyun 	w1_buf[2] = ~((crc >> 8) & 0xFF);
326*4882a593Smuzhiyun 	w1_write_block(sl->master, w1_buf, 3);
327*4882a593Smuzhiyun 
328*4882a593Smuzhiyun 	/* Wait until busy flag clears (or timeout). */
329*4882a593Smuzhiyun 	if (w1_f19_i2c_busy_wait(sl, wcount + rcount + 2) < 0)
330*4882a593Smuzhiyun 		return -ETIMEDOUT;
331*4882a593Smuzhiyun 
332*4882a593Smuzhiyun 	/* Read status from DS28E17. */
333*4882a593Smuzhiyun 	w1_read_block(sl->master, w1_buf, 2);
334*4882a593Smuzhiyun 
335*4882a593Smuzhiyun 	/* Check error conditions. */
336*4882a593Smuzhiyun 	error = w1_f19_error(sl, w1_buf);
337*4882a593Smuzhiyun 	if (error < 0)
338*4882a593Smuzhiyun 		return error;
339*4882a593Smuzhiyun 
340*4882a593Smuzhiyun 	/* Read received I2C data from DS28E17. */
341*4882a593Smuzhiyun 	return w1_read_block(sl->master, rbuffer, rcount);
342*4882a593Smuzhiyun }
343*4882a593Smuzhiyun 
344*4882a593Smuzhiyun 
345*4882a593Smuzhiyun /* Do an I2C master transfer. */
w1_f19_i2c_master_transfer(struct i2c_adapter * adapter,struct i2c_msg * msgs,int num)346*4882a593Smuzhiyun static int w1_f19_i2c_master_transfer(struct i2c_adapter *adapter,
347*4882a593Smuzhiyun 	struct i2c_msg *msgs, int num)
348*4882a593Smuzhiyun {
349*4882a593Smuzhiyun 	struct w1_slave *sl = (struct w1_slave *) adapter->algo_data;
350*4882a593Smuzhiyun 	int i = 0;
351*4882a593Smuzhiyun 	int result = 0;
352*4882a593Smuzhiyun 
353*4882a593Smuzhiyun 	/* Start onewire transaction. */
354*4882a593Smuzhiyun 	mutex_lock(&sl->master->bus_mutex);
355*4882a593Smuzhiyun 
356*4882a593Smuzhiyun 	/* Select DS28E17. */
357*4882a593Smuzhiyun 	if (w1_reset_select_slave(sl)) {
358*4882a593Smuzhiyun 		i = -EIO;
359*4882a593Smuzhiyun 		goto error;
360*4882a593Smuzhiyun 	}
361*4882a593Smuzhiyun 
362*4882a593Smuzhiyun 	/* Loop while there are still messages to transfer. */
363*4882a593Smuzhiyun 	while (i < num) {
364*4882a593Smuzhiyun 		/*
365*4882a593Smuzhiyun 		 * Check for special case: Small write followed
366*4882a593Smuzhiyun 		 * by read to same I2C device.
367*4882a593Smuzhiyun 		 */
368*4882a593Smuzhiyun 		if (i < (num-1)
369*4882a593Smuzhiyun 			&& msgs[i].addr == msgs[i+1].addr
370*4882a593Smuzhiyun 			&& !(msgs[i].flags & I2C_M_RD)
371*4882a593Smuzhiyun 			&& (msgs[i+1].flags & I2C_M_RD)
372*4882a593Smuzhiyun 			&& (msgs[i].len <= W1_F19_WRITE_DATA_LIMIT)) {
373*4882a593Smuzhiyun 			/*
374*4882a593Smuzhiyun 			 * The DS28E17 has a combined transfer
375*4882a593Smuzhiyun 			 * for small write+read.
376*4882a593Smuzhiyun 			 */
377*4882a593Smuzhiyun 			result = w1_f19_i2c_write_read(sl, msgs[i].addr,
378*4882a593Smuzhiyun 				msgs[i].buf, msgs[i].len,
379*4882a593Smuzhiyun 				msgs[i+1].buf, msgs[i+1].len);
380*4882a593Smuzhiyun 			if (result < 0) {
381*4882a593Smuzhiyun 				i = result;
382*4882a593Smuzhiyun 				goto error;
383*4882a593Smuzhiyun 			}
384*4882a593Smuzhiyun 
385*4882a593Smuzhiyun 			/*
386*4882a593Smuzhiyun 			 * Check if we should interpret the read data
387*4882a593Smuzhiyun 			 * as a length byte. The DS28E17 unfortunately
388*4882a593Smuzhiyun 			 * has no read without stop, so we can just do
389*4882a593Smuzhiyun 			 * another simple read in that case.
390*4882a593Smuzhiyun 			 */
391*4882a593Smuzhiyun 			if (msgs[i+1].flags & I2C_M_RECV_LEN) {
392*4882a593Smuzhiyun 				result = w1_f19_i2c_read(sl, msgs[i+1].addr,
393*4882a593Smuzhiyun 					&(msgs[i+1].buf[1]), msgs[i+1].buf[0]);
394*4882a593Smuzhiyun 				if (result < 0) {
395*4882a593Smuzhiyun 					i = result;
396*4882a593Smuzhiyun 					goto error;
397*4882a593Smuzhiyun 				}
398*4882a593Smuzhiyun 			}
399*4882a593Smuzhiyun 
400*4882a593Smuzhiyun 			/* Eat up read message, too. */
401*4882a593Smuzhiyun 			i++;
402*4882a593Smuzhiyun 		} else if (msgs[i].flags & I2C_M_RD) {
403*4882a593Smuzhiyun 			/* Read transfer. */
404*4882a593Smuzhiyun 			result = w1_f19_i2c_read(sl, msgs[i].addr,
405*4882a593Smuzhiyun 				msgs[i].buf, msgs[i].len);
406*4882a593Smuzhiyun 			if (result < 0) {
407*4882a593Smuzhiyun 				i = result;
408*4882a593Smuzhiyun 				goto error;
409*4882a593Smuzhiyun 			}
410*4882a593Smuzhiyun 
411*4882a593Smuzhiyun 			/*
412*4882a593Smuzhiyun 			 * Check if we should interpret the read data
413*4882a593Smuzhiyun 			 * as a length byte. The DS28E17 unfortunately
414*4882a593Smuzhiyun 			 * has no read without stop, so we can just do
415*4882a593Smuzhiyun 			 * another simple read in that case.
416*4882a593Smuzhiyun 			 */
417*4882a593Smuzhiyun 			if (msgs[i].flags & I2C_M_RECV_LEN) {
418*4882a593Smuzhiyun 				result = w1_f19_i2c_read(sl,
419*4882a593Smuzhiyun 					msgs[i].addr,
420*4882a593Smuzhiyun 					&(msgs[i].buf[1]),
421*4882a593Smuzhiyun 					msgs[i].buf[0]);
422*4882a593Smuzhiyun 				if (result < 0) {
423*4882a593Smuzhiyun 					i = result;
424*4882a593Smuzhiyun 					goto error;
425*4882a593Smuzhiyun 				}
426*4882a593Smuzhiyun 			}
427*4882a593Smuzhiyun 		} else {
428*4882a593Smuzhiyun 			/*
429*4882a593Smuzhiyun 			 * Write transfer.
430*4882a593Smuzhiyun 			 * Stop condition only for last
431*4882a593Smuzhiyun 			 * transfer.
432*4882a593Smuzhiyun 			 */
433*4882a593Smuzhiyun 			result = w1_f19_i2c_write(sl,
434*4882a593Smuzhiyun 				msgs[i].addr,
435*4882a593Smuzhiyun 				msgs[i].buf,
436*4882a593Smuzhiyun 				msgs[i].len,
437*4882a593Smuzhiyun 				i == (num-1));
438*4882a593Smuzhiyun 			if (result < 0) {
439*4882a593Smuzhiyun 				i = result;
440*4882a593Smuzhiyun 				goto error;
441*4882a593Smuzhiyun 			}
442*4882a593Smuzhiyun 		}
443*4882a593Smuzhiyun 
444*4882a593Smuzhiyun 		/* Next message. */
445*4882a593Smuzhiyun 		i++;
446*4882a593Smuzhiyun 
447*4882a593Smuzhiyun 		/* Are there still messages to send/receive? */
448*4882a593Smuzhiyun 		if (i < num) {
449*4882a593Smuzhiyun 			/* Yes. Resume to same DS28E17. */
450*4882a593Smuzhiyun 			if (w1_reset_resume_command(sl->master)) {
451*4882a593Smuzhiyun 				i = -EIO;
452*4882a593Smuzhiyun 				goto error;
453*4882a593Smuzhiyun 			}
454*4882a593Smuzhiyun 		}
455*4882a593Smuzhiyun 	}
456*4882a593Smuzhiyun 
457*4882a593Smuzhiyun error:
458*4882a593Smuzhiyun 	/* End onewire transaction. */
459*4882a593Smuzhiyun 	mutex_unlock(&sl->master->bus_mutex);
460*4882a593Smuzhiyun 
461*4882a593Smuzhiyun 	/* Return number of messages processed or error. */
462*4882a593Smuzhiyun 	return i;
463*4882a593Smuzhiyun }
464*4882a593Smuzhiyun 
465*4882a593Smuzhiyun 
466*4882a593Smuzhiyun /* Get I2C adapter functionality. */
w1_f19_i2c_functionality(struct i2c_adapter * adapter)467*4882a593Smuzhiyun static u32 w1_f19_i2c_functionality(struct i2c_adapter *adapter)
468*4882a593Smuzhiyun {
469*4882a593Smuzhiyun 	/*
470*4882a593Smuzhiyun 	 * Plain I2C functions only.
471*4882a593Smuzhiyun 	 * SMBus is emulated by the kernel's I2C layer.
472*4882a593Smuzhiyun 	 * No "I2C_FUNC_SMBUS_QUICK"
473*4882a593Smuzhiyun 	 * No "I2C_FUNC_SMBUS_READ_BLOCK_DATA"
474*4882a593Smuzhiyun 	 * No "I2C_FUNC_SMBUS_BLOCK_PROC_CALL"
475*4882a593Smuzhiyun 	 */
476*4882a593Smuzhiyun 	return I2C_FUNC_I2C |
477*4882a593Smuzhiyun 		I2C_FUNC_SMBUS_BYTE |
478*4882a593Smuzhiyun 		I2C_FUNC_SMBUS_BYTE_DATA |
479*4882a593Smuzhiyun 		I2C_FUNC_SMBUS_WORD_DATA |
480*4882a593Smuzhiyun 		I2C_FUNC_SMBUS_PROC_CALL |
481*4882a593Smuzhiyun 		I2C_FUNC_SMBUS_WRITE_BLOCK_DATA |
482*4882a593Smuzhiyun 		I2C_FUNC_SMBUS_I2C_BLOCK |
483*4882a593Smuzhiyun 		I2C_FUNC_SMBUS_PEC;
484*4882a593Smuzhiyun }
485*4882a593Smuzhiyun 
486*4882a593Smuzhiyun 
487*4882a593Smuzhiyun /* I2C adapter quirks. */
488*4882a593Smuzhiyun static const struct i2c_adapter_quirks w1_f19_i2c_adapter_quirks = {
489*4882a593Smuzhiyun 	.max_read_len = W1_F19_READ_DATA_LIMIT,
490*4882a593Smuzhiyun };
491*4882a593Smuzhiyun 
492*4882a593Smuzhiyun /* I2C algorithm. */
493*4882a593Smuzhiyun static const struct i2c_algorithm w1_f19_i2c_algorithm = {
494*4882a593Smuzhiyun 	.master_xfer    = w1_f19_i2c_master_transfer,
495*4882a593Smuzhiyun 	.functionality  = w1_f19_i2c_functionality,
496*4882a593Smuzhiyun };
497*4882a593Smuzhiyun 
498*4882a593Smuzhiyun 
499*4882a593Smuzhiyun /* Read I2C speed from DS28E17. */
w1_f19_get_i2c_speed(struct w1_slave * sl)500*4882a593Smuzhiyun static int w1_f19_get_i2c_speed(struct w1_slave *sl)
501*4882a593Smuzhiyun {
502*4882a593Smuzhiyun 	struct w1_f19_data *data = sl->family_data;
503*4882a593Smuzhiyun 	int result = -EIO;
504*4882a593Smuzhiyun 
505*4882a593Smuzhiyun 	/* Start onewire transaction. */
506*4882a593Smuzhiyun 	mutex_lock(&sl->master->bus_mutex);
507*4882a593Smuzhiyun 
508*4882a593Smuzhiyun 	/* Select slave. */
509*4882a593Smuzhiyun 	if (w1_reset_select_slave(sl))
510*4882a593Smuzhiyun 		goto error;
511*4882a593Smuzhiyun 
512*4882a593Smuzhiyun 	/* Read slave configuration byte. */
513*4882a593Smuzhiyun 	w1_write_8(sl->master, W1_F19_READ_CONFIGURATION);
514*4882a593Smuzhiyun 	result = w1_read_8(sl->master);
515*4882a593Smuzhiyun 	if (result < 0 || result > 2) {
516*4882a593Smuzhiyun 		result = -EIO;
517*4882a593Smuzhiyun 		goto error;
518*4882a593Smuzhiyun 	}
519*4882a593Smuzhiyun 
520*4882a593Smuzhiyun 	/* Update speed in slave specific data. */
521*4882a593Smuzhiyun 	data->speed = result;
522*4882a593Smuzhiyun 
523*4882a593Smuzhiyun error:
524*4882a593Smuzhiyun 	/* End onewire transaction. */
525*4882a593Smuzhiyun 	mutex_unlock(&sl->master->bus_mutex);
526*4882a593Smuzhiyun 
527*4882a593Smuzhiyun 	return result;
528*4882a593Smuzhiyun }
529*4882a593Smuzhiyun 
530*4882a593Smuzhiyun 
531*4882a593Smuzhiyun /* Set I2C speed on DS28E17. */
__w1_f19_set_i2c_speed(struct w1_slave * sl,u8 speed)532*4882a593Smuzhiyun static int __w1_f19_set_i2c_speed(struct w1_slave *sl, u8 speed)
533*4882a593Smuzhiyun {
534*4882a593Smuzhiyun 	struct w1_f19_data *data = sl->family_data;
535*4882a593Smuzhiyun 	const int i2c_speeds[3] = { 100, 400, 900 };
536*4882a593Smuzhiyun 	u8 w1_buf[2];
537*4882a593Smuzhiyun 
538*4882a593Smuzhiyun 	/* Select slave. */
539*4882a593Smuzhiyun 	if (w1_reset_select_slave(sl))
540*4882a593Smuzhiyun 		return -EIO;
541*4882a593Smuzhiyun 
542*4882a593Smuzhiyun 	w1_buf[0] = W1_F19_WRITE_CONFIGURATION;
543*4882a593Smuzhiyun 	w1_buf[1] = speed;
544*4882a593Smuzhiyun 	w1_write_block(sl->master, w1_buf, 2);
545*4882a593Smuzhiyun 
546*4882a593Smuzhiyun 	/* Update speed in slave specific data. */
547*4882a593Smuzhiyun 	data->speed = speed;
548*4882a593Smuzhiyun 
549*4882a593Smuzhiyun 	dev_info(&sl->dev, "i2c speed set to %d kBaud\n", i2c_speeds[speed]);
550*4882a593Smuzhiyun 
551*4882a593Smuzhiyun 	return 0;
552*4882a593Smuzhiyun }
553*4882a593Smuzhiyun 
w1_f19_set_i2c_speed(struct w1_slave * sl,u8 speed)554*4882a593Smuzhiyun static int w1_f19_set_i2c_speed(struct w1_slave *sl, u8 speed)
555*4882a593Smuzhiyun {
556*4882a593Smuzhiyun 	int result;
557*4882a593Smuzhiyun 
558*4882a593Smuzhiyun 	/* Start onewire transaction. */
559*4882a593Smuzhiyun 	mutex_lock(&sl->master->bus_mutex);
560*4882a593Smuzhiyun 
561*4882a593Smuzhiyun 	/* Set I2C speed on DS28E17. */
562*4882a593Smuzhiyun 	result = __w1_f19_set_i2c_speed(sl, speed);
563*4882a593Smuzhiyun 
564*4882a593Smuzhiyun 	/* End onewire transaction. */
565*4882a593Smuzhiyun 	mutex_unlock(&sl->master->bus_mutex);
566*4882a593Smuzhiyun 
567*4882a593Smuzhiyun 	return result;
568*4882a593Smuzhiyun }
569*4882a593Smuzhiyun 
570*4882a593Smuzhiyun 
571*4882a593Smuzhiyun /* Sysfs attributes. */
572*4882a593Smuzhiyun 
573*4882a593Smuzhiyun /* I2C speed attribute for a single chip. */
speed_show(struct device * dev,struct device_attribute * attr,char * buf)574*4882a593Smuzhiyun static ssize_t speed_show(struct device *dev, struct device_attribute *attr,
575*4882a593Smuzhiyun 			     char *buf)
576*4882a593Smuzhiyun {
577*4882a593Smuzhiyun 	struct w1_slave *sl = dev_to_w1_slave(dev);
578*4882a593Smuzhiyun 	int result;
579*4882a593Smuzhiyun 
580*4882a593Smuzhiyun 	/* Read current speed from slave. Updates data->speed. */
581*4882a593Smuzhiyun 	result = w1_f19_get_i2c_speed(sl);
582*4882a593Smuzhiyun 	if (result < 0)
583*4882a593Smuzhiyun 		return result;
584*4882a593Smuzhiyun 
585*4882a593Smuzhiyun 	/* Return current speed value. */
586*4882a593Smuzhiyun 	return sprintf(buf, "%d\n", result);
587*4882a593Smuzhiyun }
588*4882a593Smuzhiyun 
speed_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)589*4882a593Smuzhiyun static ssize_t speed_store(struct device *dev, struct device_attribute *attr,
590*4882a593Smuzhiyun 			      const char *buf, size_t count)
591*4882a593Smuzhiyun {
592*4882a593Smuzhiyun 	struct w1_slave *sl = dev_to_w1_slave(dev);
593*4882a593Smuzhiyun 	int error;
594*4882a593Smuzhiyun 
595*4882a593Smuzhiyun 	/* Valid values are: "100", "400", "900" */
596*4882a593Smuzhiyun 	if (count < 3 || count > 4 || !buf)
597*4882a593Smuzhiyun 		return -EINVAL;
598*4882a593Smuzhiyun 	if (count == 4 && buf[3] != '\n')
599*4882a593Smuzhiyun 		return -EINVAL;
600*4882a593Smuzhiyun 	if (buf[1] != '0' || buf[2] != '0')
601*4882a593Smuzhiyun 		return -EINVAL;
602*4882a593Smuzhiyun 
603*4882a593Smuzhiyun 	/* Set speed on slave. */
604*4882a593Smuzhiyun 	switch (buf[0]) {
605*4882a593Smuzhiyun 	case '1':
606*4882a593Smuzhiyun 		error = w1_f19_set_i2c_speed(sl, 0);
607*4882a593Smuzhiyun 		break;
608*4882a593Smuzhiyun 	case '4':
609*4882a593Smuzhiyun 		error = w1_f19_set_i2c_speed(sl, 1);
610*4882a593Smuzhiyun 		break;
611*4882a593Smuzhiyun 	case '9':
612*4882a593Smuzhiyun 		error = w1_f19_set_i2c_speed(sl, 2);
613*4882a593Smuzhiyun 		break;
614*4882a593Smuzhiyun 	default:
615*4882a593Smuzhiyun 		return -EINVAL;
616*4882a593Smuzhiyun 	}
617*4882a593Smuzhiyun 
618*4882a593Smuzhiyun 	if (error < 0)
619*4882a593Smuzhiyun 		return error;
620*4882a593Smuzhiyun 
621*4882a593Smuzhiyun 	/* Return bytes written. */
622*4882a593Smuzhiyun 	return count;
623*4882a593Smuzhiyun }
624*4882a593Smuzhiyun 
625*4882a593Smuzhiyun static DEVICE_ATTR_RW(speed);
626*4882a593Smuzhiyun 
627*4882a593Smuzhiyun 
628*4882a593Smuzhiyun /* Busy stretch attribute for a single chip. */
stretch_show(struct device * dev,struct device_attribute * attr,char * buf)629*4882a593Smuzhiyun static ssize_t stretch_show(struct device *dev, struct device_attribute *attr,
630*4882a593Smuzhiyun 			     char *buf)
631*4882a593Smuzhiyun {
632*4882a593Smuzhiyun 	struct w1_slave *sl = dev_to_w1_slave(dev);
633*4882a593Smuzhiyun 	struct w1_f19_data *data = sl->family_data;
634*4882a593Smuzhiyun 
635*4882a593Smuzhiyun 	/* Return current stretch value. */
636*4882a593Smuzhiyun 	return sprintf(buf, "%d\n", data->stretch);
637*4882a593Smuzhiyun }
638*4882a593Smuzhiyun 
stretch_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)639*4882a593Smuzhiyun static ssize_t stretch_store(struct device *dev, struct device_attribute *attr,
640*4882a593Smuzhiyun 			      const char *buf, size_t count)
641*4882a593Smuzhiyun {
642*4882a593Smuzhiyun 	struct w1_slave *sl = dev_to_w1_slave(dev);
643*4882a593Smuzhiyun 	struct w1_f19_data *data = sl->family_data;
644*4882a593Smuzhiyun 
645*4882a593Smuzhiyun 	/* Valid values are '1' to '9' */
646*4882a593Smuzhiyun 	if (count < 1 || count > 2 || !buf)
647*4882a593Smuzhiyun 		return -EINVAL;
648*4882a593Smuzhiyun 	if (count == 2 && buf[1] != '\n')
649*4882a593Smuzhiyun 		return -EINVAL;
650*4882a593Smuzhiyun 	if (buf[0] < '1' || buf[0] > '9')
651*4882a593Smuzhiyun 		return -EINVAL;
652*4882a593Smuzhiyun 
653*4882a593Smuzhiyun 	/* Set busy stretch value. */
654*4882a593Smuzhiyun 	data->stretch = buf[0] & 0x0F;
655*4882a593Smuzhiyun 
656*4882a593Smuzhiyun 	/* Return bytes written. */
657*4882a593Smuzhiyun 	return count;
658*4882a593Smuzhiyun }
659*4882a593Smuzhiyun 
660*4882a593Smuzhiyun static DEVICE_ATTR_RW(stretch);
661*4882a593Smuzhiyun 
662*4882a593Smuzhiyun 
663*4882a593Smuzhiyun /* All attributes. */
664*4882a593Smuzhiyun static struct attribute *w1_f19_attrs[] = {
665*4882a593Smuzhiyun 	&dev_attr_speed.attr,
666*4882a593Smuzhiyun 	&dev_attr_stretch.attr,
667*4882a593Smuzhiyun 	NULL,
668*4882a593Smuzhiyun };
669*4882a593Smuzhiyun 
670*4882a593Smuzhiyun static const struct attribute_group w1_f19_group = {
671*4882a593Smuzhiyun 	.attrs		= w1_f19_attrs,
672*4882a593Smuzhiyun };
673*4882a593Smuzhiyun 
674*4882a593Smuzhiyun static const struct attribute_group *w1_f19_groups[] = {
675*4882a593Smuzhiyun 	&w1_f19_group,
676*4882a593Smuzhiyun 	NULL,
677*4882a593Smuzhiyun };
678*4882a593Smuzhiyun 
679*4882a593Smuzhiyun 
680*4882a593Smuzhiyun /* Slave add and remove functions. */
w1_f19_add_slave(struct w1_slave * sl)681*4882a593Smuzhiyun static int w1_f19_add_slave(struct w1_slave *sl)
682*4882a593Smuzhiyun {
683*4882a593Smuzhiyun 	struct w1_f19_data *data = NULL;
684*4882a593Smuzhiyun 
685*4882a593Smuzhiyun 	/* Allocate memory for slave specific data. */
686*4882a593Smuzhiyun 	data = devm_kzalloc(&sl->dev, sizeof(*data), GFP_KERNEL);
687*4882a593Smuzhiyun 	if (!data)
688*4882a593Smuzhiyun 		return -ENOMEM;
689*4882a593Smuzhiyun 	sl->family_data = data;
690*4882a593Smuzhiyun 
691*4882a593Smuzhiyun 	/* Setup default I2C speed on slave. */
692*4882a593Smuzhiyun 	switch (i2c_speed) {
693*4882a593Smuzhiyun 	case 100:
694*4882a593Smuzhiyun 		__w1_f19_set_i2c_speed(sl, 0);
695*4882a593Smuzhiyun 		break;
696*4882a593Smuzhiyun 	case 400:
697*4882a593Smuzhiyun 		__w1_f19_set_i2c_speed(sl, 1);
698*4882a593Smuzhiyun 		break;
699*4882a593Smuzhiyun 	case 900:
700*4882a593Smuzhiyun 		__w1_f19_set_i2c_speed(sl, 2);
701*4882a593Smuzhiyun 		break;
702*4882a593Smuzhiyun 	default:
703*4882a593Smuzhiyun 		/*
704*4882a593Smuzhiyun 		 * A i2c_speed module parameter of anything else
705*4882a593Smuzhiyun 		 * than 100, 400, 900 means not to touch the
706*4882a593Smuzhiyun 		 * speed of the DS28E17.
707*4882a593Smuzhiyun 		 * We assume 400kBaud, the power-on value.
708*4882a593Smuzhiyun 		 */
709*4882a593Smuzhiyun 		data->speed = 1;
710*4882a593Smuzhiyun 	}
711*4882a593Smuzhiyun 
712*4882a593Smuzhiyun 	/*
713*4882a593Smuzhiyun 	 * Setup default busy stretch
714*4882a593Smuzhiyun 	 * configuration for the DS28E17.
715*4882a593Smuzhiyun 	 */
716*4882a593Smuzhiyun 	data->stretch = i2c_stretch;
717*4882a593Smuzhiyun 
718*4882a593Smuzhiyun 	/* Setup I2C adapter. */
719*4882a593Smuzhiyun 	data->adapter.owner      = THIS_MODULE;
720*4882a593Smuzhiyun 	data->adapter.algo       = &w1_f19_i2c_algorithm;
721*4882a593Smuzhiyun 	data->adapter.algo_data  = sl;
722*4882a593Smuzhiyun 	strcpy(data->adapter.name, "w1-");
723*4882a593Smuzhiyun 	strcat(data->adapter.name, sl->name);
724*4882a593Smuzhiyun 	data->adapter.dev.parent = &sl->dev;
725*4882a593Smuzhiyun 	data->adapter.quirks     = &w1_f19_i2c_adapter_quirks;
726*4882a593Smuzhiyun 
727*4882a593Smuzhiyun 	return i2c_add_adapter(&data->adapter);
728*4882a593Smuzhiyun }
729*4882a593Smuzhiyun 
w1_f19_remove_slave(struct w1_slave * sl)730*4882a593Smuzhiyun static void w1_f19_remove_slave(struct w1_slave *sl)
731*4882a593Smuzhiyun {
732*4882a593Smuzhiyun 	struct w1_f19_data *family_data = sl->family_data;
733*4882a593Smuzhiyun 
734*4882a593Smuzhiyun 	/* Delete I2C adapter. */
735*4882a593Smuzhiyun 	i2c_del_adapter(&family_data->adapter);
736*4882a593Smuzhiyun 
737*4882a593Smuzhiyun 	/* Free slave specific data. */
738*4882a593Smuzhiyun 	devm_kfree(&sl->dev, family_data);
739*4882a593Smuzhiyun 	sl->family_data = NULL;
740*4882a593Smuzhiyun }
741*4882a593Smuzhiyun 
742*4882a593Smuzhiyun 
743*4882a593Smuzhiyun /* Declarations within the w1 subsystem. */
744*4882a593Smuzhiyun static const struct w1_family_ops w1_f19_fops = {
745*4882a593Smuzhiyun 	.add_slave = w1_f19_add_slave,
746*4882a593Smuzhiyun 	.remove_slave = w1_f19_remove_slave,
747*4882a593Smuzhiyun 	.groups = w1_f19_groups,
748*4882a593Smuzhiyun };
749*4882a593Smuzhiyun 
750*4882a593Smuzhiyun static struct w1_family w1_family_19 = {
751*4882a593Smuzhiyun 	.fid = W1_FAMILY_DS28E17,
752*4882a593Smuzhiyun 	.fops = &w1_f19_fops,
753*4882a593Smuzhiyun };
754*4882a593Smuzhiyun 
755*4882a593Smuzhiyun 
756*4882a593Smuzhiyun /* Module init and remove functions. */
w1_f19_init(void)757*4882a593Smuzhiyun static int __init w1_f19_init(void)
758*4882a593Smuzhiyun {
759*4882a593Smuzhiyun 	return w1_register_family(&w1_family_19);
760*4882a593Smuzhiyun }
761*4882a593Smuzhiyun 
w1_f19_fini(void)762*4882a593Smuzhiyun static void __exit w1_f19_fini(void)
763*4882a593Smuzhiyun {
764*4882a593Smuzhiyun 	w1_unregister_family(&w1_family_19);
765*4882a593Smuzhiyun }
766*4882a593Smuzhiyun 
767*4882a593Smuzhiyun module_init(w1_f19_init);
768*4882a593Smuzhiyun module_exit(w1_f19_fini);
769*4882a593Smuzhiyun 
770