1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * 1-Wire implementation for the ds2780 chip 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Author: Renata Sayakhova <renata@oktetlabs.ru> 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * Based on w1-ds2760 driver 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #ifndef _W1_DS2781_H 11*4882a593Smuzhiyun #define _W1_DS2781_H 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun /* Function commands */ 14*4882a593Smuzhiyun #define W1_DS2781_READ_DATA 0x69 15*4882a593Smuzhiyun #define W1_DS2781_WRITE_DATA 0x6C 16*4882a593Smuzhiyun #define W1_DS2781_COPY_DATA 0x48 17*4882a593Smuzhiyun #define W1_DS2781_RECALL_DATA 0xB8 18*4882a593Smuzhiyun #define W1_DS2781_LOCK 0x6A 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun /* Register map */ 21*4882a593Smuzhiyun /* Register 0x00 Reserved */ 22*4882a593Smuzhiyun #define DS2781_STATUS 0x01 23*4882a593Smuzhiyun #define DS2781_RAAC_MSB 0x02 24*4882a593Smuzhiyun #define DS2781_RAAC_LSB 0x03 25*4882a593Smuzhiyun #define DS2781_RSAC_MSB 0x04 26*4882a593Smuzhiyun #define DS2781_RSAC_LSB 0x05 27*4882a593Smuzhiyun #define DS2781_RARC 0x06 28*4882a593Smuzhiyun #define DS2781_RSRC 0x07 29*4882a593Smuzhiyun #define DS2781_IAVG_MSB 0x08 30*4882a593Smuzhiyun #define DS2781_IAVG_LSB 0x09 31*4882a593Smuzhiyun #define DS2781_TEMP_MSB 0x0A 32*4882a593Smuzhiyun #define DS2781_TEMP_LSB 0x0B 33*4882a593Smuzhiyun #define DS2781_VOLT_MSB 0x0C 34*4882a593Smuzhiyun #define DS2781_VOLT_LSB 0x0D 35*4882a593Smuzhiyun #define DS2781_CURRENT_MSB 0x0E 36*4882a593Smuzhiyun #define DS2781_CURRENT_LSB 0x0F 37*4882a593Smuzhiyun #define DS2781_ACR_MSB 0x10 38*4882a593Smuzhiyun #define DS2781_ACR_LSB 0x11 39*4882a593Smuzhiyun #define DS2781_ACRL_MSB 0x12 40*4882a593Smuzhiyun #define DS2781_ACRL_LSB 0x13 41*4882a593Smuzhiyun #define DS2781_AS 0x14 42*4882a593Smuzhiyun #define DS2781_SFR 0x15 43*4882a593Smuzhiyun #define DS2781_FULL_MSB 0x16 44*4882a593Smuzhiyun #define DS2781_FULL_LSB 0x17 45*4882a593Smuzhiyun #define DS2781_AE_MSB 0x18 46*4882a593Smuzhiyun #define DS2781_AE_LSB 0x19 47*4882a593Smuzhiyun #define DS2781_SE_MSB 0x1A 48*4882a593Smuzhiyun #define DS2781_SE_LSB 0x1B 49*4882a593Smuzhiyun /* Register 0x1C - 0x1E Reserved */ 50*4882a593Smuzhiyun #define DS2781_EEPROM 0x1F 51*4882a593Smuzhiyun #define DS2781_EEPROM_BLOCK0_START 0x20 52*4882a593Smuzhiyun /* Register 0x20 - 0x2F User EEPROM */ 53*4882a593Smuzhiyun #define DS2781_EEPROM_BLOCK0_END 0x2F 54*4882a593Smuzhiyun /* Register 0x30 - 0x5F Reserved */ 55*4882a593Smuzhiyun #define DS2781_EEPROM_BLOCK1_START 0x60 56*4882a593Smuzhiyun #define DS2781_CONTROL 0x60 57*4882a593Smuzhiyun #define DS2781_AB 0x61 58*4882a593Smuzhiyun #define DS2781_AC_MSB 0x62 59*4882a593Smuzhiyun #define DS2781_AC_LSB 0x63 60*4882a593Smuzhiyun #define DS2781_VCHG 0x64 61*4882a593Smuzhiyun #define DS2781_IMIN 0x65 62*4882a593Smuzhiyun #define DS2781_VAE 0x66 63*4882a593Smuzhiyun #define DS2781_IAE 0x67 64*4882a593Smuzhiyun #define DS2781_AE_40 0x68 65*4882a593Smuzhiyun #define DS2781_RSNSP 0x69 66*4882a593Smuzhiyun #define DS2781_FULL_40_MSB 0x6A 67*4882a593Smuzhiyun #define DS2781_FULL_40_LSB 0x6B 68*4882a593Smuzhiyun #define DS2781_FULL_4_SLOPE 0x6C 69*4882a593Smuzhiyun #define DS2781_FULL_3_SLOPE 0x6D 70*4882a593Smuzhiyun #define DS2781_FULL_2_SLOPE 0x6E 71*4882a593Smuzhiyun #define DS2781_FULL_1_SLOPE 0x6F 72*4882a593Smuzhiyun #define DS2781_AE_4_SLOPE 0x70 73*4882a593Smuzhiyun #define DS2781_AE_3_SLOPE 0x71 74*4882a593Smuzhiyun #define DS2781_AE_2_SLOPE 0x72 75*4882a593Smuzhiyun #define DS2781_AE_1_SLOPE 0x73 76*4882a593Smuzhiyun #define DS2781_SE_4_SLOPE 0x74 77*4882a593Smuzhiyun #define DS2781_SE_3_SLOPE 0x75 78*4882a593Smuzhiyun #define DS2781_SE_2_SLOPE 0x76 79*4882a593Smuzhiyun #define DS2781_SE_1_SLOPE 0x77 80*4882a593Smuzhiyun #define DS2781_RSGAIN_MSB 0x78 81*4882a593Smuzhiyun #define DS2781_RSGAIN_LSB 0x79 82*4882a593Smuzhiyun #define DS2781_RSTC 0x7A 83*4882a593Smuzhiyun #define DS2781_COB 0x7B 84*4882a593Smuzhiyun #define DS2781_TBP34 0x7C 85*4882a593Smuzhiyun #define DS2781_TBP23 0x7D 86*4882a593Smuzhiyun #define DS2781_TBP12 0x7E 87*4882a593Smuzhiyun #define DS2781_EEPROM_BLOCK1_END 0x7F 88*4882a593Smuzhiyun /* Register 0x7D - 0xFF Reserved */ 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun #define DS2781_FSGAIN_MSB 0xB0 91*4882a593Smuzhiyun #define DS2781_FSGAIN_LSB 0xB1 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun /* Number of valid register addresses */ 94*4882a593Smuzhiyun #define DS2781_DATA_SIZE 0xB2 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun /* Status register bits */ 97*4882a593Smuzhiyun #define DS2781_STATUS_CHGTF (1 << 7) 98*4882a593Smuzhiyun #define DS2781_STATUS_AEF (1 << 6) 99*4882a593Smuzhiyun #define DS2781_STATUS_SEF (1 << 5) 100*4882a593Smuzhiyun #define DS2781_STATUS_LEARNF (1 << 4) 101*4882a593Smuzhiyun /* Bit 3 Reserved */ 102*4882a593Smuzhiyun #define DS2781_STATUS_UVF (1 << 2) 103*4882a593Smuzhiyun #define DS2781_STATUS_PORF (1 << 1) 104*4882a593Smuzhiyun /* Bit 0 Reserved */ 105*4882a593Smuzhiyun 106*4882a593Smuzhiyun /* Control register bits */ 107*4882a593Smuzhiyun /* Bit 7 Reserved */ 108*4882a593Smuzhiyun #define DS2781_CONTROL_NBEN (1 << 7) 109*4882a593Smuzhiyun #define DS2781_CONTROL_UVEN (1 << 6) 110*4882a593Smuzhiyun #define DS2781_CONTROL_PMOD (1 << 5) 111*4882a593Smuzhiyun #define DS2781_CONTROL_RNAOP (1 << 4) 112*4882a593Smuzhiyun #define DS1781_CONTROL_UVTH (1 << 3) 113*4882a593Smuzhiyun /* Bit 0 - 2 Reserved */ 114*4882a593Smuzhiyun 115*4882a593Smuzhiyun /* Special feature register bits */ 116*4882a593Smuzhiyun /* Bit 1 - 7 Reserved */ 117*4882a593Smuzhiyun #define DS2781_SFR_PIOSC (1 << 0) 118*4882a593Smuzhiyun 119*4882a593Smuzhiyun /* EEPROM register bits */ 120*4882a593Smuzhiyun #define DS2781_EEPROM_EEC (1 << 7) 121*4882a593Smuzhiyun #define DS2781_EEPROM_LOCK (1 << 6) 122*4882a593Smuzhiyun /* Bit 2 - 6 Reserved */ 123*4882a593Smuzhiyun #define DS2781_EEPROM_BL1 (1 << 1) 124*4882a593Smuzhiyun #define DS2781_EEPROM_BL0 (1 << 0) 125*4882a593Smuzhiyun 126*4882a593Smuzhiyun extern int w1_ds2781_io(struct device *dev, char *buf, int addr, size_t count, 127*4882a593Smuzhiyun int io); 128*4882a593Smuzhiyun extern int w1_ds2781_eeprom_cmd(struct device *dev, int addr, int cmd); 129*4882a593Smuzhiyun 130*4882a593Smuzhiyun #endif /* !_W1_DS2781_H */ 131