1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * 1-Wire implementation for the ds2780 chip 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2010 Indesign, LLC 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * Author: Clifton Barnes <cabarnes@indesign-llc.com> 8*4882a593Smuzhiyun * 9*4882a593Smuzhiyun * Based on w1-ds2760 driver 10*4882a593Smuzhiyun */ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #ifndef _W1_DS2780_H 13*4882a593Smuzhiyun #define _W1_DS2780_H 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun /* Function commands */ 16*4882a593Smuzhiyun #define W1_DS2780_READ_DATA 0x69 17*4882a593Smuzhiyun #define W1_DS2780_WRITE_DATA 0x6C 18*4882a593Smuzhiyun #define W1_DS2780_COPY_DATA 0x48 19*4882a593Smuzhiyun #define W1_DS2780_RECALL_DATA 0xB8 20*4882a593Smuzhiyun #define W1_DS2780_LOCK 0x6A 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun /* Register map */ 23*4882a593Smuzhiyun /* Register 0x00 Reserved */ 24*4882a593Smuzhiyun #define DS2780_STATUS_REG 0x01 25*4882a593Smuzhiyun #define DS2780_RAAC_MSB_REG 0x02 26*4882a593Smuzhiyun #define DS2780_RAAC_LSB_REG 0x03 27*4882a593Smuzhiyun #define DS2780_RSAC_MSB_REG 0x04 28*4882a593Smuzhiyun #define DS2780_RSAC_LSB_REG 0x05 29*4882a593Smuzhiyun #define DS2780_RARC_REG 0x06 30*4882a593Smuzhiyun #define DS2780_RSRC_REG 0x07 31*4882a593Smuzhiyun #define DS2780_IAVG_MSB_REG 0x08 32*4882a593Smuzhiyun #define DS2780_IAVG_LSB_REG 0x09 33*4882a593Smuzhiyun #define DS2780_TEMP_MSB_REG 0x0A 34*4882a593Smuzhiyun #define DS2780_TEMP_LSB_REG 0x0B 35*4882a593Smuzhiyun #define DS2780_VOLT_MSB_REG 0x0C 36*4882a593Smuzhiyun #define DS2780_VOLT_LSB_REG 0x0D 37*4882a593Smuzhiyun #define DS2780_CURRENT_MSB_REG 0x0E 38*4882a593Smuzhiyun #define DS2780_CURRENT_LSB_REG 0x0F 39*4882a593Smuzhiyun #define DS2780_ACR_MSB_REG 0x10 40*4882a593Smuzhiyun #define DS2780_ACR_LSB_REG 0x11 41*4882a593Smuzhiyun #define DS2780_ACRL_MSB_REG 0x12 42*4882a593Smuzhiyun #define DS2780_ACRL_LSB_REG 0x13 43*4882a593Smuzhiyun #define DS2780_AS_REG 0x14 44*4882a593Smuzhiyun #define DS2780_SFR_REG 0x15 45*4882a593Smuzhiyun #define DS2780_FULL_MSB_REG 0x16 46*4882a593Smuzhiyun #define DS2780_FULL_LSB_REG 0x17 47*4882a593Smuzhiyun #define DS2780_AE_MSB_REG 0x18 48*4882a593Smuzhiyun #define DS2780_AE_LSB_REG 0x19 49*4882a593Smuzhiyun #define DS2780_SE_MSB_REG 0x1A 50*4882a593Smuzhiyun #define DS2780_SE_LSB_REG 0x1B 51*4882a593Smuzhiyun /* Register 0x1C - 0x1E Reserved */ 52*4882a593Smuzhiyun #define DS2780_EEPROM_REG 0x1F 53*4882a593Smuzhiyun #define DS2780_EEPROM_BLOCK0_START 0x20 54*4882a593Smuzhiyun /* Register 0x20 - 0x2F User EEPROM */ 55*4882a593Smuzhiyun #define DS2780_EEPROM_BLOCK0_END 0x2F 56*4882a593Smuzhiyun /* Register 0x30 - 0x5F Reserved */ 57*4882a593Smuzhiyun #define DS2780_EEPROM_BLOCK1_START 0x60 58*4882a593Smuzhiyun #define DS2780_CONTROL_REG 0x60 59*4882a593Smuzhiyun #define DS2780_AB_REG 0x61 60*4882a593Smuzhiyun #define DS2780_AC_MSB_REG 0x62 61*4882a593Smuzhiyun #define DS2780_AC_LSB_REG 0x63 62*4882a593Smuzhiyun #define DS2780_VCHG_REG 0x64 63*4882a593Smuzhiyun #define DS2780_IMIN_REG 0x65 64*4882a593Smuzhiyun #define DS2780_VAE_REG 0x66 65*4882a593Smuzhiyun #define DS2780_IAE_REG 0x67 66*4882a593Smuzhiyun #define DS2780_AE_40_REG 0x68 67*4882a593Smuzhiyun #define DS2780_RSNSP_REG 0x69 68*4882a593Smuzhiyun #define DS2780_FULL_40_MSB_REG 0x6A 69*4882a593Smuzhiyun #define DS2780_FULL_40_LSB_REG 0x6B 70*4882a593Smuzhiyun #define DS2780_FULL_3040_SLOPE_REG 0x6C 71*4882a593Smuzhiyun #define DS2780_FULL_2030_SLOPE_REG 0x6D 72*4882a593Smuzhiyun #define DS2780_FULL_1020_SLOPE_REG 0x6E 73*4882a593Smuzhiyun #define DS2780_FULL_0010_SLOPE_REG 0x6F 74*4882a593Smuzhiyun #define DS2780_AE_3040_SLOPE_REG 0x70 75*4882a593Smuzhiyun #define DS2780_AE_2030_SLOPE_REG 0x71 76*4882a593Smuzhiyun #define DS2780_AE_1020_SLOPE_REG 0x72 77*4882a593Smuzhiyun #define DS2780_AE_0010_SLOPE_REG 0x73 78*4882a593Smuzhiyun #define DS2780_SE_3040_SLOPE_REG 0x74 79*4882a593Smuzhiyun #define DS2780_SE_2030_SLOPE_REG 0x75 80*4882a593Smuzhiyun #define DS2780_SE_1020_SLOPE_REG 0x76 81*4882a593Smuzhiyun #define DS2780_SE_0010_SLOPE_REG 0x77 82*4882a593Smuzhiyun #define DS2780_RSGAIN_MSB_REG 0x78 83*4882a593Smuzhiyun #define DS2780_RSGAIN_LSB_REG 0x79 84*4882a593Smuzhiyun #define DS2780_RSTC_REG 0x7A 85*4882a593Smuzhiyun #define DS2780_FRSGAIN_MSB_REG 0x7B 86*4882a593Smuzhiyun #define DS2780_FRSGAIN_LSB_REG 0x7C 87*4882a593Smuzhiyun #define DS2780_EEPROM_BLOCK1_END 0x7C 88*4882a593Smuzhiyun /* Register 0x7D - 0xFF Reserved */ 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun /* Number of valid register addresses */ 91*4882a593Smuzhiyun #define DS2780_DATA_SIZE 0x80 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun /* Status register bits */ 94*4882a593Smuzhiyun #define DS2780_STATUS_REG_CHGTF (1 << 7) 95*4882a593Smuzhiyun #define DS2780_STATUS_REG_AEF (1 << 6) 96*4882a593Smuzhiyun #define DS2780_STATUS_REG_SEF (1 << 5) 97*4882a593Smuzhiyun #define DS2780_STATUS_REG_LEARNF (1 << 4) 98*4882a593Smuzhiyun /* Bit 3 Reserved */ 99*4882a593Smuzhiyun #define DS2780_STATUS_REG_UVF (1 << 2) 100*4882a593Smuzhiyun #define DS2780_STATUS_REG_PORF (1 << 1) 101*4882a593Smuzhiyun /* Bit 0 Reserved */ 102*4882a593Smuzhiyun 103*4882a593Smuzhiyun /* Control register bits */ 104*4882a593Smuzhiyun /* Bit 7 Reserved */ 105*4882a593Smuzhiyun #define DS2780_CONTROL_REG_UVEN (1 << 6) 106*4882a593Smuzhiyun #define DS2780_CONTROL_REG_PMOD (1 << 5) 107*4882a593Smuzhiyun #define DS2780_CONTROL_REG_RNAOP (1 << 4) 108*4882a593Smuzhiyun /* Bit 0 - 3 Reserved */ 109*4882a593Smuzhiyun 110*4882a593Smuzhiyun /* Special feature register bits */ 111*4882a593Smuzhiyun /* Bit 1 - 7 Reserved */ 112*4882a593Smuzhiyun #define DS2780_SFR_REG_PIOSC (1 << 0) 113*4882a593Smuzhiyun 114*4882a593Smuzhiyun /* EEPROM register bits */ 115*4882a593Smuzhiyun #define DS2780_EEPROM_REG_EEC (1 << 7) 116*4882a593Smuzhiyun #define DS2780_EEPROM_REG_LOCK (1 << 6) 117*4882a593Smuzhiyun /* Bit 2 - 6 Reserved */ 118*4882a593Smuzhiyun #define DS2780_EEPROM_REG_BL1 (1 << 1) 119*4882a593Smuzhiyun #define DS2780_EEPROM_REG_BL0 (1 << 0) 120*4882a593Smuzhiyun 121*4882a593Smuzhiyun extern int w1_ds2780_io(struct device *dev, char *buf, int addr, size_t count, 122*4882a593Smuzhiyun int io); 123*4882a593Smuzhiyun extern int w1_ds2780_eeprom_cmd(struct device *dev, int addr, int cmd); 124*4882a593Smuzhiyun 125*4882a593Smuzhiyun #endif /* !_W1_DS2780_H */ 126