xref: /OK3568_Linux_fs/kernel/drivers/w1/masters/mxc_w1.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * Copyright 2005-2008 Freescale Semiconductor, Inc. All Rights Reserved.
4*4882a593Smuzhiyun  * Copyright 2008 Luotao Fu, kernel@pengutronix.de
5*4882a593Smuzhiyun  */
6*4882a593Smuzhiyun 
7*4882a593Smuzhiyun #include <linux/clk.h>
8*4882a593Smuzhiyun #include <linux/delay.h>
9*4882a593Smuzhiyun #include <linux/io.h>
10*4882a593Smuzhiyun #include <linux/ktime.h>
11*4882a593Smuzhiyun #include <linux/module.h>
12*4882a593Smuzhiyun #include <linux/mod_devicetable.h>
13*4882a593Smuzhiyun #include <linux/platform_device.h>
14*4882a593Smuzhiyun 
15*4882a593Smuzhiyun #include <linux/w1.h>
16*4882a593Smuzhiyun 
17*4882a593Smuzhiyun /*
18*4882a593Smuzhiyun  * MXC W1 Register offsets
19*4882a593Smuzhiyun  */
20*4882a593Smuzhiyun #define MXC_W1_CONTROL		0x00
21*4882a593Smuzhiyun # define MXC_W1_CONTROL_RDST	BIT(3)
22*4882a593Smuzhiyun # define MXC_W1_CONTROL_WR(x)	BIT(5 - (x))
23*4882a593Smuzhiyun # define MXC_W1_CONTROL_PST	BIT(6)
24*4882a593Smuzhiyun # define MXC_W1_CONTROL_RPP	BIT(7)
25*4882a593Smuzhiyun #define MXC_W1_TIME_DIVIDER	0x02
26*4882a593Smuzhiyun #define MXC_W1_RESET		0x04
27*4882a593Smuzhiyun # define MXC_W1_RESET_RST	BIT(0)
28*4882a593Smuzhiyun 
29*4882a593Smuzhiyun struct mxc_w1_device {
30*4882a593Smuzhiyun 	void __iomem *regs;
31*4882a593Smuzhiyun 	struct clk *clk;
32*4882a593Smuzhiyun 	struct w1_bus_master bus_master;
33*4882a593Smuzhiyun };
34*4882a593Smuzhiyun 
35*4882a593Smuzhiyun /*
36*4882a593Smuzhiyun  * this is the low level routine to
37*4882a593Smuzhiyun  * reset the device on the One Wire interface
38*4882a593Smuzhiyun  * on the hardware
39*4882a593Smuzhiyun  */
mxc_w1_ds2_reset_bus(void * data)40*4882a593Smuzhiyun static u8 mxc_w1_ds2_reset_bus(void *data)
41*4882a593Smuzhiyun {
42*4882a593Smuzhiyun 	struct mxc_w1_device *dev = data;
43*4882a593Smuzhiyun 	ktime_t timeout;
44*4882a593Smuzhiyun 
45*4882a593Smuzhiyun 	writeb(MXC_W1_CONTROL_RPP, dev->regs + MXC_W1_CONTROL);
46*4882a593Smuzhiyun 
47*4882a593Smuzhiyun 	/* Wait for reset sequence 511+512us, use 1500us for sure */
48*4882a593Smuzhiyun 	timeout = ktime_add_us(ktime_get(), 1500);
49*4882a593Smuzhiyun 
50*4882a593Smuzhiyun 	udelay(511 + 512);
51*4882a593Smuzhiyun 
52*4882a593Smuzhiyun 	do {
53*4882a593Smuzhiyun 		u8 ctrl = readb(dev->regs + MXC_W1_CONTROL);
54*4882a593Smuzhiyun 
55*4882a593Smuzhiyun 		/* PST bit is valid after the RPP bit is self-cleared */
56*4882a593Smuzhiyun 		if (!(ctrl & MXC_W1_CONTROL_RPP))
57*4882a593Smuzhiyun 			return !(ctrl & MXC_W1_CONTROL_PST);
58*4882a593Smuzhiyun 	} while (ktime_before(ktime_get(), timeout));
59*4882a593Smuzhiyun 
60*4882a593Smuzhiyun 	return 1;
61*4882a593Smuzhiyun }
62*4882a593Smuzhiyun 
63*4882a593Smuzhiyun /*
64*4882a593Smuzhiyun  * this is the low level routine to read/write a bit on the One Wire
65*4882a593Smuzhiyun  * interface on the hardware. It does write 0 if parameter bit is set
66*4882a593Smuzhiyun  * to 0, otherwise a write 1/read.
67*4882a593Smuzhiyun  */
mxc_w1_ds2_touch_bit(void * data,u8 bit)68*4882a593Smuzhiyun static u8 mxc_w1_ds2_touch_bit(void *data, u8 bit)
69*4882a593Smuzhiyun {
70*4882a593Smuzhiyun 	struct mxc_w1_device *dev = data;
71*4882a593Smuzhiyun 	ktime_t timeout;
72*4882a593Smuzhiyun 
73*4882a593Smuzhiyun 	writeb(MXC_W1_CONTROL_WR(bit), dev->regs + MXC_W1_CONTROL);
74*4882a593Smuzhiyun 
75*4882a593Smuzhiyun 	/* Wait for read/write bit (60us, Max 120us), use 200us for sure */
76*4882a593Smuzhiyun 	timeout = ktime_add_us(ktime_get(), 200);
77*4882a593Smuzhiyun 
78*4882a593Smuzhiyun 	udelay(60);
79*4882a593Smuzhiyun 
80*4882a593Smuzhiyun 	do {
81*4882a593Smuzhiyun 		u8 ctrl = readb(dev->regs + MXC_W1_CONTROL);
82*4882a593Smuzhiyun 
83*4882a593Smuzhiyun 		/* RDST bit is valid after the WR1/RD bit is self-cleared */
84*4882a593Smuzhiyun 		if (!(ctrl & MXC_W1_CONTROL_WR(bit)))
85*4882a593Smuzhiyun 			return !!(ctrl & MXC_W1_CONTROL_RDST);
86*4882a593Smuzhiyun 	} while (ktime_before(ktime_get(), timeout));
87*4882a593Smuzhiyun 
88*4882a593Smuzhiyun 	return 0;
89*4882a593Smuzhiyun }
90*4882a593Smuzhiyun 
mxc_w1_probe(struct platform_device * pdev)91*4882a593Smuzhiyun static int mxc_w1_probe(struct platform_device *pdev)
92*4882a593Smuzhiyun {
93*4882a593Smuzhiyun 	struct mxc_w1_device *mdev;
94*4882a593Smuzhiyun 	unsigned long clkrate;
95*4882a593Smuzhiyun 	unsigned int clkdiv;
96*4882a593Smuzhiyun 	int err;
97*4882a593Smuzhiyun 
98*4882a593Smuzhiyun 	mdev = devm_kzalloc(&pdev->dev, sizeof(struct mxc_w1_device),
99*4882a593Smuzhiyun 			    GFP_KERNEL);
100*4882a593Smuzhiyun 	if (!mdev)
101*4882a593Smuzhiyun 		return -ENOMEM;
102*4882a593Smuzhiyun 
103*4882a593Smuzhiyun 	mdev->clk = devm_clk_get(&pdev->dev, NULL);
104*4882a593Smuzhiyun 	if (IS_ERR(mdev->clk))
105*4882a593Smuzhiyun 		return PTR_ERR(mdev->clk);
106*4882a593Smuzhiyun 
107*4882a593Smuzhiyun 	err = clk_prepare_enable(mdev->clk);
108*4882a593Smuzhiyun 	if (err)
109*4882a593Smuzhiyun 		return err;
110*4882a593Smuzhiyun 
111*4882a593Smuzhiyun 	clkrate = clk_get_rate(mdev->clk);
112*4882a593Smuzhiyun 	if (clkrate < 10000000)
113*4882a593Smuzhiyun 		dev_warn(&pdev->dev,
114*4882a593Smuzhiyun 			 "Low clock frequency causes improper function\n");
115*4882a593Smuzhiyun 
116*4882a593Smuzhiyun 	clkdiv = DIV_ROUND_CLOSEST(clkrate, 1000000);
117*4882a593Smuzhiyun 	clkrate /= clkdiv;
118*4882a593Smuzhiyun 	if ((clkrate < 980000) || (clkrate > 1020000))
119*4882a593Smuzhiyun 		dev_warn(&pdev->dev,
120*4882a593Smuzhiyun 			 "Incorrect time base frequency %lu Hz\n", clkrate);
121*4882a593Smuzhiyun 
122*4882a593Smuzhiyun 	mdev->regs = devm_platform_ioremap_resource(pdev, 0);
123*4882a593Smuzhiyun 	if (IS_ERR(mdev->regs)) {
124*4882a593Smuzhiyun 		err = PTR_ERR(mdev->regs);
125*4882a593Smuzhiyun 		goto out_disable_clk;
126*4882a593Smuzhiyun 	}
127*4882a593Smuzhiyun 
128*4882a593Smuzhiyun 	/* Software reset 1-Wire module */
129*4882a593Smuzhiyun 	writeb(MXC_W1_RESET_RST, mdev->regs + MXC_W1_RESET);
130*4882a593Smuzhiyun 	writeb(0, mdev->regs + MXC_W1_RESET);
131*4882a593Smuzhiyun 
132*4882a593Smuzhiyun 	writeb(clkdiv - 1, mdev->regs + MXC_W1_TIME_DIVIDER);
133*4882a593Smuzhiyun 
134*4882a593Smuzhiyun 	mdev->bus_master.data = mdev;
135*4882a593Smuzhiyun 	mdev->bus_master.reset_bus = mxc_w1_ds2_reset_bus;
136*4882a593Smuzhiyun 	mdev->bus_master.touch_bit = mxc_w1_ds2_touch_bit;
137*4882a593Smuzhiyun 
138*4882a593Smuzhiyun 	platform_set_drvdata(pdev, mdev);
139*4882a593Smuzhiyun 
140*4882a593Smuzhiyun 	err = w1_add_master_device(&mdev->bus_master);
141*4882a593Smuzhiyun 	if (err)
142*4882a593Smuzhiyun 		goto out_disable_clk;
143*4882a593Smuzhiyun 
144*4882a593Smuzhiyun 	return 0;
145*4882a593Smuzhiyun 
146*4882a593Smuzhiyun out_disable_clk:
147*4882a593Smuzhiyun 	clk_disable_unprepare(mdev->clk);
148*4882a593Smuzhiyun 	return err;
149*4882a593Smuzhiyun }
150*4882a593Smuzhiyun 
151*4882a593Smuzhiyun /*
152*4882a593Smuzhiyun  * disassociate the w1 device from the driver
153*4882a593Smuzhiyun  */
mxc_w1_remove(struct platform_device * pdev)154*4882a593Smuzhiyun static int mxc_w1_remove(struct platform_device *pdev)
155*4882a593Smuzhiyun {
156*4882a593Smuzhiyun 	struct mxc_w1_device *mdev = platform_get_drvdata(pdev);
157*4882a593Smuzhiyun 
158*4882a593Smuzhiyun 	w1_remove_master_device(&mdev->bus_master);
159*4882a593Smuzhiyun 
160*4882a593Smuzhiyun 	clk_disable_unprepare(mdev->clk);
161*4882a593Smuzhiyun 
162*4882a593Smuzhiyun 	return 0;
163*4882a593Smuzhiyun }
164*4882a593Smuzhiyun 
165*4882a593Smuzhiyun static const struct of_device_id mxc_w1_dt_ids[] = {
166*4882a593Smuzhiyun 	{ .compatible = "fsl,imx21-owire" },
167*4882a593Smuzhiyun 	{ /* sentinel */ }
168*4882a593Smuzhiyun };
169*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, mxc_w1_dt_ids);
170*4882a593Smuzhiyun 
171*4882a593Smuzhiyun static struct platform_driver mxc_w1_driver = {
172*4882a593Smuzhiyun 	.driver = {
173*4882a593Smuzhiyun 		.name = "mxc_w1",
174*4882a593Smuzhiyun 		.of_match_table = mxc_w1_dt_ids,
175*4882a593Smuzhiyun 	},
176*4882a593Smuzhiyun 	.probe = mxc_w1_probe,
177*4882a593Smuzhiyun 	.remove = mxc_w1_remove,
178*4882a593Smuzhiyun };
179*4882a593Smuzhiyun module_platform_driver(mxc_w1_driver);
180*4882a593Smuzhiyun 
181*4882a593Smuzhiyun MODULE_LICENSE("GPL");
182*4882a593Smuzhiyun MODULE_AUTHOR("Freescale Semiconductors Inc");
183*4882a593Smuzhiyun MODULE_DESCRIPTION("Driver for One-Wire on MXC");
184