xref: /OK3568_Linux_fs/kernel/drivers/w1/masters/ds2482.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /**
3*4882a593Smuzhiyun  * ds2482.c - provides i2c to w1-master bridge(s)
4*4882a593Smuzhiyun  * Copyright (C) 2005  Ben Gardner <bgardner@wabtec.com>
5*4882a593Smuzhiyun  *
6*4882a593Smuzhiyun  * The DS2482 is a sensor chip made by Dallas Semiconductor (Maxim).
7*4882a593Smuzhiyun  * It is a I2C to 1-wire bridge.
8*4882a593Smuzhiyun  * There are two variations: -100 and -800, which have 1 or 8 1-wire ports.
9*4882a593Smuzhiyun  * The complete datasheet can be obtained from MAXIM's website at:
10*4882a593Smuzhiyun  *   http://www.maxim-ic.com/quick_view2.cfm/qv_pk/4382
11*4882a593Smuzhiyun  */
12*4882a593Smuzhiyun 
13*4882a593Smuzhiyun #include <linux/module.h>
14*4882a593Smuzhiyun #include <linux/init.h>
15*4882a593Smuzhiyun #include <linux/slab.h>
16*4882a593Smuzhiyun #include <linux/i2c.h>
17*4882a593Smuzhiyun #include <linux/delay.h>
18*4882a593Smuzhiyun #include <asm/delay.h>
19*4882a593Smuzhiyun 
20*4882a593Smuzhiyun #include <linux/w1.h>
21*4882a593Smuzhiyun 
22*4882a593Smuzhiyun /**
23*4882a593Smuzhiyun  * Allow the active pullup to be disabled, default is enabled.
24*4882a593Smuzhiyun  *
25*4882a593Smuzhiyun  * Note from the DS2482 datasheet:
26*4882a593Smuzhiyun  * The APU bit controls whether an active pullup (controlled slew-rate
27*4882a593Smuzhiyun  * transistor) or a passive pullup (Rwpu resistor) will be used to drive
28*4882a593Smuzhiyun  * a 1-Wire line from low to high. When APU = 0, active pullup is disabled
29*4882a593Smuzhiyun  * (resistor mode). Active Pullup should always be selected unless there is
30*4882a593Smuzhiyun  * only a single slave on the 1-Wire line.
31*4882a593Smuzhiyun  */
32*4882a593Smuzhiyun static int ds2482_active_pullup = 1;
33*4882a593Smuzhiyun module_param_named(active_pullup, ds2482_active_pullup, int, 0644);
34*4882a593Smuzhiyun MODULE_PARM_DESC(active_pullup, "Active pullup (apply to all buses): " \
35*4882a593Smuzhiyun 				"0-disable, 1-enable (default)");
36*4882a593Smuzhiyun 
37*4882a593Smuzhiyun /* extra configurations - e.g. 1WS */
38*4882a593Smuzhiyun static int extra_config;
39*4882a593Smuzhiyun module_param(extra_config, int, S_IRUGO | S_IWUSR);
40*4882a593Smuzhiyun MODULE_PARM_DESC(extra_config, "Extra Configuration settings 1=APU,2=PPM,3=SPU,8=1WS");
41*4882a593Smuzhiyun 
42*4882a593Smuzhiyun /**
43*4882a593Smuzhiyun  * The DS2482 registers - there are 3 registers that are addressed by a read
44*4882a593Smuzhiyun  * pointer. The read pointer is set by the last command executed.
45*4882a593Smuzhiyun  *
46*4882a593Smuzhiyun  * To read the data, issue a register read for any address
47*4882a593Smuzhiyun  */
48*4882a593Smuzhiyun #define DS2482_CMD_RESET		0xF0	/* No param */
49*4882a593Smuzhiyun #define DS2482_CMD_SET_READ_PTR		0xE1	/* Param: DS2482_PTR_CODE_xxx */
50*4882a593Smuzhiyun #define DS2482_CMD_CHANNEL_SELECT	0xC3	/* Param: Channel byte - DS2482-800 only */
51*4882a593Smuzhiyun #define DS2482_CMD_WRITE_CONFIG		0xD2	/* Param: Config byte */
52*4882a593Smuzhiyun #define DS2482_CMD_1WIRE_RESET		0xB4	/* Param: None */
53*4882a593Smuzhiyun #define DS2482_CMD_1WIRE_SINGLE_BIT	0x87	/* Param: Bit byte (bit7) */
54*4882a593Smuzhiyun #define DS2482_CMD_1WIRE_WRITE_BYTE	0xA5	/* Param: Data byte */
55*4882a593Smuzhiyun #define DS2482_CMD_1WIRE_READ_BYTE	0x96	/* Param: None */
56*4882a593Smuzhiyun /* Note to read the byte, Set the ReadPtr to Data then read (any addr) */
57*4882a593Smuzhiyun #define DS2482_CMD_1WIRE_TRIPLET	0x78	/* Param: Dir byte (bit7) */
58*4882a593Smuzhiyun 
59*4882a593Smuzhiyun /* Values for DS2482_CMD_SET_READ_PTR */
60*4882a593Smuzhiyun #define DS2482_PTR_CODE_STATUS		0xF0
61*4882a593Smuzhiyun #define DS2482_PTR_CODE_DATA		0xE1
62*4882a593Smuzhiyun #define DS2482_PTR_CODE_CHANNEL		0xD2	/* DS2482-800 only */
63*4882a593Smuzhiyun #define DS2482_PTR_CODE_CONFIG		0xC3
64*4882a593Smuzhiyun 
65*4882a593Smuzhiyun /**
66*4882a593Smuzhiyun  * Configure Register bit definitions
67*4882a593Smuzhiyun  * The top 4 bits always read 0.
68*4882a593Smuzhiyun  * To write, the top nibble must be the 1's compl. of the low nibble.
69*4882a593Smuzhiyun  */
70*4882a593Smuzhiyun #define DS2482_REG_CFG_1WS		0x08	/* 1-wire speed */
71*4882a593Smuzhiyun #define DS2482_REG_CFG_SPU		0x04	/* strong pull-up */
72*4882a593Smuzhiyun #define DS2482_REG_CFG_PPM		0x02	/* presence pulse masking */
73*4882a593Smuzhiyun #define DS2482_REG_CFG_APU		0x01	/* active pull-up */
74*4882a593Smuzhiyun 
75*4882a593Smuzhiyun 
76*4882a593Smuzhiyun /**
77*4882a593Smuzhiyun  * Write and verify codes for the CHANNEL_SELECT command (DS2482-800 only).
78*4882a593Smuzhiyun  * To set the channel, write the value at the index of the channel.
79*4882a593Smuzhiyun  * Read and compare against the corresponding value to verify the change.
80*4882a593Smuzhiyun  */
81*4882a593Smuzhiyun static const u8 ds2482_chan_wr[8] =
82*4882a593Smuzhiyun 	{ 0xF0, 0xE1, 0xD2, 0xC3, 0xB4, 0xA5, 0x96, 0x87 };
83*4882a593Smuzhiyun static const u8 ds2482_chan_rd[8] =
84*4882a593Smuzhiyun 	{ 0xB8, 0xB1, 0xAA, 0xA3, 0x9C, 0x95, 0x8E, 0x87 };
85*4882a593Smuzhiyun 
86*4882a593Smuzhiyun 
87*4882a593Smuzhiyun /**
88*4882a593Smuzhiyun  * Status Register bit definitions (read only)
89*4882a593Smuzhiyun  */
90*4882a593Smuzhiyun #define DS2482_REG_STS_DIR		0x80
91*4882a593Smuzhiyun #define DS2482_REG_STS_TSB		0x40
92*4882a593Smuzhiyun #define DS2482_REG_STS_SBR		0x20
93*4882a593Smuzhiyun #define DS2482_REG_STS_RST		0x10
94*4882a593Smuzhiyun #define DS2482_REG_STS_LL		0x08
95*4882a593Smuzhiyun #define DS2482_REG_STS_SD		0x04
96*4882a593Smuzhiyun #define DS2482_REG_STS_PPD		0x02
97*4882a593Smuzhiyun #define DS2482_REG_STS_1WB		0x01
98*4882a593Smuzhiyun 
99*4882a593Smuzhiyun /*
100*4882a593Smuzhiyun  * Client data (each client gets its own)
101*4882a593Smuzhiyun  */
102*4882a593Smuzhiyun 
103*4882a593Smuzhiyun struct ds2482_data;
104*4882a593Smuzhiyun 
105*4882a593Smuzhiyun struct ds2482_w1_chan {
106*4882a593Smuzhiyun 	struct ds2482_data	*pdev;
107*4882a593Smuzhiyun 	u8			channel;
108*4882a593Smuzhiyun 	struct w1_bus_master	w1_bm;
109*4882a593Smuzhiyun };
110*4882a593Smuzhiyun 
111*4882a593Smuzhiyun struct ds2482_data {
112*4882a593Smuzhiyun 	struct i2c_client	*client;
113*4882a593Smuzhiyun 	struct mutex		access_lock;
114*4882a593Smuzhiyun 
115*4882a593Smuzhiyun 	/* 1-wire interface(s) */
116*4882a593Smuzhiyun 	int			w1_count;	/* 1 or 8 */
117*4882a593Smuzhiyun 	struct ds2482_w1_chan	w1_ch[8];
118*4882a593Smuzhiyun 
119*4882a593Smuzhiyun 	/* per-device values */
120*4882a593Smuzhiyun 	u8			channel;
121*4882a593Smuzhiyun 	u8			read_prt;	/* see DS2482_PTR_CODE_xxx */
122*4882a593Smuzhiyun 	u8			reg_config;
123*4882a593Smuzhiyun };
124*4882a593Smuzhiyun 
125*4882a593Smuzhiyun 
126*4882a593Smuzhiyun /**
127*4882a593Smuzhiyun  * Helper to calculate values for configuration register
128*4882a593Smuzhiyun  * @param conf the raw config value
129*4882a593Smuzhiyun  * @return the value w/ complements that can be written to register
130*4882a593Smuzhiyun  */
ds2482_calculate_config(u8 conf)131*4882a593Smuzhiyun static inline u8 ds2482_calculate_config(u8 conf)
132*4882a593Smuzhiyun {
133*4882a593Smuzhiyun 	conf |= extra_config;
134*4882a593Smuzhiyun 
135*4882a593Smuzhiyun 	if (ds2482_active_pullup)
136*4882a593Smuzhiyun 		conf |= DS2482_REG_CFG_APU;
137*4882a593Smuzhiyun 
138*4882a593Smuzhiyun 	return conf | ((~conf & 0x0f) << 4);
139*4882a593Smuzhiyun }
140*4882a593Smuzhiyun 
141*4882a593Smuzhiyun 
142*4882a593Smuzhiyun /**
143*4882a593Smuzhiyun  * Sets the read pointer.
144*4882a593Smuzhiyun  * @param pdev		The ds2482 client pointer
145*4882a593Smuzhiyun  * @param read_ptr	see DS2482_PTR_CODE_xxx above
146*4882a593Smuzhiyun  * @return -1 on failure, 0 on success
147*4882a593Smuzhiyun  */
ds2482_select_register(struct ds2482_data * pdev,u8 read_ptr)148*4882a593Smuzhiyun static inline int ds2482_select_register(struct ds2482_data *pdev, u8 read_ptr)
149*4882a593Smuzhiyun {
150*4882a593Smuzhiyun 	if (pdev->read_prt != read_ptr) {
151*4882a593Smuzhiyun 		if (i2c_smbus_write_byte_data(pdev->client,
152*4882a593Smuzhiyun 					      DS2482_CMD_SET_READ_PTR,
153*4882a593Smuzhiyun 					      read_ptr) < 0)
154*4882a593Smuzhiyun 			return -1;
155*4882a593Smuzhiyun 
156*4882a593Smuzhiyun 		pdev->read_prt = read_ptr;
157*4882a593Smuzhiyun 	}
158*4882a593Smuzhiyun 	return 0;
159*4882a593Smuzhiyun }
160*4882a593Smuzhiyun 
161*4882a593Smuzhiyun /**
162*4882a593Smuzhiyun  * Sends a command without a parameter
163*4882a593Smuzhiyun  * @param pdev	The ds2482 client pointer
164*4882a593Smuzhiyun  * @param cmd	DS2482_CMD_RESET,
165*4882a593Smuzhiyun  *		DS2482_CMD_1WIRE_RESET,
166*4882a593Smuzhiyun  *		DS2482_CMD_1WIRE_READ_BYTE
167*4882a593Smuzhiyun  * @return -1 on failure, 0 on success
168*4882a593Smuzhiyun  */
ds2482_send_cmd(struct ds2482_data * pdev,u8 cmd)169*4882a593Smuzhiyun static inline int ds2482_send_cmd(struct ds2482_data *pdev, u8 cmd)
170*4882a593Smuzhiyun {
171*4882a593Smuzhiyun 	if (i2c_smbus_write_byte(pdev->client, cmd) < 0)
172*4882a593Smuzhiyun 		return -1;
173*4882a593Smuzhiyun 
174*4882a593Smuzhiyun 	pdev->read_prt = DS2482_PTR_CODE_STATUS;
175*4882a593Smuzhiyun 	return 0;
176*4882a593Smuzhiyun }
177*4882a593Smuzhiyun 
178*4882a593Smuzhiyun /**
179*4882a593Smuzhiyun  * Sends a command with a parameter
180*4882a593Smuzhiyun  * @param pdev	The ds2482 client pointer
181*4882a593Smuzhiyun  * @param cmd	DS2482_CMD_WRITE_CONFIG,
182*4882a593Smuzhiyun  *		DS2482_CMD_1WIRE_SINGLE_BIT,
183*4882a593Smuzhiyun  *		DS2482_CMD_1WIRE_WRITE_BYTE,
184*4882a593Smuzhiyun  *		DS2482_CMD_1WIRE_TRIPLET
185*4882a593Smuzhiyun  * @param byte	The data to send
186*4882a593Smuzhiyun  * @return -1 on failure, 0 on success
187*4882a593Smuzhiyun  */
ds2482_send_cmd_data(struct ds2482_data * pdev,u8 cmd,u8 byte)188*4882a593Smuzhiyun static inline int ds2482_send_cmd_data(struct ds2482_data *pdev,
189*4882a593Smuzhiyun 				       u8 cmd, u8 byte)
190*4882a593Smuzhiyun {
191*4882a593Smuzhiyun 	if (i2c_smbus_write_byte_data(pdev->client, cmd, byte) < 0)
192*4882a593Smuzhiyun 		return -1;
193*4882a593Smuzhiyun 
194*4882a593Smuzhiyun 	/* all cmds leave in STATUS, except CONFIG */
195*4882a593Smuzhiyun 	pdev->read_prt = (cmd != DS2482_CMD_WRITE_CONFIG) ?
196*4882a593Smuzhiyun 			 DS2482_PTR_CODE_STATUS : DS2482_PTR_CODE_CONFIG;
197*4882a593Smuzhiyun 	return 0;
198*4882a593Smuzhiyun }
199*4882a593Smuzhiyun 
200*4882a593Smuzhiyun 
201*4882a593Smuzhiyun /*
202*4882a593Smuzhiyun  * 1-Wire interface code
203*4882a593Smuzhiyun  */
204*4882a593Smuzhiyun 
205*4882a593Smuzhiyun #define DS2482_WAIT_IDLE_TIMEOUT	100
206*4882a593Smuzhiyun 
207*4882a593Smuzhiyun /**
208*4882a593Smuzhiyun  * Waits until the 1-wire interface is idle (not busy)
209*4882a593Smuzhiyun  *
210*4882a593Smuzhiyun  * @param pdev Pointer to the device structure
211*4882a593Smuzhiyun  * @return the last value read from status or -1 (failure)
212*4882a593Smuzhiyun  */
ds2482_wait_1wire_idle(struct ds2482_data * pdev)213*4882a593Smuzhiyun static int ds2482_wait_1wire_idle(struct ds2482_data *pdev)
214*4882a593Smuzhiyun {
215*4882a593Smuzhiyun 	int temp = -1;
216*4882a593Smuzhiyun 	int retries = 0;
217*4882a593Smuzhiyun 
218*4882a593Smuzhiyun 	if (!ds2482_select_register(pdev, DS2482_PTR_CODE_STATUS)) {
219*4882a593Smuzhiyun 		do {
220*4882a593Smuzhiyun 			temp = i2c_smbus_read_byte(pdev->client);
221*4882a593Smuzhiyun 		} while ((temp >= 0) && (temp & DS2482_REG_STS_1WB) &&
222*4882a593Smuzhiyun 			 (++retries < DS2482_WAIT_IDLE_TIMEOUT));
223*4882a593Smuzhiyun 	}
224*4882a593Smuzhiyun 
225*4882a593Smuzhiyun 	if (retries >= DS2482_WAIT_IDLE_TIMEOUT)
226*4882a593Smuzhiyun 		pr_err("%s: timeout on channel %d\n",
227*4882a593Smuzhiyun 		       __func__, pdev->channel);
228*4882a593Smuzhiyun 
229*4882a593Smuzhiyun 	return temp;
230*4882a593Smuzhiyun }
231*4882a593Smuzhiyun 
232*4882a593Smuzhiyun /**
233*4882a593Smuzhiyun  * Selects a w1 channel.
234*4882a593Smuzhiyun  * The 1-wire interface must be idle before calling this function.
235*4882a593Smuzhiyun  *
236*4882a593Smuzhiyun  * @param pdev		The ds2482 client pointer
237*4882a593Smuzhiyun  * @param channel	0-7
238*4882a593Smuzhiyun  * @return		-1 (failure) or 0 (success)
239*4882a593Smuzhiyun  */
ds2482_set_channel(struct ds2482_data * pdev,u8 channel)240*4882a593Smuzhiyun static int ds2482_set_channel(struct ds2482_data *pdev, u8 channel)
241*4882a593Smuzhiyun {
242*4882a593Smuzhiyun 	if (i2c_smbus_write_byte_data(pdev->client, DS2482_CMD_CHANNEL_SELECT,
243*4882a593Smuzhiyun 				      ds2482_chan_wr[channel]) < 0)
244*4882a593Smuzhiyun 		return -1;
245*4882a593Smuzhiyun 
246*4882a593Smuzhiyun 	pdev->read_prt = DS2482_PTR_CODE_CHANNEL;
247*4882a593Smuzhiyun 	pdev->channel = -1;
248*4882a593Smuzhiyun 	if (i2c_smbus_read_byte(pdev->client) == ds2482_chan_rd[channel]) {
249*4882a593Smuzhiyun 		pdev->channel = channel;
250*4882a593Smuzhiyun 		return 0;
251*4882a593Smuzhiyun 	}
252*4882a593Smuzhiyun 	return -1;
253*4882a593Smuzhiyun }
254*4882a593Smuzhiyun 
255*4882a593Smuzhiyun 
256*4882a593Smuzhiyun /**
257*4882a593Smuzhiyun  * Performs the touch-bit function, which writes a 0 or 1 and reads the level.
258*4882a593Smuzhiyun  *
259*4882a593Smuzhiyun  * @param data	The ds2482 channel pointer
260*4882a593Smuzhiyun  * @param bit	The level to write: 0 or non-zero
261*4882a593Smuzhiyun  * @return	The level read: 0 or 1
262*4882a593Smuzhiyun  */
ds2482_w1_touch_bit(void * data,u8 bit)263*4882a593Smuzhiyun static u8 ds2482_w1_touch_bit(void *data, u8 bit)
264*4882a593Smuzhiyun {
265*4882a593Smuzhiyun 	struct ds2482_w1_chan *pchan = data;
266*4882a593Smuzhiyun 	struct ds2482_data    *pdev = pchan->pdev;
267*4882a593Smuzhiyun 	int status = -1;
268*4882a593Smuzhiyun 
269*4882a593Smuzhiyun 	mutex_lock(&pdev->access_lock);
270*4882a593Smuzhiyun 
271*4882a593Smuzhiyun 	/* Select the channel */
272*4882a593Smuzhiyun 	ds2482_wait_1wire_idle(pdev);
273*4882a593Smuzhiyun 	if (pdev->w1_count > 1)
274*4882a593Smuzhiyun 		ds2482_set_channel(pdev, pchan->channel);
275*4882a593Smuzhiyun 
276*4882a593Smuzhiyun 	/* Send the touch command, wait until 1WB == 0, return the status */
277*4882a593Smuzhiyun 	if (!ds2482_send_cmd_data(pdev, DS2482_CMD_1WIRE_SINGLE_BIT,
278*4882a593Smuzhiyun 				  bit ? 0xFF : 0))
279*4882a593Smuzhiyun 		status = ds2482_wait_1wire_idle(pdev);
280*4882a593Smuzhiyun 
281*4882a593Smuzhiyun 	mutex_unlock(&pdev->access_lock);
282*4882a593Smuzhiyun 
283*4882a593Smuzhiyun 	return (status & DS2482_REG_STS_SBR) ? 1 : 0;
284*4882a593Smuzhiyun }
285*4882a593Smuzhiyun 
286*4882a593Smuzhiyun /**
287*4882a593Smuzhiyun  * Performs the triplet function, which reads two bits and writes a bit.
288*4882a593Smuzhiyun  * The bit written is determined by the two reads:
289*4882a593Smuzhiyun  *   00 => dbit, 01 => 0, 10 => 1
290*4882a593Smuzhiyun  *
291*4882a593Smuzhiyun  * @param data	The ds2482 channel pointer
292*4882a593Smuzhiyun  * @param dbit	The direction to choose if both branches are valid
293*4882a593Smuzhiyun  * @return	b0=read1 b1=read2 b3=bit written
294*4882a593Smuzhiyun  */
ds2482_w1_triplet(void * data,u8 dbit)295*4882a593Smuzhiyun static u8 ds2482_w1_triplet(void *data, u8 dbit)
296*4882a593Smuzhiyun {
297*4882a593Smuzhiyun 	struct ds2482_w1_chan *pchan = data;
298*4882a593Smuzhiyun 	struct ds2482_data    *pdev = pchan->pdev;
299*4882a593Smuzhiyun 	int status = (3 << 5);
300*4882a593Smuzhiyun 
301*4882a593Smuzhiyun 	mutex_lock(&pdev->access_lock);
302*4882a593Smuzhiyun 
303*4882a593Smuzhiyun 	/* Select the channel */
304*4882a593Smuzhiyun 	ds2482_wait_1wire_idle(pdev);
305*4882a593Smuzhiyun 	if (pdev->w1_count > 1)
306*4882a593Smuzhiyun 		ds2482_set_channel(pdev, pchan->channel);
307*4882a593Smuzhiyun 
308*4882a593Smuzhiyun 	/* Send the triplet command, wait until 1WB == 0, return the status */
309*4882a593Smuzhiyun 	if (!ds2482_send_cmd_data(pdev, DS2482_CMD_1WIRE_TRIPLET,
310*4882a593Smuzhiyun 				  dbit ? 0xFF : 0))
311*4882a593Smuzhiyun 		status = ds2482_wait_1wire_idle(pdev);
312*4882a593Smuzhiyun 
313*4882a593Smuzhiyun 	mutex_unlock(&pdev->access_lock);
314*4882a593Smuzhiyun 
315*4882a593Smuzhiyun 	/* Decode the status */
316*4882a593Smuzhiyun 	return (status >> 5);
317*4882a593Smuzhiyun }
318*4882a593Smuzhiyun 
319*4882a593Smuzhiyun /**
320*4882a593Smuzhiyun  * Performs the write byte function.
321*4882a593Smuzhiyun  *
322*4882a593Smuzhiyun  * @param data	The ds2482 channel pointer
323*4882a593Smuzhiyun  * @param byte	The value to write
324*4882a593Smuzhiyun  */
ds2482_w1_write_byte(void * data,u8 byte)325*4882a593Smuzhiyun static void ds2482_w1_write_byte(void *data, u8 byte)
326*4882a593Smuzhiyun {
327*4882a593Smuzhiyun 	struct ds2482_w1_chan *pchan = data;
328*4882a593Smuzhiyun 	struct ds2482_data    *pdev = pchan->pdev;
329*4882a593Smuzhiyun 
330*4882a593Smuzhiyun 	mutex_lock(&pdev->access_lock);
331*4882a593Smuzhiyun 
332*4882a593Smuzhiyun 	/* Select the channel */
333*4882a593Smuzhiyun 	ds2482_wait_1wire_idle(pdev);
334*4882a593Smuzhiyun 	if (pdev->w1_count > 1)
335*4882a593Smuzhiyun 		ds2482_set_channel(pdev, pchan->channel);
336*4882a593Smuzhiyun 
337*4882a593Smuzhiyun 	/* Send the write byte command */
338*4882a593Smuzhiyun 	ds2482_send_cmd_data(pdev, DS2482_CMD_1WIRE_WRITE_BYTE, byte);
339*4882a593Smuzhiyun 
340*4882a593Smuzhiyun 	mutex_unlock(&pdev->access_lock);
341*4882a593Smuzhiyun }
342*4882a593Smuzhiyun 
343*4882a593Smuzhiyun /**
344*4882a593Smuzhiyun  * Performs the read byte function.
345*4882a593Smuzhiyun  *
346*4882a593Smuzhiyun  * @param data	The ds2482 channel pointer
347*4882a593Smuzhiyun  * @return	The value read
348*4882a593Smuzhiyun  */
ds2482_w1_read_byte(void * data)349*4882a593Smuzhiyun static u8 ds2482_w1_read_byte(void *data)
350*4882a593Smuzhiyun {
351*4882a593Smuzhiyun 	struct ds2482_w1_chan *pchan = data;
352*4882a593Smuzhiyun 	struct ds2482_data    *pdev = pchan->pdev;
353*4882a593Smuzhiyun 	int result;
354*4882a593Smuzhiyun 
355*4882a593Smuzhiyun 	mutex_lock(&pdev->access_lock);
356*4882a593Smuzhiyun 
357*4882a593Smuzhiyun 	/* Select the channel */
358*4882a593Smuzhiyun 	ds2482_wait_1wire_idle(pdev);
359*4882a593Smuzhiyun 	if (pdev->w1_count > 1)
360*4882a593Smuzhiyun 		ds2482_set_channel(pdev, pchan->channel);
361*4882a593Smuzhiyun 
362*4882a593Smuzhiyun 	/* Send the read byte command */
363*4882a593Smuzhiyun 	ds2482_send_cmd(pdev, DS2482_CMD_1WIRE_READ_BYTE);
364*4882a593Smuzhiyun 
365*4882a593Smuzhiyun 	/* Wait until 1WB == 0 */
366*4882a593Smuzhiyun 	ds2482_wait_1wire_idle(pdev);
367*4882a593Smuzhiyun 
368*4882a593Smuzhiyun 	/* Select the data register */
369*4882a593Smuzhiyun 	ds2482_select_register(pdev, DS2482_PTR_CODE_DATA);
370*4882a593Smuzhiyun 
371*4882a593Smuzhiyun 	/* Read the data byte */
372*4882a593Smuzhiyun 	result = i2c_smbus_read_byte(pdev->client);
373*4882a593Smuzhiyun 
374*4882a593Smuzhiyun 	mutex_unlock(&pdev->access_lock);
375*4882a593Smuzhiyun 
376*4882a593Smuzhiyun 	return result;
377*4882a593Smuzhiyun }
378*4882a593Smuzhiyun 
379*4882a593Smuzhiyun 
380*4882a593Smuzhiyun /**
381*4882a593Smuzhiyun  * Sends a reset on the 1-wire interface
382*4882a593Smuzhiyun  *
383*4882a593Smuzhiyun  * @param data	The ds2482 channel pointer
384*4882a593Smuzhiyun  * @return	0=Device present, 1=No device present or error
385*4882a593Smuzhiyun  */
ds2482_w1_reset_bus(void * data)386*4882a593Smuzhiyun static u8 ds2482_w1_reset_bus(void *data)
387*4882a593Smuzhiyun {
388*4882a593Smuzhiyun 	struct ds2482_w1_chan *pchan = data;
389*4882a593Smuzhiyun 	struct ds2482_data    *pdev = pchan->pdev;
390*4882a593Smuzhiyun 	int err;
391*4882a593Smuzhiyun 	u8 retval = 1;
392*4882a593Smuzhiyun 
393*4882a593Smuzhiyun 	mutex_lock(&pdev->access_lock);
394*4882a593Smuzhiyun 
395*4882a593Smuzhiyun 	/* Select the channel */
396*4882a593Smuzhiyun 	ds2482_wait_1wire_idle(pdev);
397*4882a593Smuzhiyun 	if (pdev->w1_count > 1)
398*4882a593Smuzhiyun 		ds2482_set_channel(pdev, pchan->channel);
399*4882a593Smuzhiyun 
400*4882a593Smuzhiyun 	/* Send the reset command */
401*4882a593Smuzhiyun 	err = ds2482_send_cmd(pdev, DS2482_CMD_1WIRE_RESET);
402*4882a593Smuzhiyun 	if (err >= 0) {
403*4882a593Smuzhiyun 		/* Wait until the reset is complete */
404*4882a593Smuzhiyun 		err = ds2482_wait_1wire_idle(pdev);
405*4882a593Smuzhiyun 		retval = !(err & DS2482_REG_STS_PPD);
406*4882a593Smuzhiyun 
407*4882a593Smuzhiyun 		/* If the chip did reset since detect, re-config it */
408*4882a593Smuzhiyun 		if (err & DS2482_REG_STS_RST)
409*4882a593Smuzhiyun 			ds2482_send_cmd_data(pdev, DS2482_CMD_WRITE_CONFIG,
410*4882a593Smuzhiyun 					     ds2482_calculate_config(0x00));
411*4882a593Smuzhiyun 	}
412*4882a593Smuzhiyun 
413*4882a593Smuzhiyun 	mutex_unlock(&pdev->access_lock);
414*4882a593Smuzhiyun 
415*4882a593Smuzhiyun 	return retval;
416*4882a593Smuzhiyun }
417*4882a593Smuzhiyun 
ds2482_w1_set_pullup(void * data,int delay)418*4882a593Smuzhiyun static u8 ds2482_w1_set_pullup(void *data, int delay)
419*4882a593Smuzhiyun {
420*4882a593Smuzhiyun 	struct ds2482_w1_chan *pchan = data;
421*4882a593Smuzhiyun 	struct ds2482_data    *pdev = pchan->pdev;
422*4882a593Smuzhiyun 	u8 retval = 1;
423*4882a593Smuzhiyun 
424*4882a593Smuzhiyun 	/* if delay is non-zero activate the pullup,
425*4882a593Smuzhiyun 	 * the strong pullup will be automatically deactivated
426*4882a593Smuzhiyun 	 * by the master, so do not explicitly deactive it
427*4882a593Smuzhiyun 	 */
428*4882a593Smuzhiyun 	if (delay) {
429*4882a593Smuzhiyun 		/* both waits are crucial, otherwise devices might not be
430*4882a593Smuzhiyun 		 * powered long enough, causing e.g. a w1_therm sensor to
431*4882a593Smuzhiyun 		 * provide wrong conversion results
432*4882a593Smuzhiyun 		 */
433*4882a593Smuzhiyun 		ds2482_wait_1wire_idle(pdev);
434*4882a593Smuzhiyun 		/* note: it seems like both SPU and APU have to be set! */
435*4882a593Smuzhiyun 		retval = ds2482_send_cmd_data(pdev, DS2482_CMD_WRITE_CONFIG,
436*4882a593Smuzhiyun 			ds2482_calculate_config(DS2482_REG_CFG_SPU |
437*4882a593Smuzhiyun 						DS2482_REG_CFG_APU));
438*4882a593Smuzhiyun 		ds2482_wait_1wire_idle(pdev);
439*4882a593Smuzhiyun 	}
440*4882a593Smuzhiyun 
441*4882a593Smuzhiyun 	return retval;
442*4882a593Smuzhiyun }
443*4882a593Smuzhiyun 
444*4882a593Smuzhiyun 
ds2482_probe(struct i2c_client * client,const struct i2c_device_id * id)445*4882a593Smuzhiyun static int ds2482_probe(struct i2c_client *client,
446*4882a593Smuzhiyun 			const struct i2c_device_id *id)
447*4882a593Smuzhiyun {
448*4882a593Smuzhiyun 	struct ds2482_data *data;
449*4882a593Smuzhiyun 	int err = -ENODEV;
450*4882a593Smuzhiyun 	int temp1;
451*4882a593Smuzhiyun 	int idx;
452*4882a593Smuzhiyun 
453*4882a593Smuzhiyun 	if (!i2c_check_functionality(client->adapter,
454*4882a593Smuzhiyun 				     I2C_FUNC_SMBUS_WRITE_BYTE_DATA |
455*4882a593Smuzhiyun 				     I2C_FUNC_SMBUS_BYTE))
456*4882a593Smuzhiyun 		return -ENODEV;
457*4882a593Smuzhiyun 
458*4882a593Smuzhiyun 	if (!(data = kzalloc(sizeof(struct ds2482_data), GFP_KERNEL))) {
459*4882a593Smuzhiyun 		err = -ENOMEM;
460*4882a593Smuzhiyun 		goto exit;
461*4882a593Smuzhiyun 	}
462*4882a593Smuzhiyun 
463*4882a593Smuzhiyun 	data->client = client;
464*4882a593Smuzhiyun 	i2c_set_clientdata(client, data);
465*4882a593Smuzhiyun 
466*4882a593Smuzhiyun 	/* Reset the device (sets the read_ptr to status) */
467*4882a593Smuzhiyun 	if (ds2482_send_cmd(data, DS2482_CMD_RESET) < 0) {
468*4882a593Smuzhiyun 		dev_warn(&client->dev, "DS2482 reset failed.\n");
469*4882a593Smuzhiyun 		goto exit_free;
470*4882a593Smuzhiyun 	}
471*4882a593Smuzhiyun 
472*4882a593Smuzhiyun 	/* Sleep at least 525ns to allow the reset to complete */
473*4882a593Smuzhiyun 	ndelay(525);
474*4882a593Smuzhiyun 
475*4882a593Smuzhiyun 	/* Read the status byte - only reset bit and line should be set */
476*4882a593Smuzhiyun 	temp1 = i2c_smbus_read_byte(client);
477*4882a593Smuzhiyun 	if (temp1 != (DS2482_REG_STS_LL | DS2482_REG_STS_RST)) {
478*4882a593Smuzhiyun 		dev_warn(&client->dev, "DS2482 reset status "
479*4882a593Smuzhiyun 			 "0x%02X - not a DS2482\n", temp1);
480*4882a593Smuzhiyun 		goto exit_free;
481*4882a593Smuzhiyun 	}
482*4882a593Smuzhiyun 
483*4882a593Smuzhiyun 	/* Detect the 8-port version */
484*4882a593Smuzhiyun 	data->w1_count = 1;
485*4882a593Smuzhiyun 	if (ds2482_set_channel(data, 7) == 0)
486*4882a593Smuzhiyun 		data->w1_count = 8;
487*4882a593Smuzhiyun 
488*4882a593Smuzhiyun 	/* Set all config items to 0 (off) */
489*4882a593Smuzhiyun 	ds2482_send_cmd_data(data, DS2482_CMD_WRITE_CONFIG,
490*4882a593Smuzhiyun 		ds2482_calculate_config(0x00));
491*4882a593Smuzhiyun 
492*4882a593Smuzhiyun 	mutex_init(&data->access_lock);
493*4882a593Smuzhiyun 
494*4882a593Smuzhiyun 	/* Register 1-wire interface(s) */
495*4882a593Smuzhiyun 	for (idx = 0; idx < data->w1_count; idx++) {
496*4882a593Smuzhiyun 		data->w1_ch[idx].pdev = data;
497*4882a593Smuzhiyun 		data->w1_ch[idx].channel = idx;
498*4882a593Smuzhiyun 
499*4882a593Smuzhiyun 		/* Populate all the w1 bus master stuff */
500*4882a593Smuzhiyun 		data->w1_ch[idx].w1_bm.data       = &data->w1_ch[idx];
501*4882a593Smuzhiyun 		data->w1_ch[idx].w1_bm.read_byte  = ds2482_w1_read_byte;
502*4882a593Smuzhiyun 		data->w1_ch[idx].w1_bm.write_byte = ds2482_w1_write_byte;
503*4882a593Smuzhiyun 		data->w1_ch[idx].w1_bm.touch_bit  = ds2482_w1_touch_bit;
504*4882a593Smuzhiyun 		data->w1_ch[idx].w1_bm.triplet    = ds2482_w1_triplet;
505*4882a593Smuzhiyun 		data->w1_ch[idx].w1_bm.reset_bus  = ds2482_w1_reset_bus;
506*4882a593Smuzhiyun 		data->w1_ch[idx].w1_bm.set_pullup = ds2482_w1_set_pullup;
507*4882a593Smuzhiyun 
508*4882a593Smuzhiyun 		err = w1_add_master_device(&data->w1_ch[idx].w1_bm);
509*4882a593Smuzhiyun 		if (err) {
510*4882a593Smuzhiyun 			data->w1_ch[idx].pdev = NULL;
511*4882a593Smuzhiyun 			goto exit_w1_remove;
512*4882a593Smuzhiyun 		}
513*4882a593Smuzhiyun 	}
514*4882a593Smuzhiyun 
515*4882a593Smuzhiyun 	return 0;
516*4882a593Smuzhiyun 
517*4882a593Smuzhiyun exit_w1_remove:
518*4882a593Smuzhiyun 	for (idx = 0; idx < data->w1_count; idx++) {
519*4882a593Smuzhiyun 		if (data->w1_ch[idx].pdev != NULL)
520*4882a593Smuzhiyun 			w1_remove_master_device(&data->w1_ch[idx].w1_bm);
521*4882a593Smuzhiyun 	}
522*4882a593Smuzhiyun exit_free:
523*4882a593Smuzhiyun 	kfree(data);
524*4882a593Smuzhiyun exit:
525*4882a593Smuzhiyun 	return err;
526*4882a593Smuzhiyun }
527*4882a593Smuzhiyun 
ds2482_remove(struct i2c_client * client)528*4882a593Smuzhiyun static int ds2482_remove(struct i2c_client *client)
529*4882a593Smuzhiyun {
530*4882a593Smuzhiyun 	struct ds2482_data   *data = i2c_get_clientdata(client);
531*4882a593Smuzhiyun 	int idx;
532*4882a593Smuzhiyun 
533*4882a593Smuzhiyun 	/* Unregister the 1-wire bridge(s) */
534*4882a593Smuzhiyun 	for (idx = 0; idx < data->w1_count; idx++) {
535*4882a593Smuzhiyun 		if (data->w1_ch[idx].pdev != NULL)
536*4882a593Smuzhiyun 			w1_remove_master_device(&data->w1_ch[idx].w1_bm);
537*4882a593Smuzhiyun 	}
538*4882a593Smuzhiyun 
539*4882a593Smuzhiyun 	/* Free the memory */
540*4882a593Smuzhiyun 	kfree(data);
541*4882a593Smuzhiyun 	return 0;
542*4882a593Smuzhiyun }
543*4882a593Smuzhiyun 
544*4882a593Smuzhiyun /**
545*4882a593Smuzhiyun  * Driver data (common to all clients)
546*4882a593Smuzhiyun  */
547*4882a593Smuzhiyun static const struct i2c_device_id ds2482_id[] = {
548*4882a593Smuzhiyun 	{ "ds2482", 0 },
549*4882a593Smuzhiyun 	{ }
550*4882a593Smuzhiyun };
551*4882a593Smuzhiyun MODULE_DEVICE_TABLE(i2c, ds2482_id);
552*4882a593Smuzhiyun 
553*4882a593Smuzhiyun static struct i2c_driver ds2482_driver = {
554*4882a593Smuzhiyun 	.driver = {
555*4882a593Smuzhiyun 		.name	= "ds2482",
556*4882a593Smuzhiyun 	},
557*4882a593Smuzhiyun 	.probe		= ds2482_probe,
558*4882a593Smuzhiyun 	.remove		= ds2482_remove,
559*4882a593Smuzhiyun 	.id_table	= ds2482_id,
560*4882a593Smuzhiyun };
561*4882a593Smuzhiyun module_i2c_driver(ds2482_driver);
562*4882a593Smuzhiyun 
563*4882a593Smuzhiyun MODULE_AUTHOR("Ben Gardner <bgardner@wabtec.com>");
564*4882a593Smuzhiyun MODULE_DESCRIPTION("DS2482 driver");
565*4882a593Smuzhiyun 
566*4882a593Smuzhiyun MODULE_LICENSE("GPL");
567