1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * linux/drivers/video/vgastate.c -- VGA state save/restore
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * Copyright 2002 James Simmons
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * Copyright history from vga16fb.c:
7*4882a593Smuzhiyun * Copyright 1999 Ben Pfaff and Petr Vandrovec
8*4882a593Smuzhiyun * Based on VGA info at http://www.goodnet.com/~tinara/FreeVGA/home.htm
9*4882a593Smuzhiyun * Based on VESA framebuffer (c) 1998 Gerd Knorr
10*4882a593Smuzhiyun *
11*4882a593Smuzhiyun * This file is subject to the terms and conditions of the GNU General
12*4882a593Smuzhiyun * Public License. See the file COPYING in the main directory of this
13*4882a593Smuzhiyun * archive for more details.
14*4882a593Smuzhiyun *
15*4882a593Smuzhiyun */
16*4882a593Smuzhiyun #include <linux/module.h>
17*4882a593Smuzhiyun #include <linux/slab.h>
18*4882a593Smuzhiyun #include <linux/fb.h>
19*4882a593Smuzhiyun #include <linux/vmalloc.h>
20*4882a593Smuzhiyun #include <video/vga.h>
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun struct regstate {
23*4882a593Smuzhiyun __u8 *vga_font0;
24*4882a593Smuzhiyun __u8 *vga_font1;
25*4882a593Smuzhiyun __u8 *vga_text;
26*4882a593Smuzhiyun __u8 *vga_cmap;
27*4882a593Smuzhiyun __u8 *attr;
28*4882a593Smuzhiyun __u8 *crtc;
29*4882a593Smuzhiyun __u8 *gfx;
30*4882a593Smuzhiyun __u8 *seq;
31*4882a593Smuzhiyun __u8 misc;
32*4882a593Smuzhiyun };
33*4882a593Smuzhiyun
vga_rcrtcs(void __iomem * regbase,unsigned short iobase,unsigned char reg)34*4882a593Smuzhiyun static inline unsigned char vga_rcrtcs(void __iomem *regbase, unsigned short iobase,
35*4882a593Smuzhiyun unsigned char reg)
36*4882a593Smuzhiyun {
37*4882a593Smuzhiyun vga_w(regbase, iobase + 0x4, reg);
38*4882a593Smuzhiyun return vga_r(regbase, iobase + 0x5);
39*4882a593Smuzhiyun }
40*4882a593Smuzhiyun
vga_wcrtcs(void __iomem * regbase,unsigned short iobase,unsigned char reg,unsigned char val)41*4882a593Smuzhiyun static inline void vga_wcrtcs(void __iomem *regbase, unsigned short iobase,
42*4882a593Smuzhiyun unsigned char reg, unsigned char val)
43*4882a593Smuzhiyun {
44*4882a593Smuzhiyun vga_w(regbase, iobase + 0x4, reg);
45*4882a593Smuzhiyun vga_w(regbase, iobase + 0x5, val);
46*4882a593Smuzhiyun }
47*4882a593Smuzhiyun
save_vga_text(struct vgastate * state,void __iomem * fbbase)48*4882a593Smuzhiyun static void save_vga_text(struct vgastate *state, void __iomem *fbbase)
49*4882a593Smuzhiyun {
50*4882a593Smuzhiyun struct regstate *saved = (struct regstate *) state->vidstate;
51*4882a593Smuzhiyun int i;
52*4882a593Smuzhiyun u8 misc, attr10, gr4, gr5, gr6, seq1, seq2, seq4;
53*4882a593Smuzhiyun unsigned short iobase;
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun /* if in graphics mode, no need to save */
56*4882a593Smuzhiyun misc = vga_r(state->vgabase, VGA_MIS_R);
57*4882a593Smuzhiyun iobase = (misc & 1) ? 0x3d0 : 0x3b0;
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun vga_r(state->vgabase, iobase + 0xa);
60*4882a593Smuzhiyun vga_w(state->vgabase, VGA_ATT_W, 0x00);
61*4882a593Smuzhiyun attr10 = vga_rattr(state->vgabase, 0x10);
62*4882a593Smuzhiyun vga_r(state->vgabase, iobase + 0xa);
63*4882a593Smuzhiyun vga_w(state->vgabase, VGA_ATT_W, 0x20);
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun if (attr10 & 1)
66*4882a593Smuzhiyun return;
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun /* save regs */
69*4882a593Smuzhiyun gr4 = vga_rgfx(state->vgabase, VGA_GFX_PLANE_READ);
70*4882a593Smuzhiyun gr5 = vga_rgfx(state->vgabase, VGA_GFX_MODE);
71*4882a593Smuzhiyun gr6 = vga_rgfx(state->vgabase, VGA_GFX_MISC);
72*4882a593Smuzhiyun seq2 = vga_rseq(state->vgabase, VGA_SEQ_PLANE_WRITE);
73*4882a593Smuzhiyun seq4 = vga_rseq(state->vgabase, VGA_SEQ_MEMORY_MODE);
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun /* blank screen */
76*4882a593Smuzhiyun seq1 = vga_rseq(state->vgabase, VGA_SEQ_CLOCK_MODE);
77*4882a593Smuzhiyun vga_wseq(state->vgabase, VGA_SEQ_RESET, 0x1);
78*4882a593Smuzhiyun vga_wseq(state->vgabase, VGA_SEQ_CLOCK_MODE, seq1 | 1 << 5);
79*4882a593Smuzhiyun vga_wseq(state->vgabase, VGA_SEQ_RESET, 0x3);
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun /* save font at plane 2 */
82*4882a593Smuzhiyun if (state->flags & VGA_SAVE_FONT0) {
83*4882a593Smuzhiyun vga_wseq(state->vgabase, VGA_SEQ_PLANE_WRITE, 0x4);
84*4882a593Smuzhiyun vga_wseq(state->vgabase, VGA_SEQ_MEMORY_MODE, 0x6);
85*4882a593Smuzhiyun vga_wgfx(state->vgabase, VGA_GFX_PLANE_READ, 0x2);
86*4882a593Smuzhiyun vga_wgfx(state->vgabase, VGA_GFX_MODE, 0x0);
87*4882a593Smuzhiyun vga_wgfx(state->vgabase, VGA_GFX_MISC, 0x5);
88*4882a593Smuzhiyun for (i = 0; i < 4 * 8192; i++)
89*4882a593Smuzhiyun saved->vga_font0[i] = vga_r(fbbase, i);
90*4882a593Smuzhiyun }
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun /* save font at plane 3 */
93*4882a593Smuzhiyun if (state->flags & VGA_SAVE_FONT1) {
94*4882a593Smuzhiyun vga_wseq(state->vgabase, VGA_SEQ_PLANE_WRITE, 0x8);
95*4882a593Smuzhiyun vga_wseq(state->vgabase, VGA_SEQ_MEMORY_MODE, 0x6);
96*4882a593Smuzhiyun vga_wgfx(state->vgabase, VGA_GFX_PLANE_READ, 0x3);
97*4882a593Smuzhiyun vga_wgfx(state->vgabase, VGA_GFX_MODE, 0x0);
98*4882a593Smuzhiyun vga_wgfx(state->vgabase, VGA_GFX_MISC, 0x5);
99*4882a593Smuzhiyun for (i = 0; i < state->memsize; i++)
100*4882a593Smuzhiyun saved->vga_font1[i] = vga_r(fbbase, i);
101*4882a593Smuzhiyun }
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun /* save font at plane 0/1 */
104*4882a593Smuzhiyun if (state->flags & VGA_SAVE_TEXT) {
105*4882a593Smuzhiyun vga_wseq(state->vgabase, VGA_SEQ_PLANE_WRITE, 0x1);
106*4882a593Smuzhiyun vga_wseq(state->vgabase, VGA_SEQ_MEMORY_MODE, 0x6);
107*4882a593Smuzhiyun vga_wgfx(state->vgabase, VGA_GFX_PLANE_READ, 0x0);
108*4882a593Smuzhiyun vga_wgfx(state->vgabase, VGA_GFX_MODE, 0x0);
109*4882a593Smuzhiyun vga_wgfx(state->vgabase, VGA_GFX_MISC, 0x5);
110*4882a593Smuzhiyun for (i = 0; i < 8192; i++)
111*4882a593Smuzhiyun saved->vga_text[i] = vga_r(fbbase, i);
112*4882a593Smuzhiyun
113*4882a593Smuzhiyun vga_wseq(state->vgabase, VGA_SEQ_PLANE_WRITE, 0x2);
114*4882a593Smuzhiyun vga_wseq(state->vgabase, VGA_SEQ_MEMORY_MODE, 0x6);
115*4882a593Smuzhiyun vga_wgfx(state->vgabase, VGA_GFX_PLANE_READ, 0x1);
116*4882a593Smuzhiyun vga_wgfx(state->vgabase, VGA_GFX_MODE, 0x0);
117*4882a593Smuzhiyun vga_wgfx(state->vgabase, VGA_GFX_MISC, 0x5);
118*4882a593Smuzhiyun for (i = 0; i < 8192; i++)
119*4882a593Smuzhiyun saved->vga_text[8192+i] = vga_r(fbbase + 2 * 8192, i);
120*4882a593Smuzhiyun }
121*4882a593Smuzhiyun
122*4882a593Smuzhiyun /* restore regs */
123*4882a593Smuzhiyun vga_wseq(state->vgabase, VGA_SEQ_PLANE_WRITE, seq2);
124*4882a593Smuzhiyun vga_wseq(state->vgabase, VGA_SEQ_MEMORY_MODE, seq4);
125*4882a593Smuzhiyun
126*4882a593Smuzhiyun vga_wgfx(state->vgabase, VGA_GFX_PLANE_READ, gr4);
127*4882a593Smuzhiyun vga_wgfx(state->vgabase, VGA_GFX_MODE, gr5);
128*4882a593Smuzhiyun vga_wgfx(state->vgabase, VGA_GFX_MISC, gr6);
129*4882a593Smuzhiyun
130*4882a593Smuzhiyun /* unblank screen */
131*4882a593Smuzhiyun vga_wseq(state->vgabase, VGA_SEQ_RESET, 0x1);
132*4882a593Smuzhiyun vga_wseq(state->vgabase, VGA_SEQ_CLOCK_MODE, seq1 & ~(1 << 5));
133*4882a593Smuzhiyun vga_wseq(state->vgabase, VGA_SEQ_RESET, 0x3);
134*4882a593Smuzhiyun
135*4882a593Smuzhiyun vga_wseq(state->vgabase, VGA_SEQ_CLOCK_MODE, seq1);
136*4882a593Smuzhiyun }
137*4882a593Smuzhiyun
restore_vga_text(struct vgastate * state,void __iomem * fbbase)138*4882a593Smuzhiyun static void restore_vga_text(struct vgastate *state, void __iomem *fbbase)
139*4882a593Smuzhiyun {
140*4882a593Smuzhiyun struct regstate *saved = (struct regstate *) state->vidstate;
141*4882a593Smuzhiyun int i;
142*4882a593Smuzhiyun u8 gr1, gr3, gr4, gr5, gr6, gr8;
143*4882a593Smuzhiyun u8 seq1, seq2, seq4;
144*4882a593Smuzhiyun
145*4882a593Smuzhiyun /* save regs */
146*4882a593Smuzhiyun gr1 = vga_rgfx(state->vgabase, VGA_GFX_SR_ENABLE);
147*4882a593Smuzhiyun gr3 = vga_rgfx(state->vgabase, VGA_GFX_DATA_ROTATE);
148*4882a593Smuzhiyun gr4 = vga_rgfx(state->vgabase, VGA_GFX_PLANE_READ);
149*4882a593Smuzhiyun gr5 = vga_rgfx(state->vgabase, VGA_GFX_MODE);
150*4882a593Smuzhiyun gr6 = vga_rgfx(state->vgabase, VGA_GFX_MISC);
151*4882a593Smuzhiyun gr8 = vga_rgfx(state->vgabase, VGA_GFX_BIT_MASK);
152*4882a593Smuzhiyun seq2 = vga_rseq(state->vgabase, VGA_SEQ_PLANE_WRITE);
153*4882a593Smuzhiyun seq4 = vga_rseq(state->vgabase, VGA_SEQ_MEMORY_MODE);
154*4882a593Smuzhiyun
155*4882a593Smuzhiyun /* blank screen */
156*4882a593Smuzhiyun seq1 = vga_rseq(state->vgabase, VGA_SEQ_CLOCK_MODE);
157*4882a593Smuzhiyun vga_wseq(state->vgabase, VGA_SEQ_RESET, 0x1);
158*4882a593Smuzhiyun vga_wseq(state->vgabase, VGA_SEQ_CLOCK_MODE, seq1 | 1 << 5);
159*4882a593Smuzhiyun vga_wseq(state->vgabase, VGA_SEQ_RESET, 0x3);
160*4882a593Smuzhiyun
161*4882a593Smuzhiyun if (state->depth == 4) {
162*4882a593Smuzhiyun vga_wgfx(state->vgabase, VGA_GFX_DATA_ROTATE, 0x0);
163*4882a593Smuzhiyun vga_wgfx(state->vgabase, VGA_GFX_BIT_MASK, 0xff);
164*4882a593Smuzhiyun vga_wgfx(state->vgabase, VGA_GFX_SR_ENABLE, 0x00);
165*4882a593Smuzhiyun }
166*4882a593Smuzhiyun
167*4882a593Smuzhiyun /* restore font at plane 2 */
168*4882a593Smuzhiyun if (state->flags & VGA_SAVE_FONT0) {
169*4882a593Smuzhiyun vga_wseq(state->vgabase, VGA_SEQ_PLANE_WRITE, 0x4);
170*4882a593Smuzhiyun vga_wseq(state->vgabase, VGA_SEQ_MEMORY_MODE, 0x6);
171*4882a593Smuzhiyun vga_wgfx(state->vgabase, VGA_GFX_PLANE_READ, 0x2);
172*4882a593Smuzhiyun vga_wgfx(state->vgabase, VGA_GFX_MODE, 0x0);
173*4882a593Smuzhiyun vga_wgfx(state->vgabase, VGA_GFX_MISC, 0x5);
174*4882a593Smuzhiyun for (i = 0; i < 4 * 8192; i++)
175*4882a593Smuzhiyun vga_w(fbbase, i, saved->vga_font0[i]);
176*4882a593Smuzhiyun }
177*4882a593Smuzhiyun
178*4882a593Smuzhiyun /* restore font at plane 3 */
179*4882a593Smuzhiyun if (state->flags & VGA_SAVE_FONT1) {
180*4882a593Smuzhiyun vga_wseq(state->vgabase, VGA_SEQ_PLANE_WRITE, 0x8);
181*4882a593Smuzhiyun vga_wseq(state->vgabase, VGA_SEQ_MEMORY_MODE, 0x6);
182*4882a593Smuzhiyun vga_wgfx(state->vgabase, VGA_GFX_PLANE_READ, 0x3);
183*4882a593Smuzhiyun vga_wgfx(state->vgabase, VGA_GFX_MODE, 0x0);
184*4882a593Smuzhiyun vga_wgfx(state->vgabase, VGA_GFX_MISC, 0x5);
185*4882a593Smuzhiyun for (i = 0; i < state->memsize; i++)
186*4882a593Smuzhiyun vga_w(fbbase, i, saved->vga_font1[i]);
187*4882a593Smuzhiyun }
188*4882a593Smuzhiyun
189*4882a593Smuzhiyun /* restore font at plane 0/1 */
190*4882a593Smuzhiyun if (state->flags & VGA_SAVE_TEXT) {
191*4882a593Smuzhiyun vga_wseq(state->vgabase, VGA_SEQ_PLANE_WRITE, 0x1);
192*4882a593Smuzhiyun vga_wseq(state->vgabase, VGA_SEQ_MEMORY_MODE, 0x6);
193*4882a593Smuzhiyun vga_wgfx(state->vgabase, VGA_GFX_PLANE_READ, 0x0);
194*4882a593Smuzhiyun vga_wgfx(state->vgabase, VGA_GFX_MODE, 0x0);
195*4882a593Smuzhiyun vga_wgfx(state->vgabase, VGA_GFX_MISC, 0x5);
196*4882a593Smuzhiyun for (i = 0; i < 8192; i++)
197*4882a593Smuzhiyun vga_w(fbbase, i, saved->vga_text[i]);
198*4882a593Smuzhiyun
199*4882a593Smuzhiyun vga_wseq(state->vgabase, VGA_SEQ_PLANE_WRITE, 0x2);
200*4882a593Smuzhiyun vga_wseq(state->vgabase, VGA_SEQ_MEMORY_MODE, 0x6);
201*4882a593Smuzhiyun vga_wgfx(state->vgabase, VGA_GFX_PLANE_READ, 0x1);
202*4882a593Smuzhiyun vga_wgfx(state->vgabase, VGA_GFX_MODE, 0x0);
203*4882a593Smuzhiyun vga_wgfx(state->vgabase, VGA_GFX_MISC, 0x5);
204*4882a593Smuzhiyun for (i = 0; i < 8192; i++)
205*4882a593Smuzhiyun vga_w(fbbase, i, saved->vga_text[8192+i]);
206*4882a593Smuzhiyun }
207*4882a593Smuzhiyun
208*4882a593Smuzhiyun /* unblank screen */
209*4882a593Smuzhiyun vga_wseq(state->vgabase, VGA_SEQ_RESET, 0x1);
210*4882a593Smuzhiyun vga_wseq(state->vgabase, VGA_SEQ_CLOCK_MODE, seq1 & ~(1 << 5));
211*4882a593Smuzhiyun vga_wseq(state->vgabase, VGA_SEQ_RESET, 0x3);
212*4882a593Smuzhiyun
213*4882a593Smuzhiyun /* restore regs */
214*4882a593Smuzhiyun vga_wgfx(state->vgabase, VGA_GFX_SR_ENABLE, gr1);
215*4882a593Smuzhiyun vga_wgfx(state->vgabase, VGA_GFX_DATA_ROTATE, gr3);
216*4882a593Smuzhiyun vga_wgfx(state->vgabase, VGA_GFX_PLANE_READ, gr4);
217*4882a593Smuzhiyun vga_wgfx(state->vgabase, VGA_GFX_MODE, gr5);
218*4882a593Smuzhiyun vga_wgfx(state->vgabase, VGA_GFX_MISC, gr6);
219*4882a593Smuzhiyun vga_wgfx(state->vgabase, VGA_GFX_BIT_MASK, gr8);
220*4882a593Smuzhiyun
221*4882a593Smuzhiyun vga_wseq(state->vgabase, VGA_SEQ_CLOCK_MODE, seq1);
222*4882a593Smuzhiyun vga_wseq(state->vgabase, VGA_SEQ_PLANE_WRITE, seq2);
223*4882a593Smuzhiyun vga_wseq(state->vgabase, VGA_SEQ_MEMORY_MODE, seq4);
224*4882a593Smuzhiyun }
225*4882a593Smuzhiyun
save_vga_mode(struct vgastate * state)226*4882a593Smuzhiyun static void save_vga_mode(struct vgastate *state)
227*4882a593Smuzhiyun {
228*4882a593Smuzhiyun struct regstate *saved = (struct regstate *) state->vidstate;
229*4882a593Smuzhiyun unsigned short iobase;
230*4882a593Smuzhiyun int i;
231*4882a593Smuzhiyun
232*4882a593Smuzhiyun saved->misc = vga_r(state->vgabase, VGA_MIS_R);
233*4882a593Smuzhiyun if (saved->misc & 1)
234*4882a593Smuzhiyun iobase = 0x3d0;
235*4882a593Smuzhiyun else
236*4882a593Smuzhiyun iobase = 0x3b0;
237*4882a593Smuzhiyun
238*4882a593Smuzhiyun for (i = 0; i < state->num_crtc; i++)
239*4882a593Smuzhiyun saved->crtc[i] = vga_rcrtcs(state->vgabase, iobase, i);
240*4882a593Smuzhiyun
241*4882a593Smuzhiyun vga_r(state->vgabase, iobase + 0xa);
242*4882a593Smuzhiyun vga_w(state->vgabase, VGA_ATT_W, 0x00);
243*4882a593Smuzhiyun for (i = 0; i < state->num_attr; i++) {
244*4882a593Smuzhiyun vga_r(state->vgabase, iobase + 0xa);
245*4882a593Smuzhiyun saved->attr[i] = vga_rattr(state->vgabase, i);
246*4882a593Smuzhiyun }
247*4882a593Smuzhiyun vga_r(state->vgabase, iobase + 0xa);
248*4882a593Smuzhiyun vga_w(state->vgabase, VGA_ATT_W, 0x20);
249*4882a593Smuzhiyun
250*4882a593Smuzhiyun for (i = 0; i < state->num_gfx; i++)
251*4882a593Smuzhiyun saved->gfx[i] = vga_rgfx(state->vgabase, i);
252*4882a593Smuzhiyun
253*4882a593Smuzhiyun for (i = 0; i < state->num_seq; i++)
254*4882a593Smuzhiyun saved->seq[i] = vga_rseq(state->vgabase, i);
255*4882a593Smuzhiyun }
256*4882a593Smuzhiyun
restore_vga_mode(struct vgastate * state)257*4882a593Smuzhiyun static void restore_vga_mode(struct vgastate *state)
258*4882a593Smuzhiyun {
259*4882a593Smuzhiyun struct regstate *saved = (struct regstate *) state->vidstate;
260*4882a593Smuzhiyun unsigned short iobase;
261*4882a593Smuzhiyun int i;
262*4882a593Smuzhiyun
263*4882a593Smuzhiyun vga_w(state->vgabase, VGA_MIS_W, saved->misc);
264*4882a593Smuzhiyun
265*4882a593Smuzhiyun if (saved->misc & 1)
266*4882a593Smuzhiyun iobase = 0x3d0;
267*4882a593Smuzhiyun else
268*4882a593Smuzhiyun iobase = 0x3b0;
269*4882a593Smuzhiyun
270*4882a593Smuzhiyun /* turn off display */
271*4882a593Smuzhiyun vga_wseq(state->vgabase, VGA_SEQ_CLOCK_MODE,
272*4882a593Smuzhiyun saved->seq[VGA_SEQ_CLOCK_MODE] | 0x20);
273*4882a593Smuzhiyun
274*4882a593Smuzhiyun /* disable sequencer */
275*4882a593Smuzhiyun vga_wseq(state->vgabase, VGA_SEQ_RESET, 0x01);
276*4882a593Smuzhiyun
277*4882a593Smuzhiyun /* enable palette addressing */
278*4882a593Smuzhiyun vga_r(state->vgabase, iobase + 0xa);
279*4882a593Smuzhiyun vga_w(state->vgabase, VGA_ATT_W, 0x00);
280*4882a593Smuzhiyun
281*4882a593Smuzhiyun for (i = 2; i < state->num_seq; i++)
282*4882a593Smuzhiyun vga_wseq(state->vgabase, i, saved->seq[i]);
283*4882a593Smuzhiyun
284*4882a593Smuzhiyun
285*4882a593Smuzhiyun /* unprotect vga regs */
286*4882a593Smuzhiyun vga_wcrtcs(state->vgabase, iobase, 17, saved->crtc[17] & ~0x80);
287*4882a593Smuzhiyun for (i = 0; i < state->num_crtc; i++)
288*4882a593Smuzhiyun vga_wcrtcs(state->vgabase, iobase, i, saved->crtc[i]);
289*4882a593Smuzhiyun
290*4882a593Smuzhiyun for (i = 0; i < state->num_gfx; i++)
291*4882a593Smuzhiyun vga_wgfx(state->vgabase, i, saved->gfx[i]);
292*4882a593Smuzhiyun
293*4882a593Smuzhiyun for (i = 0; i < state->num_attr; i++) {
294*4882a593Smuzhiyun vga_r(state->vgabase, iobase + 0xa);
295*4882a593Smuzhiyun vga_wattr(state->vgabase, i, saved->attr[i]);
296*4882a593Smuzhiyun }
297*4882a593Smuzhiyun
298*4882a593Smuzhiyun /* reenable sequencer */
299*4882a593Smuzhiyun vga_wseq(state->vgabase, VGA_SEQ_RESET, 0x03);
300*4882a593Smuzhiyun /* turn display on */
301*4882a593Smuzhiyun vga_wseq(state->vgabase, VGA_SEQ_CLOCK_MODE,
302*4882a593Smuzhiyun saved->seq[VGA_SEQ_CLOCK_MODE] & ~(1 << 5));
303*4882a593Smuzhiyun
304*4882a593Smuzhiyun /* disable video/palette source */
305*4882a593Smuzhiyun vga_r(state->vgabase, iobase + 0xa);
306*4882a593Smuzhiyun vga_w(state->vgabase, VGA_ATT_W, 0x20);
307*4882a593Smuzhiyun }
308*4882a593Smuzhiyun
save_vga_cmap(struct vgastate * state)309*4882a593Smuzhiyun static void save_vga_cmap(struct vgastate *state)
310*4882a593Smuzhiyun {
311*4882a593Smuzhiyun struct regstate *saved = (struct regstate *) state->vidstate;
312*4882a593Smuzhiyun int i;
313*4882a593Smuzhiyun
314*4882a593Smuzhiyun vga_w(state->vgabase, VGA_PEL_MSK, 0xff);
315*4882a593Smuzhiyun
316*4882a593Smuzhiyun /* assumes DAC is readable and writable */
317*4882a593Smuzhiyun vga_w(state->vgabase, VGA_PEL_IR, 0x00);
318*4882a593Smuzhiyun for (i = 0; i < 768; i++)
319*4882a593Smuzhiyun saved->vga_cmap[i] = vga_r(state->vgabase, VGA_PEL_D);
320*4882a593Smuzhiyun }
321*4882a593Smuzhiyun
restore_vga_cmap(struct vgastate * state)322*4882a593Smuzhiyun static void restore_vga_cmap(struct vgastate *state)
323*4882a593Smuzhiyun {
324*4882a593Smuzhiyun struct regstate *saved = (struct regstate *) state->vidstate;
325*4882a593Smuzhiyun int i;
326*4882a593Smuzhiyun
327*4882a593Smuzhiyun vga_w(state->vgabase, VGA_PEL_MSK, 0xff);
328*4882a593Smuzhiyun
329*4882a593Smuzhiyun /* assumes DAC is readable and writable */
330*4882a593Smuzhiyun vga_w(state->vgabase, VGA_PEL_IW, 0x00);
331*4882a593Smuzhiyun for (i = 0; i < 768; i++)
332*4882a593Smuzhiyun vga_w(state->vgabase, VGA_PEL_D, saved->vga_cmap[i]);
333*4882a593Smuzhiyun }
334*4882a593Smuzhiyun
vga_cleanup(struct vgastate * state)335*4882a593Smuzhiyun static void vga_cleanup(struct vgastate *state)
336*4882a593Smuzhiyun {
337*4882a593Smuzhiyun if (state->vidstate != NULL) {
338*4882a593Smuzhiyun struct regstate *saved = (struct regstate *) state->vidstate;
339*4882a593Smuzhiyun
340*4882a593Smuzhiyun vfree(saved->vga_font0);
341*4882a593Smuzhiyun vfree(saved->vga_font1);
342*4882a593Smuzhiyun vfree(saved->vga_text);
343*4882a593Smuzhiyun vfree(saved->vga_cmap);
344*4882a593Smuzhiyun vfree(saved->attr);
345*4882a593Smuzhiyun kfree(saved);
346*4882a593Smuzhiyun state->vidstate = NULL;
347*4882a593Smuzhiyun }
348*4882a593Smuzhiyun }
349*4882a593Smuzhiyun
save_vga(struct vgastate * state)350*4882a593Smuzhiyun int save_vga(struct vgastate *state)
351*4882a593Smuzhiyun {
352*4882a593Smuzhiyun struct regstate *saved;
353*4882a593Smuzhiyun
354*4882a593Smuzhiyun saved = kzalloc(sizeof(struct regstate), GFP_KERNEL);
355*4882a593Smuzhiyun
356*4882a593Smuzhiyun if (saved == NULL)
357*4882a593Smuzhiyun return 1;
358*4882a593Smuzhiyun
359*4882a593Smuzhiyun state->vidstate = (void *)saved;
360*4882a593Smuzhiyun
361*4882a593Smuzhiyun if (state->flags & VGA_SAVE_CMAP) {
362*4882a593Smuzhiyun saved->vga_cmap = vmalloc(768);
363*4882a593Smuzhiyun if (!saved->vga_cmap) {
364*4882a593Smuzhiyun vga_cleanup(state);
365*4882a593Smuzhiyun return 1;
366*4882a593Smuzhiyun }
367*4882a593Smuzhiyun save_vga_cmap(state);
368*4882a593Smuzhiyun }
369*4882a593Smuzhiyun
370*4882a593Smuzhiyun if (state->flags & VGA_SAVE_MODE) {
371*4882a593Smuzhiyun int total;
372*4882a593Smuzhiyun
373*4882a593Smuzhiyun if (state->num_attr < 21)
374*4882a593Smuzhiyun state->num_attr = 21;
375*4882a593Smuzhiyun if (state->num_crtc < 25)
376*4882a593Smuzhiyun state->num_crtc = 25;
377*4882a593Smuzhiyun if (state->num_gfx < 9)
378*4882a593Smuzhiyun state->num_gfx = 9;
379*4882a593Smuzhiyun if (state->num_seq < 5)
380*4882a593Smuzhiyun state->num_seq = 5;
381*4882a593Smuzhiyun total = state->num_attr + state->num_crtc +
382*4882a593Smuzhiyun state->num_gfx + state->num_seq;
383*4882a593Smuzhiyun
384*4882a593Smuzhiyun saved->attr = vmalloc(total);
385*4882a593Smuzhiyun if (!saved->attr) {
386*4882a593Smuzhiyun vga_cleanup(state);
387*4882a593Smuzhiyun return 1;
388*4882a593Smuzhiyun }
389*4882a593Smuzhiyun saved->crtc = saved->attr + state->num_attr;
390*4882a593Smuzhiyun saved->gfx = saved->crtc + state->num_crtc;
391*4882a593Smuzhiyun saved->seq = saved->gfx + state->num_gfx;
392*4882a593Smuzhiyun
393*4882a593Smuzhiyun save_vga_mode(state);
394*4882a593Smuzhiyun }
395*4882a593Smuzhiyun
396*4882a593Smuzhiyun if (state->flags & VGA_SAVE_FONTS) {
397*4882a593Smuzhiyun void __iomem *fbbase;
398*4882a593Smuzhiyun
399*4882a593Smuzhiyun /* exit if window is less than 32K */
400*4882a593Smuzhiyun if (state->memsize && state->memsize < 4 * 8192) {
401*4882a593Smuzhiyun vga_cleanup(state);
402*4882a593Smuzhiyun return 1;
403*4882a593Smuzhiyun }
404*4882a593Smuzhiyun if (!state->memsize)
405*4882a593Smuzhiyun state->memsize = 8 * 8192;
406*4882a593Smuzhiyun
407*4882a593Smuzhiyun if (!state->membase)
408*4882a593Smuzhiyun state->membase = 0xA0000;
409*4882a593Smuzhiyun
410*4882a593Smuzhiyun fbbase = ioremap(state->membase, state->memsize);
411*4882a593Smuzhiyun
412*4882a593Smuzhiyun if (!fbbase) {
413*4882a593Smuzhiyun vga_cleanup(state);
414*4882a593Smuzhiyun return 1;
415*4882a593Smuzhiyun }
416*4882a593Smuzhiyun
417*4882a593Smuzhiyun /*
418*4882a593Smuzhiyun * save only first 32K used by vgacon
419*4882a593Smuzhiyun */
420*4882a593Smuzhiyun if (state->flags & VGA_SAVE_FONT0) {
421*4882a593Smuzhiyun saved->vga_font0 = vmalloc(4 * 8192);
422*4882a593Smuzhiyun if (!saved->vga_font0) {
423*4882a593Smuzhiyun iounmap(fbbase);
424*4882a593Smuzhiyun vga_cleanup(state);
425*4882a593Smuzhiyun return 1;
426*4882a593Smuzhiyun }
427*4882a593Smuzhiyun }
428*4882a593Smuzhiyun /*
429*4882a593Smuzhiyun * largely unused, but if required by the caller
430*4882a593Smuzhiyun * we'll just save everything.
431*4882a593Smuzhiyun */
432*4882a593Smuzhiyun if (state->flags & VGA_SAVE_FONT1) {
433*4882a593Smuzhiyun saved->vga_font1 = vmalloc(state->memsize);
434*4882a593Smuzhiyun if (!saved->vga_font1) {
435*4882a593Smuzhiyun iounmap(fbbase);
436*4882a593Smuzhiyun vga_cleanup(state);
437*4882a593Smuzhiyun return 1;
438*4882a593Smuzhiyun }
439*4882a593Smuzhiyun }
440*4882a593Smuzhiyun /*
441*4882a593Smuzhiyun * Save 8K at plane0[0], and 8K at plane1[16K]
442*4882a593Smuzhiyun */
443*4882a593Smuzhiyun if (state->flags & VGA_SAVE_TEXT) {
444*4882a593Smuzhiyun saved->vga_text = vmalloc(8192 * 2);
445*4882a593Smuzhiyun if (!saved->vga_text) {
446*4882a593Smuzhiyun iounmap(fbbase);
447*4882a593Smuzhiyun vga_cleanup(state);
448*4882a593Smuzhiyun return 1;
449*4882a593Smuzhiyun }
450*4882a593Smuzhiyun }
451*4882a593Smuzhiyun
452*4882a593Smuzhiyun save_vga_text(state, fbbase);
453*4882a593Smuzhiyun iounmap(fbbase);
454*4882a593Smuzhiyun }
455*4882a593Smuzhiyun return 0;
456*4882a593Smuzhiyun }
457*4882a593Smuzhiyun
restore_vga(struct vgastate * state)458*4882a593Smuzhiyun int restore_vga(struct vgastate *state)
459*4882a593Smuzhiyun {
460*4882a593Smuzhiyun if (state->vidstate == NULL)
461*4882a593Smuzhiyun return 1;
462*4882a593Smuzhiyun
463*4882a593Smuzhiyun if (state->flags & VGA_SAVE_MODE)
464*4882a593Smuzhiyun restore_vga_mode(state);
465*4882a593Smuzhiyun
466*4882a593Smuzhiyun if (state->flags & VGA_SAVE_FONTS) {
467*4882a593Smuzhiyun void __iomem *fbbase = ioremap(state->membase, state->memsize);
468*4882a593Smuzhiyun
469*4882a593Smuzhiyun if (!fbbase) {
470*4882a593Smuzhiyun vga_cleanup(state);
471*4882a593Smuzhiyun return 1;
472*4882a593Smuzhiyun }
473*4882a593Smuzhiyun restore_vga_text(state, fbbase);
474*4882a593Smuzhiyun iounmap(fbbase);
475*4882a593Smuzhiyun }
476*4882a593Smuzhiyun
477*4882a593Smuzhiyun if (state->flags & VGA_SAVE_CMAP)
478*4882a593Smuzhiyun restore_vga_cmap(state);
479*4882a593Smuzhiyun
480*4882a593Smuzhiyun vga_cleanup(state);
481*4882a593Smuzhiyun return 0;
482*4882a593Smuzhiyun }
483*4882a593Smuzhiyun
484*4882a593Smuzhiyun EXPORT_SYMBOL(save_vga);
485*4882a593Smuzhiyun EXPORT_SYMBOL(restore_vga);
486*4882a593Smuzhiyun
487*4882a593Smuzhiyun MODULE_AUTHOR("James Simmons <jsimmons@users.sf.net>");
488*4882a593Smuzhiyun MODULE_DESCRIPTION("VGA State Save/Restore");
489*4882a593Smuzhiyun MODULE_LICENSE("GPL");
490*4882a593Smuzhiyun
491