1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Rockchip Vehicle driver 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2022 Rockchip Electronics Co., Ltd. 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun #ifndef __VEHICLE_CIF_H 8*4882a593Smuzhiyun #define __VEHICLE_CIF_H 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #include "vehicle_cfg.h" 11*4882a593Smuzhiyun #include "vehicle_cif_regs.h" 12*4882a593Smuzhiyun #include "../../../media/platform/rockchip/cif/dev.h" 13*4882a593Smuzhiyun #include <linux/dma-mapping.h> 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun enum vehicle_rkcif_chip_id { 16*4882a593Smuzhiyun CHIP_RK3568_VEHICLE_CIF = 0x0, 17*4882a593Smuzhiyun CHIP_RK3588_VEHICLE_CIF, 18*4882a593Smuzhiyun CHIP_RK3562_VEHICLE_CIF, 19*4882a593Smuzhiyun }; 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun enum rkcif_csi_host_idx { 22*4882a593Smuzhiyun RKCIF_MIPI0_CSI2 = 0x0, 23*4882a593Smuzhiyun RKCIF_MIPI1_CSI2, 24*4882a593Smuzhiyun RKCIF_MIPI2_CSI2, 25*4882a593Smuzhiyun RKCIF_MIPI3_CSI2, 26*4882a593Smuzhiyun RKCIF_MIPI4_CSI2, 27*4882a593Smuzhiyun RKCIF_MIPI5_CSI2, 28*4882a593Smuzhiyun }; 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun struct vehicle_rkcif_dummy_buffer { 31*4882a593Smuzhiyun void *vaddr; 32*4882a593Smuzhiyun dma_addr_t dma_addr; 33*4882a593Smuzhiyun u32 size; 34*4882a593Smuzhiyun }; 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun struct rk_cif_clk { 37*4882a593Smuzhiyun /************clk************/ 38*4882a593Smuzhiyun struct clk *clks[RKCIF_MAX_BUS_CLK]; 39*4882a593Smuzhiyun struct clk *xvclk; 40*4882a593Smuzhiyun int clks_num; 41*4882a593Smuzhiyun /************reset************/ 42*4882a593Smuzhiyun struct reset_control *cif_rst[RKCIF_MAX_RESET]; 43*4882a593Smuzhiyun int rsts_num; 44*4882a593Smuzhiyun /* spinlock_t lock; */ 45*4882a593Smuzhiyun bool on; 46*4882a593Smuzhiyun }; 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun struct rk_cif_irqinfo { 49*4882a593Smuzhiyun unsigned int irq; 50*4882a593Smuzhiyun unsigned long cifirq_idx; 51*4882a593Smuzhiyun unsigned long cifirq_normal_idx; 52*4882a593Smuzhiyun unsigned long cifirq_abnormal_idx; 53*4882a593Smuzhiyun unsigned long dmairq_idx; 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun /* @csi_overflow_cnt: count of csi overflow irq 56*4882a593Smuzhiyun * @csi_bwidth_lack_cnt: count of csi bandwidth lack irq 57*4882a593Smuzhiyun * @dvp_bus_err_cnt: count of dvp bus err irq 58*4882a593Smuzhiyun * @dvp_overflow_cnt: count dvp overflow irq 59*4882a593Smuzhiyun * @dvp_line_err_cnt: count dvp line err irq 60*4882a593Smuzhiyun * @dvp_pix_err_cnt: count dvp pix err irq 61*4882a593Smuzhiyun * @all_frm_end_cnt: raw frame end count 62*4882a593Smuzhiyun * @all_err_cnt: all err count 63*4882a593Smuzhiyun * @ 64*4882a593Smuzhiyun */ 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun u64 csi_overflow_cnt; 67*4882a593Smuzhiyun u64 csi_bwidth_lack_cnt; 68*4882a593Smuzhiyun u64 dvp_bus_err_cnt; 69*4882a593Smuzhiyun u64 dvp_overflow_cnt; 70*4882a593Smuzhiyun u64 dvp_line_err_cnt; 71*4882a593Smuzhiyun u64 dvp_pix_err_cnt; 72*4882a593Smuzhiyun u64 all_frm_end_cnt; 73*4882a593Smuzhiyun u64 all_err_cnt; 74*4882a593Smuzhiyun u64 dvp_size_err_cnt; 75*4882a593Smuzhiyun u64 dvp_bwidth_lack_cnt; 76*4882a593Smuzhiyun u64 csi_size_err_cnt; 77*4882a593Smuzhiyun }; 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun #define RKCIF_MAX_CSI_CHANNEL 4 80*4882a593Smuzhiyun struct vehicle_csi_channel_info { 81*4882a593Smuzhiyun unsigned char id; 82*4882a593Smuzhiyun unsigned char enable; /* capture enable */ 83*4882a593Smuzhiyun unsigned char vc; 84*4882a593Smuzhiyun unsigned char data_type; 85*4882a593Smuzhiyun unsigned char crop_en; 86*4882a593Smuzhiyun unsigned char cmd_mode_en; 87*4882a593Smuzhiyun unsigned char fmt_val; 88*4882a593Smuzhiyun unsigned int width; 89*4882a593Smuzhiyun unsigned int height; 90*4882a593Smuzhiyun unsigned int virtual_width; 91*4882a593Smuzhiyun unsigned int crop_st_x; 92*4882a593Smuzhiyun unsigned int crop_st_y; 93*4882a593Smuzhiyun }; 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun struct vehicle_csi2_err_state_work { 96*4882a593Smuzhiyun struct workqueue_struct *err_print_wq; 97*4882a593Smuzhiyun struct work_struct work; 98*4882a593Smuzhiyun char err_str[CSI_ERRSTR_LEN]; 99*4882a593Smuzhiyun u32 err_val; 100*4882a593Smuzhiyun u32 err_num; 101*4882a593Smuzhiyun unsigned long err_stat; 102*4882a593Smuzhiyun }; 103*4882a593Smuzhiyun 104*4882a593Smuzhiyun struct vehicle_cif { 105*4882a593Smuzhiyun struct device *dev; 106*4882a593Smuzhiyun struct device_node *phy_node; 107*4882a593Smuzhiyun struct rk_cif_clk clk; 108*4882a593Smuzhiyun struct vehicle_cfg cif_cfg; 109*4882a593Smuzhiyun char *base; /*cif base addr*/ 110*4882a593Smuzhiyun //unsigned long cru_base; 111*4882a593Smuzhiyun //unsigned long grf_base; 112*4882a593Smuzhiyun void __iomem *cru_base; /*cru base addr*/ 113*4882a593Smuzhiyun void __iomem *grf_base; /*grf base addr*/ 114*4882a593Smuzhiyun void __iomem *csi2_dphy_base; /*csi2_dphy base addr*/ 115*4882a593Smuzhiyun void __iomem *csi2_base; /*csi2 base addr*/ 116*4882a593Smuzhiyun struct delayed_work work; 117*4882a593Smuzhiyun 118*4882a593Smuzhiyun bool is_enabled; 119*4882a593Smuzhiyun u32 frame_buf[MAX_BUF_NUM]; 120*4882a593Smuzhiyun u32 current_buf_index; 121*4882a593Smuzhiyun u32 last_buf_index; 122*4882a593Smuzhiyun u32 active[2]; 123*4882a593Smuzhiyun int irq; 124*4882a593Smuzhiyun int csi2_irq1; 125*4882a593Smuzhiyun int csi2_irq2; 126*4882a593Smuzhiyun int drop_frames; 127*4882a593Smuzhiyun struct rk_cif_irqinfo irqinfo; 128*4882a593Smuzhiyun const struct vehicle_cif_reg *cif_regs; 129*4882a593Smuzhiyun struct regmap *regmap_grf; 130*4882a593Smuzhiyun struct regmap *regmap_dphy_grf; 131*4882a593Smuzhiyun unsigned int frame_idx; 132*4882a593Smuzhiyun struct vehicle_rkcif_dummy_buffer dummy_buf; 133*4882a593Smuzhiyun struct csi2_dphy_hw *dphy_hw; 134*4882a593Smuzhiyun int num_channels; 135*4882a593Smuzhiyun int chip_id; 136*4882a593Smuzhiyun int inf_id; 137*4882a593Smuzhiyun unsigned int csi_host_idx; 138*4882a593Smuzhiyun struct vehicle_csi_channel_info channels[RKCIF_MAX_CSI_CHANNEL]; 139*4882a593Smuzhiyun spinlock_t vbq_lock; /* vfd lock */ 140*4882a593Smuzhiyun bool interlaced_enable; 141*4882a593Smuzhiyun unsigned int interlaced_offset; 142*4882a593Smuzhiyun unsigned int interlaced_counts; 143*4882a593Smuzhiyun unsigned long *interlaced_buffer; 144*4882a593Smuzhiyun atomic_t reset_status; 145*4882a593Smuzhiyun wait_queue_head_t wq_stopped; 146*4882a593Smuzhiyun bool stopping; 147*4882a593Smuzhiyun struct mutex stream_lock; 148*4882a593Smuzhiyun enum rkcif_state state; 149*4882a593Smuzhiyun struct vehicle_csi2_err_state_work err_state; 150*4882a593Smuzhiyun }; 151*4882a593Smuzhiyun 152*4882a593Smuzhiyun int vehicle_cif_init_mclk(struct vehicle_cif *cif); 153*4882a593Smuzhiyun int vehicle_cif_init(struct vehicle_cif *cif); 154*4882a593Smuzhiyun int vehicle_cif_deinit(struct vehicle_cif *cif); 155*4882a593Smuzhiyun 156*4882a593Smuzhiyun int vehicle_cif_reverse_open(struct vehicle_cfg *v_cfg); 157*4882a593Smuzhiyun 158*4882a593Smuzhiyun int vehicle_cif_reverse_close(void); 159*4882a593Smuzhiyun int vehicle_wait_cif_reset_done(void); 160*4882a593Smuzhiyun 161*4882a593Smuzhiyun /* CIF IRQ STAT*/ 162*4882a593Smuzhiyun #define DMA_FRAME_END (0x01 << 0) 163*4882a593Smuzhiyun #define LINE_END (0x01 << 1) 164*4882a593Smuzhiyun #define IFIFO_OF (0x01 << 4) 165*4882a593Smuzhiyun #define DFIFO_OF (0x01 << 5) 166*4882a593Smuzhiyun #define PRE_INF_FRAME_END (0x01 << 8) 167*4882a593Smuzhiyun #define PST_INF_FRAME_END (0x01 << 9) 168*4882a593Smuzhiyun 169*4882a593Smuzhiyun enum rk_camera_signal_polarity { 170*4882a593Smuzhiyun RK_CAMERA_DEVICE_SIGNAL_HIGH_LEVEL = 1, 171*4882a593Smuzhiyun RK_CAMERA_DEVICE_SIGNAL_LOW_LEVEL = 0, 172*4882a593Smuzhiyun }; 173*4882a593Smuzhiyun 174*4882a593Smuzhiyun enum rk_camera_device_type { 175*4882a593Smuzhiyun RK_CAMERA_DEVICE_BT601_8 = 0x10000011, 176*4882a593Smuzhiyun RK_CAMERA_DEVICE_BT601_10 = 0x10000012, 177*4882a593Smuzhiyun RK_CAMERA_DEVICE_BT601_12 = 0x10000014, 178*4882a593Smuzhiyun RK_CAMERA_DEVICE_BT601_16 = 0x10000018, 179*4882a593Smuzhiyun 180*4882a593Smuzhiyun RK_CAMERA_DEVICE_BT656_8 = 0x10000021, 181*4882a593Smuzhiyun RK_CAMERA_DEVICE_BT656_10 = 0x10000022, 182*4882a593Smuzhiyun RK_CAMERA_DEVICE_BT656_12 = 0x10000024, 183*4882a593Smuzhiyun RK_CAMERA_DEVICE_BT656_16 = 0x10000028, 184*4882a593Smuzhiyun 185*4882a593Smuzhiyun RK_CAMERA_DEVICE_CVBS_NTSC = 0x20000001, 186*4882a593Smuzhiyun RK_CAMERA_DEVICE_CVBS_PAL = 0x20000002 187*4882a593Smuzhiyun }; 188*4882a593Smuzhiyun 189*4882a593Smuzhiyun #endif 190