1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (C) Rockchip Electronics Co., Ltd. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Author: Huang Lee <Putin.li@rock-chips.com> 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun #ifndef _RVE_DRIVER_H_ 8*4882a593Smuzhiyun #define _RVE_DRIVER_H_ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #include <linux/mutex.h> 11*4882a593Smuzhiyun #include <linux/scatterlist.h> 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun /* Use 'r' as magic number */ 14*4882a593Smuzhiyun #define RVE_IOC_MAGIC 'r' 15*4882a593Smuzhiyun #define RVE_IOW(nr, type) _IOW(RVE_IOC_MAGIC, nr, type) 16*4882a593Smuzhiyun #define RVE_IOR(nr, type) _IOR(RVE_IOC_MAGIC, nr, type) 17*4882a593Smuzhiyun #define RVE_IOWR(nr, type) _IOWR(RVE_IOC_MAGIC, nr, type) 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun #define RVE_IOC_GET_VER RVE_IOR(0x1, struct rve_version_t) 20*4882a593Smuzhiyun #define RVE_IOC_GET_HW_VER RVE_IOR(0x2, struct rve_hw_versions_t) 21*4882a593Smuzhiyun #define RVE_IOC_IMPORT_BUFFER RVE_IOWR(0x3, struct rve_buffer_pool) 22*4882a593Smuzhiyun #define RVE_IOC_RELEASE_BUFFER RVE_IOW(0x4, struct rve_buffer_pool) 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun #define RVE_IOC_START_CONFIG RVE_IOR(0x5, uint32_t) 25*4882a593Smuzhiyun #define RVE_IOC_END_CONFIG RVE_IOWR(0x6, struct rve_user_ctx_t) 26*4882a593Smuzhiyun #define RVE_IOC_CMD_CONFIG RVE_IOWR(0x7, struct rve_user_ctx_t) 27*4882a593Smuzhiyun #define RVE_IOC_CANCEL_CONFIG RVE_IOWR(0x8, uint32_t) 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun #define RVE_CMD_NUM_MAX 10 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun #define RVE_BUFFER_POOL_SIZE_MAX 40 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun enum rve_memory_type { 34*4882a593Smuzhiyun RVE_DMA_BUFFER = 0, 35*4882a593Smuzhiyun RVE_VIRTUAL_ADDRESS, 36*4882a593Smuzhiyun RVE_PHYSICAL_ADDRESS 37*4882a593Smuzhiyun }; 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun #define RVE_SCHED_PRIORITY_DEFAULT 0 40*4882a593Smuzhiyun #define RVE_SCHED_PRIORITY_MAX 6 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun #define RVE_VERSION_SIZE 16 43*4882a593Smuzhiyun #define RVE_HW_SIZE 5 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun struct rve_version_t { 46*4882a593Smuzhiyun uint32_t major; 47*4882a593Smuzhiyun uint32_t minor; 48*4882a593Smuzhiyun uint32_t revision; 49*4882a593Smuzhiyun uint32_t prod_num; 50*4882a593Smuzhiyun uint8_t str[RVE_VERSION_SIZE]; 51*4882a593Smuzhiyun }; 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun struct rve_hw_versions_t { 54*4882a593Smuzhiyun struct rve_version_t version[RVE_HW_SIZE]; 55*4882a593Smuzhiyun uint32_t size; 56*4882a593Smuzhiyun }; 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun struct rve_user_ctx_t { 59*4882a593Smuzhiyun uint32_t header; 60*4882a593Smuzhiyun uint64_t regcmd_data; 61*4882a593Smuzhiyun int32_t in_fence_fd; 62*4882a593Smuzhiyun int32_t out_fence_fd; 63*4882a593Smuzhiyun int32_t cmd_num; 64*4882a593Smuzhiyun uint32_t id; 65*4882a593Smuzhiyun uint8_t priority; 66*4882a593Smuzhiyun uint32_t sync_mode; 67*4882a593Smuzhiyun uint32_t disable_auto_cancel; 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun uint32_t reserve[31]; 70*4882a593Smuzhiyun }; 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun #endif /*_RVE_DRIVER_H_*/ 73