1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun #ifndef __RGA_MMU_INFO_H__ 3*4882a593Smuzhiyun #define __RGA_MMU_INFO_H__ 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun #include "rga_drv.h" 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun /* RGA_IOMMU register offsets */ 8*4882a593Smuzhiyun #define RGA_IOMMU_BASE 0xf00 9*4882a593Smuzhiyun #define RGA_IOMMU_DTE_ADDR (RGA_IOMMU_BASE + 0x00) /* Directory table address */ 10*4882a593Smuzhiyun #define RGA_IOMMU_STATUS (RGA_IOMMU_BASE + 0x04) 11*4882a593Smuzhiyun #define RGA_IOMMU_COMMAND (RGA_IOMMU_BASE + 0x08) 12*4882a593Smuzhiyun #define RGA_IOMMU_PAGE_FAULT_ADDR (RGA_IOMMU_BASE + 0x0C) /* IOVA of last page fault */ 13*4882a593Smuzhiyun #define RGA_IOMMU_ZAP_ONE_LINE (RGA_IOMMU_BASE + 0x10) /* Shootdown one IOTLB entry */ 14*4882a593Smuzhiyun #define RGA_IOMMU_INT_RAWSTAT (RGA_IOMMU_BASE + 0x14) /* IRQ status ignoring mask */ 15*4882a593Smuzhiyun #define RGA_IOMMU_INT_CLEAR (RGA_IOMMU_BASE + 0x18) /* Acknowledge and re-arm irq */ 16*4882a593Smuzhiyun #define RGA_IOMMU_INT_MASK (RGA_IOMMU_BASE + 0x1C) /* IRQ enable */ 17*4882a593Smuzhiyun #define RGA_IOMMU_INT_STATUS (RGA_IOMMU_BASE + 0x20) /* IRQ status after masking */ 18*4882a593Smuzhiyun #define RGA_IOMMU_AUTO_GATING (RGA_IOMMU_BASE + 0x24) 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun /* RGA_IOMMU_STATUS fields */ 21*4882a593Smuzhiyun #define RGA_IOMMU_STATUS_PAGING_ENABLED BIT(0) 22*4882a593Smuzhiyun #define RGA_IOMMU_STATUS_PAGE_FAULT_ACTIVE BIT(1) 23*4882a593Smuzhiyun #define RGA_IOMMU_STATUS_STALL_ACTIVE BIT(2) 24*4882a593Smuzhiyun #define RGA_IOMMU_STATUS_IDLE BIT(3) 25*4882a593Smuzhiyun #define RGA_IOMMU_STATUS_REPLAY_BUFFER_EMPTY BIT(4) 26*4882a593Smuzhiyun #define RGA_IOMMU_STATUS_PAGE_FAULT_IS_WRITE BIT(5) 27*4882a593Smuzhiyun #define RGA_IOMMU_STATUS_STALL_NOT_ACTIVE BIT(31) 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun /* RGA_IOMMU_COMMAND command values */ 30*4882a593Smuzhiyun #define RGA_IOMMU_CMD_ENABLE_PAGING 0 /* Enable memory translation */ 31*4882a593Smuzhiyun #define RGA_IOMMU_CMD_DISABLE_PAGING 1 /* Disable memory translation */ 32*4882a593Smuzhiyun #define RGA_IOMMU_CMD_ENABLE_STALL 2 /* Stall paging to allow other cmds */ 33*4882a593Smuzhiyun #define RGA_IOMMU_CMD_DISABLE_STALL 3 /* Stop stall re-enables paging */ 34*4882a593Smuzhiyun #define RGA_IOMMU_CMD_ZAP_CACHE 4 /* Shoot down entire IOTLB */ 35*4882a593Smuzhiyun #define RGA_IOMMU_CMD_PAGE_FAULT_DONE 5 /* Clear page fault */ 36*4882a593Smuzhiyun #define RGA_IOMMU_CMD_FORCE_RESET 6 /* Reset all registers */ 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun /* RGA_IOMMU_INT_* register fields */ 39*4882a593Smuzhiyun #define RGA_IOMMU_IRQ_PAGE_FAULT 0x01 /* page fault */ 40*4882a593Smuzhiyun #define RGA_IOMMU_IRQ_BUS_ERROR 0x02 /* bus read error */ 41*4882a593Smuzhiyun #define RGA_IOMMU_IRQ_MASK (RGA_IOMMU_IRQ_PAGE_FAULT | RGA_IOMMU_IRQ_BUS_ERROR) 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun /* 44*4882a593Smuzhiyun * The maximum input is 8192*8192, the maximum output is 4096*4096 45*4882a593Smuzhiyun * The size of physical pages requested is: 46*4882a593Smuzhiyun * (( maximum_input_value * 47*4882a593Smuzhiyun * maximum_input_value * format_bpp ) / 4K_page_size) + 1 48*4882a593Smuzhiyun */ 49*4882a593Smuzhiyun #define RGA2_PHY_PAGE_SIZE (((8192 * 8192 * 4) / 4096) + 1) 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun struct rga_mmu_base { 52*4882a593Smuzhiyun unsigned int *buf_virtual; 53*4882a593Smuzhiyun struct page **pages; 54*4882a593Smuzhiyun u8 buf_order; 55*4882a593Smuzhiyun u8 pages_order; 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun int32_t front; 58*4882a593Smuzhiyun int32_t back; 59*4882a593Smuzhiyun int32_t size; 60*4882a593Smuzhiyun int32_t curr; 61*4882a593Smuzhiyun }; 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun int rga_user_memory_check(struct page **pages, u32 w, u32 h, u32 format, int flag); 64*4882a593Smuzhiyun int rga_set_mmu_base(struct rga_job *job, struct rga2_req *req); 65*4882a593Smuzhiyun unsigned int *rga_mmu_buf_get(struct rga_mmu_base *mmu_base, uint32_t size); 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun struct rga_mmu_base *rga_mmu_base_init(size_t size); 68*4882a593Smuzhiyun void rga_mmu_base_free(struct rga_mmu_base **mmu_base); 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun int rga_iommu_detach(struct rga_iommu_info *info); 71*4882a593Smuzhiyun int rga_iommu_attach(struct rga_iommu_info *info); 72*4882a593Smuzhiyun struct rga_iommu_info *rga_iommu_probe(struct device *dev); 73*4882a593Smuzhiyun int rga_iommu_remove(struct rga_iommu_info *info); 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun int rga_iommu_bind(void); 76*4882a593Smuzhiyun void rga_iommu_unbind(void); 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun #endif 79*4882a593Smuzhiyun 80