xref: /OK3568_Linux_fs/kernel/drivers/video/rockchip/mpp/mpp_rkvdec2_link.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * Copyright (c) 2021 Rockchip Electronics Co., Ltd
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * author:
6*4882a593Smuzhiyun  *	Herman Chen <herman.chen@rock-chips.com>
7*4882a593Smuzhiyun  */
8*4882a593Smuzhiyun #ifndef __ROCKCHIP_MPP_RKVDEC2_LINK_H__
9*4882a593Smuzhiyun #define __ROCKCHIP_MPP_RKVDEC2_LINK_H__
10*4882a593Smuzhiyun 
11*4882a593Smuzhiyun #include "mpp_rkvdec2.h"
12*4882a593Smuzhiyun 
13*4882a593Smuzhiyun #define RKVDEC_REG_IMPORTANT_BASE	0x2c
14*4882a593Smuzhiyun #define RKVDEC_REG_IMPORTANT_INDEX	11
15*4882a593Smuzhiyun #define RKVDEC_SOFTREST_EN		BIT(20)
16*4882a593Smuzhiyun 
17*4882a593Smuzhiyun #define RKVDEC_REG_SECOND_EN_BASE	0x30
18*4882a593Smuzhiyun #define RKVDEC_REG_SECOND_EN_INDEX	12
19*4882a593Smuzhiyun #define RKVDEC_WAIT_RESET_EN		BIT(7)
20*4882a593Smuzhiyun 
21*4882a593Smuzhiyun #define RKVDEC_REG_EN_MODE_SET		13
22*4882a593Smuzhiyun 
23*4882a593Smuzhiyun #define RKVDEC_REG_DEBUG_INT_BASE	0x440
24*4882a593Smuzhiyun #define RKVDEC_REG_DEBUG_INT_INDEX	272
25*4882a593Smuzhiyun #define RKVDEC_BIT_BUS_IDLE		BIT(0)
26*4882a593Smuzhiyun 
27*4882a593Smuzhiyun #define RKVDEC_REG_TIMEOUT_THRESHOLD	32
28*4882a593Smuzhiyun 
29*4882a593Smuzhiyun /* define for link hardware */
30*4882a593Smuzhiyun #define RKVDEC_LINK_ADD_CFG_NUM		1
31*4882a593Smuzhiyun 
32*4882a593Smuzhiyun #define RKVDEC_LINK_IRQ_BASE		0x000
33*4882a593Smuzhiyun #define RKVDEC_LINK_BIT_IRQ_DIS		BIT(2)
34*4882a593Smuzhiyun #define RKVDEC_LINK_BIT_IRQ		BIT(8)
35*4882a593Smuzhiyun #define RKVDEC_LINK_BIT_IRQ_RAW		BIT(9)
36*4882a593Smuzhiyun #define RKVDEC_LINK_BIT_CORE_WORK_MODE	BIT(16)
37*4882a593Smuzhiyun #define RKVDEC_LINK_BIT_CCU_WORK_MODE	BIT(17)
38*4882a593Smuzhiyun 
39*4882a593Smuzhiyun #define RKVDEC_LINK_CFG_ADDR_BASE	0x004
40*4882a593Smuzhiyun 
41*4882a593Smuzhiyun #define RKVDEC_LINK_MODE_BASE		0x008
42*4882a593Smuzhiyun #define RKVDEC_LINK_BIT_ADD_MODE	BIT(31)
43*4882a593Smuzhiyun 
44*4882a593Smuzhiyun #define RKVDEC_LINK_CFG_CTRL_BASE	0x00c
45*4882a593Smuzhiyun #define RKVDEC_LINK_BIT_CFG_DONE	BIT(0)
46*4882a593Smuzhiyun 
47*4882a593Smuzhiyun #define RKVDEC_LINK_DEC_NUM_BASE	0x010
48*4882a593Smuzhiyun 
49*4882a593Smuzhiyun #define RKVDEC_LINK_TOTAL_NUM_BASE	0x014
50*4882a593Smuzhiyun 
51*4882a593Smuzhiyun #define RKVDEC_LINK_EN_BASE		0x018
52*4882a593Smuzhiyun #define RKVDEC_LINK_BIT_EN		BIT(0)
53*4882a593Smuzhiyun 
54*4882a593Smuzhiyun #define RKVDEC_LINK_NEXT_ADDR_BASE	0x01c
55*4882a593Smuzhiyun 
56*4882a593Smuzhiyun #define RKVDEC_LINK_STA_BASE		0x024
57*4882a593Smuzhiyun 
58*4882a593Smuzhiyun #define RKVDEC_LINK_REG_CYCLE_CNT	179
59*4882a593Smuzhiyun 
60*4882a593Smuzhiyun /* define for ccu link hardware */
61*4882a593Smuzhiyun #define RKVDEC_CCU_CTRL_BASE		0x000
62*4882a593Smuzhiyun #define RKVDEC_CCU_BIT_AUTOGATE		BIT(0)
63*4882a593Smuzhiyun #define RKVDEC_CCU_BIT_FIX_RCB		BIT(20)
64*4882a593Smuzhiyun 
65*4882a593Smuzhiyun #define RKVDEC_CCU_CFG_ADDR_BASE	0x004
66*4882a593Smuzhiyun #define RKVDEC_CCU_LINK_MODE_BASE	0x008
67*4882a593Smuzhiyun #define RKVDEC_CCU_BIT_ADD_MODE		BIT(31)
68*4882a593Smuzhiyun 
69*4882a593Smuzhiyun #define RKVDEC_CCU_CFG_DONE_BASE	0x00c
70*4882a593Smuzhiyun #define RKVDEC_CCU_BIT_CFG_DONE		BIT(0)
71*4882a593Smuzhiyun 
72*4882a593Smuzhiyun #define RKVDEC_CCU_DEC_NUM_BASE		0x010
73*4882a593Smuzhiyun #define RKVDEC_CCU_TOTAL_NUM_BASE	0x014
74*4882a593Smuzhiyun 
75*4882a593Smuzhiyun #define RKVDEC_CCU_WORK_BASE		0x018
76*4882a593Smuzhiyun #define RKVDEC_CCU_BIT_WORK_EN		BIT(0)
77*4882a593Smuzhiyun 
78*4882a593Smuzhiyun #define RKVDEC_CCU_SEND_NUM_BASE	0x024
79*4882a593Smuzhiyun #define RKVDEC_CCU_WORK_MODE_BASE	0x040
80*4882a593Smuzhiyun #define RKVDEC_CCU_BIT_WORK_MODE	BIT(0)
81*4882a593Smuzhiyun 
82*4882a593Smuzhiyun #define RKVDEC_CCU_CORE_WORK_BASE	0x044
83*4882a593Smuzhiyun #define RKVDEC_CCU_CORE_STA_BASE	0x048
84*4882a593Smuzhiyun #define RKVDEC_CCU_CORE_IDLE_BASE	0x04c
85*4882a593Smuzhiyun #define RKVDEC_CCU_CORE_ERR_BASE	0x054
86*4882a593Smuzhiyun 
87*4882a593Smuzhiyun #define RKVDEC_CCU_CORE_RW_MASK		0x30000
88*4882a593Smuzhiyun 
89*4882a593Smuzhiyun #define RKVDEC_MAX_WRITE_PART	6
90*4882a593Smuzhiyun #define RKVDEC_MAX_READ_PART	2
91*4882a593Smuzhiyun 
92*4882a593Smuzhiyun struct rkvdec_link_part {
93*4882a593Smuzhiyun 	/* register offset of table buffer */
94*4882a593Smuzhiyun 	u32 tb_reg_off;
95*4882a593Smuzhiyun 	/* start idx of task register */
96*4882a593Smuzhiyun 	u32 reg_start;
97*4882a593Smuzhiyun 	/* number of task register */
98*4882a593Smuzhiyun 	u32 reg_num;
99*4882a593Smuzhiyun };
100*4882a593Smuzhiyun 
101*4882a593Smuzhiyun struct rkvdec_link_status {
102*4882a593Smuzhiyun 	u32 dec_num_mask;
103*4882a593Smuzhiyun 	u32 err_flag_base;
104*4882a593Smuzhiyun 	u32 err_flag_bit;
105*4882a593Smuzhiyun };
106*4882a593Smuzhiyun 
107*4882a593Smuzhiyun struct rkvdec_link_info {
108*4882a593Smuzhiyun 	dma_addr_t iova;
109*4882a593Smuzhiyun 	/* total register for link table buffer */
110*4882a593Smuzhiyun 	u32 tb_reg_num;
111*4882a593Smuzhiyun 	/* next link table addr in table buffer */
112*4882a593Smuzhiyun 	u32 tb_reg_next;
113*4882a593Smuzhiyun 	/* current read back addr in table buffer */
114*4882a593Smuzhiyun 	u32 tb_reg_r;
115*4882a593Smuzhiyun 	/* secondary enable in table buffer */
116*4882a593Smuzhiyun 	u32 tb_reg_second_en;
117*4882a593Smuzhiyun 	u32 part_w_num;
118*4882a593Smuzhiyun 	u32 part_r_num;
119*4882a593Smuzhiyun 
120*4882a593Smuzhiyun 	struct rkvdec_link_part part_w[RKVDEC_MAX_WRITE_PART];
121*4882a593Smuzhiyun 	struct rkvdec_link_part part_r[RKVDEC_MAX_READ_PART];
122*4882a593Smuzhiyun 
123*4882a593Smuzhiyun 	/* interrupt read back in table buffer */
124*4882a593Smuzhiyun 	u32 tb_reg_int;
125*4882a593Smuzhiyun 	u32 tb_reg_cycle;
126*4882a593Smuzhiyun 	bool hack_setup;
127*4882a593Smuzhiyun 	struct rkvdec_link_status reg_status;
128*4882a593Smuzhiyun };
129*4882a593Smuzhiyun 
130*4882a593Smuzhiyun struct rkvdec_link_dev {
131*4882a593Smuzhiyun 	struct device *dev;
132*4882a593Smuzhiyun 	struct mpp_dev *mpp;
133*4882a593Smuzhiyun 	void __iomem *reg_base;
134*4882a593Smuzhiyun 	u32 enabled;
135*4882a593Smuzhiyun 	u32 link_mode;
136*4882a593Smuzhiyun 	u32 decoded_status;
137*4882a593Smuzhiyun 	u32 irq_status;
138*4882a593Smuzhiyun 	u32 iova_curr;
139*4882a593Smuzhiyun 	u32 iova_next;
140*4882a593Smuzhiyun 	u32 decoded;
141*4882a593Smuzhiyun 	u32 total;
142*4882a593Smuzhiyun 	u32 error;
143*4882a593Smuzhiyun 	u32 hack_task_running;
144*4882a593Smuzhiyun 
145*4882a593Smuzhiyun 	struct rkvdec_link_info *info;
146*4882a593Smuzhiyun 	struct mpp_dma_buffer *table;
147*4882a593Smuzhiyun 	u32 link_node_size;
148*4882a593Smuzhiyun 	u32 link_reg_count;
149*4882a593Smuzhiyun 
150*4882a593Smuzhiyun 	/* taskqueue variables */
151*4882a593Smuzhiyun 	u32 task_running;
152*4882a593Smuzhiyun 	atomic_t task_pending;
153*4882a593Smuzhiyun 	/* timeout can be trigger in different thread so atomic is needed */
154*4882a593Smuzhiyun 	atomic_t task_timeout;
155*4882a593Smuzhiyun 	u32 task_timeout_prev;
156*4882a593Smuzhiyun 
157*4882a593Smuzhiyun 	/* link mode hardware status */
158*4882a593Smuzhiyun 	atomic_t power_enabled;
159*4882a593Smuzhiyun 	u32 irq_enabled;
160*4882a593Smuzhiyun 
161*4882a593Smuzhiyun 	/* debug variable */
162*4882a593Smuzhiyun 	u32 statistic_count;
163*4882a593Smuzhiyun 	u64 task_cycle_sum;
164*4882a593Smuzhiyun 	u32 task_cnt;
165*4882a593Smuzhiyun 	u64 stuff_cycle_sum;
166*4882a593Smuzhiyun 	u32 stuff_cnt;
167*4882a593Smuzhiyun 
168*4882a593Smuzhiyun 	/* link info */
169*4882a593Smuzhiyun 	u32 task_capacity;
170*4882a593Smuzhiyun 	struct mpp_dma_buffer *table_array;
171*4882a593Smuzhiyun 	struct list_head unused_list;
172*4882a593Smuzhiyun 	struct list_head used_list;
173*4882a593Smuzhiyun };
174*4882a593Smuzhiyun 
175*4882a593Smuzhiyun enum RKVDEC2_CCU_MODE {
176*4882a593Smuzhiyun 	RKVDEC2_CCU_MODE_NULL		= 0,
177*4882a593Smuzhiyun 	RKVDEC2_CCU_TASK_SOFT		= 1,
178*4882a593Smuzhiyun 	RKVDEC2_CCU_TASK_HARD		= 2,
179*4882a593Smuzhiyun 	RKVDEC2_CCU_MODE_BUTT,
180*4882a593Smuzhiyun };
181*4882a593Smuzhiyun 
182*4882a593Smuzhiyun struct rkvdec2_ccu {
183*4882a593Smuzhiyun 	struct device *dev;
184*4882a593Smuzhiyun 	/* register base */
185*4882a593Smuzhiyun 	void __iomem *reg_base;
186*4882a593Smuzhiyun 
187*4882a593Smuzhiyun 	atomic_t power_enabled;
188*4882a593Smuzhiyun 	struct mpp_clk_info aclk_info;
189*4882a593Smuzhiyun #ifdef CONFIG_ROCKCHIP_MPP_PROC_FS
190*4882a593Smuzhiyun 	struct proc_dir_entry *procfs;
191*4882a593Smuzhiyun #endif
192*4882a593Smuzhiyun 	struct reset_control *rst_a;
193*4882a593Smuzhiyun 	enum RKVDEC2_CCU_MODE ccu_mode;
194*4882a593Smuzhiyun 	u32 ccu_core_work_mode;
195*4882a593Smuzhiyun 
196*4882a593Smuzhiyun 	struct mpp_dma_buffer *table_array;
197*4882a593Smuzhiyun 	struct list_head unused_list;
198*4882a593Smuzhiyun 	struct list_head used_list;
199*4882a593Smuzhiyun 	u32 timeout_flag;
200*4882a593Smuzhiyun };
201*4882a593Smuzhiyun 
202*4882a593Smuzhiyun extern struct rkvdec_link_info rkvdec_link_rk356x_hw_info;
203*4882a593Smuzhiyun extern struct rkvdec_link_info rkvdec_link_v2_hw_info;
204*4882a593Smuzhiyun extern struct rkvdec_link_info rkvdec_link_vdpu382_hw_info;
205*4882a593Smuzhiyun 
206*4882a593Smuzhiyun int rkvdec_link_dump(struct mpp_dev *mpp);
207*4882a593Smuzhiyun 
208*4882a593Smuzhiyun int rkvdec2_link_init(struct platform_device *pdev, struct rkvdec2_dev *dec);
209*4882a593Smuzhiyun int rkvdec2_link_procfs_init(struct mpp_dev *mpp);
210*4882a593Smuzhiyun int rkvdec2_link_remove(struct mpp_dev *mpp, struct rkvdec_link_dev *link_dec);
211*4882a593Smuzhiyun 
212*4882a593Smuzhiyun irqreturn_t rkvdec2_link_irq_proc(int irq, void *param);
213*4882a593Smuzhiyun int rkvdec2_link_process_task(struct mpp_session *session,
214*4882a593Smuzhiyun 			      struct mpp_task_msgs *msgs);
215*4882a593Smuzhiyun int rkvdec2_link_wait_result(struct mpp_session *session,
216*4882a593Smuzhiyun 			     struct mpp_task_msgs *msgs);
217*4882a593Smuzhiyun void rkvdec2_link_worker(struct kthread_work *work_s);
218*4882a593Smuzhiyun void rkvdec2_link_session_deinit(struct mpp_session *session);
219*4882a593Smuzhiyun 
220*4882a593Smuzhiyun /* for ccu link */
221*4882a593Smuzhiyun int rkvdec2_attach_ccu(struct device *dev, struct rkvdec2_dev *dec);
222*4882a593Smuzhiyun int rkvdec2_ccu_link_init(struct platform_device *pdev, struct rkvdec2_dev *dec);
223*4882a593Smuzhiyun void *rkvdec2_ccu_alloc_task(struct mpp_session *session, struct mpp_task_msgs *msgs);
224*4882a593Smuzhiyun int rkvdec2_ccu_iommu_fault_handle(struct iommu_domain *iommu,
225*4882a593Smuzhiyun 				   struct device *iommu_dev,
226*4882a593Smuzhiyun 				   unsigned long iova, int status, void *arg);
227*4882a593Smuzhiyun irqreturn_t rkvdec2_soft_ccu_irq(int irq, void *param);
228*4882a593Smuzhiyun void rkvdec2_soft_ccu_worker(struct kthread_work *work_s);
229*4882a593Smuzhiyun 
230*4882a593Smuzhiyun int rkvdec2_ccu_alloc_table(struct rkvdec2_dev *dec,
231*4882a593Smuzhiyun 			    struct rkvdec_link_dev *link_dec);
232*4882a593Smuzhiyun irqreturn_t rkvdec2_hard_ccu_irq(int irq, void *param);
233*4882a593Smuzhiyun void rkvdec2_hard_ccu_worker(struct kthread_work *work_s);
234*4882a593Smuzhiyun 
235*4882a593Smuzhiyun #endif
236