1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) 2022 Rockchip Electronics Co., Ltd 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun #ifndef __ROCKCHIP_DVBM_H__ 6*4882a593Smuzhiyun #define __ROCKCHIP_DVBM_H__ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #include <linux/clk.h> 9*4882a593Smuzhiyun #include <linux/reset.h> 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun struct rk_dvbm_base { 12*4882a593Smuzhiyun /* 0x2c */ 13*4882a593Smuzhiyun u32 ybuf_bot; 14*4882a593Smuzhiyun /* 0x30 */ 15*4882a593Smuzhiyun u32 ybuf_top; 16*4882a593Smuzhiyun /* 0x34 */ 17*4882a593Smuzhiyun u32 ybuf_sadr; 18*4882a593Smuzhiyun /* 0x38 */ 19*4882a593Smuzhiyun u32 ybuf_lstd; 20*4882a593Smuzhiyun /* 0x3c */ 21*4882a593Smuzhiyun u32 ybuf_fstd; 22*4882a593Smuzhiyun /* 0x40 */ 23*4882a593Smuzhiyun u32 cbuf_bot; 24*4882a593Smuzhiyun /* 0x44 */ 25*4882a593Smuzhiyun u32 cbuf_top; 26*4882a593Smuzhiyun /* 0x48 */ 27*4882a593Smuzhiyun u32 cbuf_sadr; 28*4882a593Smuzhiyun /* 0x4c */ 29*4882a593Smuzhiyun u32 cbuf_lstd; 30*4882a593Smuzhiyun /* 0x50 */ 31*4882a593Smuzhiyun u32 cbuf_fstd; 32*4882a593Smuzhiyun /* 0x54 */ 33*4882a593Smuzhiyun u32 aful_thdy; 34*4882a593Smuzhiyun /* 0x58 */ 35*4882a593Smuzhiyun u32 aful_thdc; 36*4882a593Smuzhiyun /* 0x5c */ 37*4882a593Smuzhiyun u32 oful_thdy; 38*4882a593Smuzhiyun /* 0x60 */ 39*4882a593Smuzhiyun u32 oful_thdc; 40*4882a593Smuzhiyun }; 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun struct rk_dvbm_regs { 43*4882a593Smuzhiyun /* 0x0 */ 44*4882a593Smuzhiyun u32 version; 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun /* 0x4 */ 47*4882a593Smuzhiyun struct { 48*4882a593Smuzhiyun u32 isp_cnct : 1; 49*4882a593Smuzhiyun u32 reserved : 31; 50*4882a593Smuzhiyun } isp_cnct; 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun /* 0x8 */ 53*4882a593Smuzhiyun struct { 54*4882a593Smuzhiyun u32 vepu_cnct : 1; 55*4882a593Smuzhiyun u32 reserved : 31; 56*4882a593Smuzhiyun } vepu_cnct; 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun /* 0xc */ 59*4882a593Smuzhiyun struct { 60*4882a593Smuzhiyun u32 auto_resyn : 1; 61*4882a593Smuzhiyun u32 ignore_vepu_cnct_ack : 1; 62*4882a593Smuzhiyun /* 63*4882a593Smuzhiyun * 1’b0 : the current ISP frame 64*4882a593Smuzhiyun * 1’b1 : the next ISP frame 65*4882a593Smuzhiyun */ 66*4882a593Smuzhiyun u32 start_point_after_vepu_cnct : 1; 67*4882a593Smuzhiyun u32 reserved0 : 5; 68*4882a593Smuzhiyun /* only support yuv420sp 4'h0 */ 69*4882a593Smuzhiyun u32 fmt : 4; 70*4882a593Smuzhiyun u32 reserved1 : 20; 71*4882a593Smuzhiyun } dvbm_cfg; 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun /* 0x10 */ 74*4882a593Smuzhiyun struct { 75*4882a593Smuzhiyun u32 wdg_isp_cnct_timeout : 22; 76*4882a593Smuzhiyun u32 reserved : 10; 77*4882a593Smuzhiyun } wdg_cfg0; 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun /* 0x14 */ 80*4882a593Smuzhiyun struct { 81*4882a593Smuzhiyun u32 wdg_vepu_cnct_timeout : 22; 82*4882a593Smuzhiyun u32 reserved : 10; 83*4882a593Smuzhiyun } wdg_cfg1; 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun /* 0x18 */ 86*4882a593Smuzhiyun struct { 87*4882a593Smuzhiyun u32 wdg_vepu_handshake_timeout : 22; 88*4882a593Smuzhiyun u32 reserved : 10; 89*4882a593Smuzhiyun } wdg_cfg2; 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun /* 0x1c */ 92*4882a593Smuzhiyun struct { 93*4882a593Smuzhiyun u32 buf_ovfl : 1; 94*4882a593Smuzhiyun u32 resync_finish : 1; 95*4882a593Smuzhiyun u32 isp_cnct_timeout : 1; 96*4882a593Smuzhiyun u32 vepu_cnct_timeout : 1; 97*4882a593Smuzhiyun 98*4882a593Smuzhiyun u32 vepu_handshake_timeout : 1; 99*4882a593Smuzhiyun u32 isp_cnct : 1; 100*4882a593Smuzhiyun u32 isp_discnct : 1; 101*4882a593Smuzhiyun u32 vepu_cnct : 1; 102*4882a593Smuzhiyun 103*4882a593Smuzhiyun u32 vepu_discnct : 1; 104*4882a593Smuzhiyun u32 reserved : 23; 105*4882a593Smuzhiyun } int_en; 106*4882a593Smuzhiyun 107*4882a593Smuzhiyun /* 0x20 */ 108*4882a593Smuzhiyun struct { 109*4882a593Smuzhiyun u32 buf_ovfl : 1; 110*4882a593Smuzhiyun u32 resync_finish : 1; 111*4882a593Smuzhiyun u32 isp_cnct_timeout : 1; 112*4882a593Smuzhiyun u32 vepu_cnct_timeout : 1; 113*4882a593Smuzhiyun 114*4882a593Smuzhiyun u32 vepu_handshake_timeout : 1; 115*4882a593Smuzhiyun u32 isp_cnct : 1; 116*4882a593Smuzhiyun u32 isp_discnct : 1; 117*4882a593Smuzhiyun u32 vepu_cnct : 1; 118*4882a593Smuzhiyun 119*4882a593Smuzhiyun u32 vepu_discnct : 1; 120*4882a593Smuzhiyun u32 reserved : 23; 121*4882a593Smuzhiyun } int_msk; 122*4882a593Smuzhiyun 123*4882a593Smuzhiyun /* 0x24 */ 124*4882a593Smuzhiyun struct { 125*4882a593Smuzhiyun u32 buf_ovfl : 1; 126*4882a593Smuzhiyun u32 resync_finish : 1; 127*4882a593Smuzhiyun u32 isp_cnct_timeout : 1; 128*4882a593Smuzhiyun u32 vepu_cnct_timeout : 1; 129*4882a593Smuzhiyun 130*4882a593Smuzhiyun u32 vepu_handshake_timeout : 1; 131*4882a593Smuzhiyun u32 isp_cnct : 1; 132*4882a593Smuzhiyun u32 isp_discnct : 1; 133*4882a593Smuzhiyun u32 vepu_cnct : 1; 134*4882a593Smuzhiyun 135*4882a593Smuzhiyun u32 vepu_discnct : 1; 136*4882a593Smuzhiyun u32 reserved : 23; 137*4882a593Smuzhiyun } int_clr; 138*4882a593Smuzhiyun 139*4882a593Smuzhiyun /* 0x28 */ 140*4882a593Smuzhiyun struct { 141*4882a593Smuzhiyun u32 buf_ovfl : 1; 142*4882a593Smuzhiyun u32 resync_finish : 1; 143*4882a593Smuzhiyun u32 isp_cnct_timeout : 1; 144*4882a593Smuzhiyun u32 vepu_cnct_timeout : 1; 145*4882a593Smuzhiyun 146*4882a593Smuzhiyun u32 vepu_handshake_timeout : 1; 147*4882a593Smuzhiyun u32 isp_cnct : 1; 148*4882a593Smuzhiyun u32 isp_discnct : 1; 149*4882a593Smuzhiyun u32 vepu_cnct : 1; 150*4882a593Smuzhiyun 151*4882a593Smuzhiyun u32 vepu_discnct : 1; 152*4882a593Smuzhiyun u32 reserved : 23; 153*4882a593Smuzhiyun } int_st; 154*4882a593Smuzhiyun struct rk_dvbm_base addr_base; 155*4882a593Smuzhiyun /* 0x64 - 0x7c */ 156*4882a593Smuzhiyun u32 reserved[7]; 157*4882a593Smuzhiyun 158*4882a593Smuzhiyun /* 0x80 */ 159*4882a593Smuzhiyun struct { 160*4882a593Smuzhiyun u32 isp_connection : 1; 161*4882a593Smuzhiyun u32 vepu_connection : 1; 162*4882a593Smuzhiyun u32 resynchronization : 1; 163*4882a593Smuzhiyun u32 y_buf_ovfl : 1; 164*4882a593Smuzhiyun 165*4882a593Smuzhiyun u32 c_buf_ovfl : 1; 166*4882a593Smuzhiyun u32 reserved : 27; 167*4882a593Smuzhiyun } dvbm_st; 168*4882a593Smuzhiyun 169*4882a593Smuzhiyun /* 0x84 */ 170*4882a593Smuzhiyun u32 ovfl_st; 171*4882a593Smuzhiyun }; 172*4882a593Smuzhiyun 173*4882a593Smuzhiyun struct dvbm_ctx { 174*4882a593Smuzhiyun struct clk *clk; 175*4882a593Smuzhiyun struct device *dev; 176*4882a593Smuzhiyun void __iomem *reg_base; 177*4882a593Smuzhiyun struct rk_dvbm_regs regs; 178*4882a593Smuzhiyun struct reset_control *rst; 179*4882a593Smuzhiyun 180*4882a593Smuzhiyun u32 isp_connet; 181*4882a593Smuzhiyun u32 vepu_connet; 182*4882a593Smuzhiyun u32 buf_overflow; 183*4882a593Smuzhiyun u32 irq_status; 184*4882a593Smuzhiyun u32 dvbm_status; 185*4882a593Smuzhiyun int irq; 186*4882a593Smuzhiyun 187*4882a593Smuzhiyun /* vepu infos */ 188*4882a593Smuzhiyun struct dvbm_port port_vepu; 189*4882a593Smuzhiyun atomic_t vepu_ref; 190*4882a593Smuzhiyun atomic_t vepu_link; 191*4882a593Smuzhiyun struct dvbm_cb vepu_cb; 192*4882a593Smuzhiyun struct dvbm_addr_cfg vepu_cfg; 193*4882a593Smuzhiyun 194*4882a593Smuzhiyun /* isp infos */ 195*4882a593Smuzhiyun struct dvbm_port port_isp; 196*4882a593Smuzhiyun struct dvbm_cb isp_cb; 197*4882a593Smuzhiyun struct dvbm_isp_cfg_t isp_cfg; 198*4882a593Smuzhiyun struct dvbm_isp_frm_info isp_frm_info; 199*4882a593Smuzhiyun atomic_t isp_link; 200*4882a593Smuzhiyun atomic_t isp_ref; 201*4882a593Smuzhiyun u32 isp_max_lcnt; 202*4882a593Smuzhiyun u32 isp_frm_start; 203*4882a593Smuzhiyun u32 isp_frm_end; 204*4882a593Smuzhiyun ktime_t isp_frm_time; 205*4882a593Smuzhiyun u32 wrap_line; 206*4882a593Smuzhiyun 207*4882a593Smuzhiyun /* debug infos */ 208*4882a593Smuzhiyun u32 dump_s; 209*4882a593Smuzhiyun u32 dump_e; 210*4882a593Smuzhiyun u32 ignore_ovfl; 211*4882a593Smuzhiyun u32 loopcnt; 212*4882a593Smuzhiyun }; 213*4882a593Smuzhiyun 214*4882a593Smuzhiyun #endif 215