1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * GOVR registers list for WM8505 chips 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2010 Ed Spiridonov <edo.rus@gmail.com> 6*4882a593Smuzhiyun * Based on VIA/WonderMedia wm8510-govrh-reg.h 7*4882a593Smuzhiyun * http://github.com/projectgus/kernel_wm8505/blob/wm8505_2.6.29/ 8*4882a593Smuzhiyun * drivers/video/wmt/register/wm8510/wm8510-govrh-reg.h 9*4882a593Smuzhiyun */ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #ifndef _WM8505FB_REGS_H 12*4882a593Smuzhiyun #define _WM8505FB_REGS_H 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun /* 15*4882a593Smuzhiyun * Color space select register, default value 0x1c 16*4882a593Smuzhiyun * BIT0 GOVRH_DVO_YUV2RGB_ENABLE 17*4882a593Smuzhiyun * BIT1 GOVRH_VGA_YUV2RGB_ENABLE 18*4882a593Smuzhiyun * BIT2 GOVRH_RGB_MODE 19*4882a593Smuzhiyun * BIT3 GOVRH_DAC_CLKINV 20*4882a593Smuzhiyun * BIT4 GOVRH_BLANK_ZERO 21*4882a593Smuzhiyun */ 22*4882a593Smuzhiyun #define WMT_GOVR_COLORSPACE 0x1e4 23*4882a593Smuzhiyun /* 24*4882a593Smuzhiyun * Another colorspace select register, default value 1 25*4882a593Smuzhiyun * BIT0 GOVRH_DVO_RGB 26*4882a593Smuzhiyun * BIT1 GOVRH_DVO_YUV422 27*4882a593Smuzhiyun */ 28*4882a593Smuzhiyun #define WMT_GOVR_COLORSPACE1 0x30 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun #define WMT_GOVR_CONTRAST 0x1b8 31*4882a593Smuzhiyun #define WMT_GOVR_BRGHTNESS 0x1bc /* incompatible with RGB? */ 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun /* Framubeffer address */ 34*4882a593Smuzhiyun #define WMT_GOVR_FBADDR 0x90 35*4882a593Smuzhiyun #define WMT_GOVR_FBADDR1 0x94 /* UV offset in YUV mode */ 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun /* Offset of visible window */ 38*4882a593Smuzhiyun #define WMT_GOVR_XPAN 0xa4 39*4882a593Smuzhiyun #define WMT_GOVR_YPAN 0xa0 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun #define WMT_GOVR_XRES 0x98 42*4882a593Smuzhiyun #define WMT_GOVR_XRES_VIRTUAL 0x9c 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun #define WMT_GOVR_MIF_ENABLE 0x80 45*4882a593Smuzhiyun #define WMT_GOVR_FHI 0xa8 46*4882a593Smuzhiyun #define WMT_GOVR_REG_UPDATE 0xe4 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun /* 49*4882a593Smuzhiyun * BIT0 GOVRH_DVO_OUTWIDTH 50*4882a593Smuzhiyun * BIT1 GOVRH_DVO_SYNC_POLAR 51*4882a593Smuzhiyun * BIT2 GOVRH_DVO_ENABLE 52*4882a593Smuzhiyun */ 53*4882a593Smuzhiyun #define WMT_GOVR_DVO_SET 0x148 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun /* Timing generator? */ 56*4882a593Smuzhiyun #define WMT_GOVR_TG 0x100 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun /* Timings */ 59*4882a593Smuzhiyun #define WMT_GOVR_TIMING_H_ALL 0x108 60*4882a593Smuzhiyun #define WMT_GOVR_TIMING_V_ALL 0x10c 61*4882a593Smuzhiyun #define WMT_GOVR_TIMING_V_START 0x110 62*4882a593Smuzhiyun #define WMT_GOVR_TIMING_V_END 0x114 63*4882a593Smuzhiyun #define WMT_GOVR_TIMING_H_START 0x118 64*4882a593Smuzhiyun #define WMT_GOVR_TIMING_H_END 0x11c 65*4882a593Smuzhiyun #define WMT_GOVR_TIMING_V_SYNC 0x128 66*4882a593Smuzhiyun #define WMT_GOVR_TIMING_H_SYNC 0x12c 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun #endif /* _WM8505FB_REGS_H */ 69