1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
4*4882a593Smuzhiyun * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
5*4882a593Smuzhiyun * Copyright 2011 Florian Tobias Schandinat <FlorianSchandinat@gmx.de>
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun /*
8*4882a593Smuzhiyun * clock and PLL management functions
9*4882a593Smuzhiyun */
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun #ifndef __VIA_CLOCK_H__
12*4882a593Smuzhiyun #define __VIA_CLOCK_H__
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun #include <linux/types.h>
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun enum via_clksrc {
17*4882a593Smuzhiyun VIA_CLKSRC_X1 = 0,
18*4882a593Smuzhiyun VIA_CLKSRC_TVX1,
19*4882a593Smuzhiyun VIA_CLKSRC_TVPLL,
20*4882a593Smuzhiyun VIA_CLKSRC_DVP1TVCLKR,
21*4882a593Smuzhiyun VIA_CLKSRC_CAP0,
22*4882a593Smuzhiyun VIA_CLKSRC_CAP1,
23*4882a593Smuzhiyun };
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun struct via_pll_config {
26*4882a593Smuzhiyun u16 multiplier;
27*4882a593Smuzhiyun u8 divisor;
28*4882a593Smuzhiyun u8 rshift;
29*4882a593Smuzhiyun };
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun struct via_clock {
32*4882a593Smuzhiyun void (*set_primary_clock_state)(u8 state);
33*4882a593Smuzhiyun void (*set_primary_clock_source)(enum via_clksrc src, bool use_pll);
34*4882a593Smuzhiyun void (*set_primary_pll_state)(u8 state);
35*4882a593Smuzhiyun void (*set_primary_pll)(struct via_pll_config config);
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun void (*set_secondary_clock_state)(u8 state);
38*4882a593Smuzhiyun void (*set_secondary_clock_source)(enum via_clksrc src, bool use_pll);
39*4882a593Smuzhiyun void (*set_secondary_pll_state)(u8 state);
40*4882a593Smuzhiyun void (*set_secondary_pll)(struct via_pll_config config);
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun void (*set_engine_pll_state)(u8 state);
43*4882a593Smuzhiyun void (*set_engine_pll)(struct via_pll_config config);
44*4882a593Smuzhiyun };
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun
get_pll_internal_frequency(u32 ref_freq,struct via_pll_config pll)47*4882a593Smuzhiyun static inline u32 get_pll_internal_frequency(u32 ref_freq,
48*4882a593Smuzhiyun struct via_pll_config pll)
49*4882a593Smuzhiyun {
50*4882a593Smuzhiyun return ref_freq / pll.divisor * pll.multiplier;
51*4882a593Smuzhiyun }
52*4882a593Smuzhiyun
get_pll_output_frequency(u32 ref_freq,struct via_pll_config pll)53*4882a593Smuzhiyun static inline u32 get_pll_output_frequency(u32 ref_freq,
54*4882a593Smuzhiyun struct via_pll_config pll)
55*4882a593Smuzhiyun {
56*4882a593Smuzhiyun return get_pll_internal_frequency(ref_freq, pll) >> pll.rshift;
57*4882a593Smuzhiyun }
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun void via_clock_init(struct via_clock *clock, int gfx_chip);
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun #endif /* __VIA_CLOCK_H__ */
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