1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved. 4*4882a593Smuzhiyun * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved. 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef __DVI_H__ 9*4882a593Smuzhiyun #define __DVI_H__ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun /*Definition TMDS Device ID register*/ 12*4882a593Smuzhiyun #define VT1632_DEVICE_ID_REG 0x02 13*4882a593Smuzhiyun #define VT1632_DEVICE_ID 0x92 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #define GET_DVI_SIZE_BY_SYSTEM_BIOS 0x01 16*4882a593Smuzhiyun #define GET_DVI_SIZE_BY_VGA_BIOS 0x02 17*4882a593Smuzhiyun #define GET_DVI_SZIE_BY_HW_STRAPPING 0x03 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun /* Definition DVI Panel ID*/ 20*4882a593Smuzhiyun /* Resolution: 640x480, Channel: single, Dithering: Enable */ 21*4882a593Smuzhiyun #define DVI_PANEL_ID0_640X480 0x00 22*4882a593Smuzhiyun /* Resolution: 800x600, Channel: single, Dithering: Enable */ 23*4882a593Smuzhiyun #define DVI_PANEL_ID1_800x600 0x01 24*4882a593Smuzhiyun /* Resolution: 1024x768, Channel: single, Dithering: Enable */ 25*4882a593Smuzhiyun #define DVI_PANEL_ID1_1024x768 0x02 26*4882a593Smuzhiyun /* Resolution: 1280x768, Channel: single, Dithering: Enable */ 27*4882a593Smuzhiyun #define DVI_PANEL_ID1_1280x768 0x03 28*4882a593Smuzhiyun /* Resolution: 1280x1024, Channel: dual, Dithering: Enable */ 29*4882a593Smuzhiyun #define DVI_PANEL_ID1_1280x1024 0x04 30*4882a593Smuzhiyun /* Resolution: 1400x1050, Channel: dual, Dithering: Enable */ 31*4882a593Smuzhiyun #define DVI_PANEL_ID1_1400x1050 0x05 32*4882a593Smuzhiyun /* Resolution: 1600x1200, Channel: dual, Dithering: Enable */ 33*4882a593Smuzhiyun #define DVI_PANEL_ID1_1600x1200 0x06 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun /* Define the version of EDID*/ 36*4882a593Smuzhiyun #define EDID_VERSION_1 1 37*4882a593Smuzhiyun #define EDID_VERSION_2 2 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun #define DEV_CONNECT_DVI 0x01 40*4882a593Smuzhiyun #define DEV_CONNECT_HDMI 0x02 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun int viafb_dvi_sense(void); 43*4882a593Smuzhiyun void viafb_dvi_disable(void); 44*4882a593Smuzhiyun void viafb_dvi_enable(void); 45*4882a593Smuzhiyun bool viafb_tmds_trasmitter_identify(void); 46*4882a593Smuzhiyun void viafb_init_dvi_size(struct tmds_chip_information *tmds_chip, 47*4882a593Smuzhiyun struct tmds_setting_information *tmds_setting); 48*4882a593Smuzhiyun void viafb_dvi_set_mode(const struct fb_var_screeninfo *var, 49*4882a593Smuzhiyun u16 cxres, u16 cyres, int iga); 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun #endif /* __DVI_H__ */ 52