1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved. 4*4882a593Smuzhiyun * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved. 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun #ifndef __CHIP_H__ 8*4882a593Smuzhiyun #define __CHIP_H__ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #include "global.h" 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun /***************************************/ 13*4882a593Smuzhiyun /* Definition Graphic Chip Information */ 14*4882a593Smuzhiyun /***************************************/ 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun #define PCI_VIA_VENDOR_ID 0x1106 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun /* Define VIA Graphic Chip Name */ 19*4882a593Smuzhiyun #define UNICHROME_CLE266 1 20*4882a593Smuzhiyun #define UNICHROME_CLE266_DID 0x3122 21*4882a593Smuzhiyun #define CLE266_REVISION_AX 0x0A 22*4882a593Smuzhiyun #define CLE266_REVISION_CX 0x0C 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun #define UNICHROME_K400 2 25*4882a593Smuzhiyun #define UNICHROME_K400_DID 0x7205 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun #define UNICHROME_K800 3 28*4882a593Smuzhiyun #define UNICHROME_K800_DID 0x3108 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun #define UNICHROME_PM800 4 31*4882a593Smuzhiyun #define UNICHROME_PM800_DID 0x3118 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun #define UNICHROME_CN700 5 34*4882a593Smuzhiyun #define UNICHROME_CN700_DID 0x3344 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun #define UNICHROME_CX700 6 37*4882a593Smuzhiyun #define UNICHROME_CX700_DID 0x3157 38*4882a593Smuzhiyun #define CX700_REVISION_700 0x0 39*4882a593Smuzhiyun #define CX700_REVISION_700M 0x1 40*4882a593Smuzhiyun #define CX700_REVISION_700M2 0x2 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun #define UNICHROME_CN750 7 43*4882a593Smuzhiyun #define UNICHROME_CN750_DID 0x3225 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun #define UNICHROME_K8M890 8 46*4882a593Smuzhiyun #define UNICHROME_K8M890_DID 0x3230 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun #define UNICHROME_P4M890 9 49*4882a593Smuzhiyun #define UNICHROME_P4M890_DID 0x3343 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun #define UNICHROME_P4M900 10 52*4882a593Smuzhiyun #define UNICHROME_P4M900_DID 0x3371 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun #define UNICHROME_VX800 11 55*4882a593Smuzhiyun #define UNICHROME_VX800_DID 0x1122 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun #define UNICHROME_VX855 12 58*4882a593Smuzhiyun #define UNICHROME_VX855_DID 0x5122 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun #define UNICHROME_VX900 13 61*4882a593Smuzhiyun #define UNICHROME_VX900_DID 0x7122 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun /**************************************************/ 64*4882a593Smuzhiyun /* Definition TMDS Trasmitter Information */ 65*4882a593Smuzhiyun /**************************************************/ 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun /* Definition TMDS Trasmitter Index */ 68*4882a593Smuzhiyun #define NON_TMDS_TRANSMITTER 0x00 69*4882a593Smuzhiyun #define VT1632_TMDS 0x01 70*4882a593Smuzhiyun #define INTEGRATED_TMDS 0x42 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun /* Definition TMDS Trasmitter I2C Slave Address */ 73*4882a593Smuzhiyun #define VT1632_TMDS_I2C_ADDR 0x10 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun /**************************************************/ 76*4882a593Smuzhiyun /* Definition LVDS Trasmitter Information */ 77*4882a593Smuzhiyun /**************************************************/ 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun /* Definition LVDS Trasmitter Index */ 80*4882a593Smuzhiyun #define NON_LVDS_TRANSMITTER 0x00 81*4882a593Smuzhiyun #define VT1631_LVDS 0x01 82*4882a593Smuzhiyun #define VT1636_LVDS 0x0E 83*4882a593Smuzhiyun #define INTEGRATED_LVDS 0x41 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun /* Definition Digital Transmitter Mode */ 86*4882a593Smuzhiyun #define TX_DATA_12_BITS 0x01 87*4882a593Smuzhiyun #define TX_DATA_24_BITS 0x02 88*4882a593Smuzhiyun #define TX_DATA_DDR_MODE 0x04 89*4882a593Smuzhiyun #define TX_DATA_SDR_MODE 0x08 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun /* Definition LVDS Trasmitter I2C Slave Address */ 92*4882a593Smuzhiyun #define VT1631_LVDS_I2C_ADDR 0x70 93*4882a593Smuzhiyun #define VT3271_LVDS_I2C_ADDR 0x80 94*4882a593Smuzhiyun #define VT1636_LVDS_I2C_ADDR 0x80 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun struct tmds_chip_information { 97*4882a593Smuzhiyun int tmds_chip_name; 98*4882a593Smuzhiyun int tmds_chip_slave_addr; 99*4882a593Smuzhiyun int output_interface; 100*4882a593Smuzhiyun int i2c_port; 101*4882a593Smuzhiyun }; 102*4882a593Smuzhiyun 103*4882a593Smuzhiyun struct lvds_chip_information { 104*4882a593Smuzhiyun int lvds_chip_name; 105*4882a593Smuzhiyun int lvds_chip_slave_addr; 106*4882a593Smuzhiyun int output_interface; 107*4882a593Smuzhiyun int i2c_port; 108*4882a593Smuzhiyun }; 109*4882a593Smuzhiyun 110*4882a593Smuzhiyun /* The type of 2D engine */ 111*4882a593Smuzhiyun enum via_2d_engine { 112*4882a593Smuzhiyun VIA_2D_ENG_H2, 113*4882a593Smuzhiyun VIA_2D_ENG_H5, 114*4882a593Smuzhiyun VIA_2D_ENG_M1, 115*4882a593Smuzhiyun }; 116*4882a593Smuzhiyun 117*4882a593Smuzhiyun struct chip_information { 118*4882a593Smuzhiyun int gfx_chip_name; 119*4882a593Smuzhiyun int gfx_chip_revision; 120*4882a593Smuzhiyun enum via_2d_engine twod_engine; 121*4882a593Smuzhiyun struct tmds_chip_information tmds_chip_info; 122*4882a593Smuzhiyun struct lvds_chip_information lvds_chip_info; 123*4882a593Smuzhiyun struct lvds_chip_information lvds_chip_info2; 124*4882a593Smuzhiyun }; 125*4882a593Smuzhiyun 126*4882a593Smuzhiyun struct tmds_setting_information { 127*4882a593Smuzhiyun int iga_path; 128*4882a593Smuzhiyun int h_active; 129*4882a593Smuzhiyun int v_active; 130*4882a593Smuzhiyun int max_pixel_clock; 131*4882a593Smuzhiyun }; 132*4882a593Smuzhiyun 133*4882a593Smuzhiyun struct lvds_setting_information { 134*4882a593Smuzhiyun int iga_path; 135*4882a593Smuzhiyun int lcd_panel_hres; 136*4882a593Smuzhiyun int lcd_panel_vres; 137*4882a593Smuzhiyun int display_method; 138*4882a593Smuzhiyun int device_lcd_dualedge; 139*4882a593Smuzhiyun int LCDDithering; 140*4882a593Smuzhiyun int lcd_mode; 141*4882a593Smuzhiyun u32 vclk; /*panel mode clock value */ 142*4882a593Smuzhiyun }; 143*4882a593Smuzhiyun 144*4882a593Smuzhiyun struct GFX_DPA_SETTING { 145*4882a593Smuzhiyun int ClkRangeIndex; 146*4882a593Smuzhiyun u8 DVP0; /* CR96[3:0] */ 147*4882a593Smuzhiyun u8 DVP0DataDri_S1; /* SR2A[5] */ 148*4882a593Smuzhiyun u8 DVP0DataDri_S; /* SR1B[1] */ 149*4882a593Smuzhiyun u8 DVP0ClockDri_S1; /* SR2A[4] */ 150*4882a593Smuzhiyun u8 DVP0ClockDri_S; /* SR1E[2] */ 151*4882a593Smuzhiyun u8 DVP1; /* CR9B[3:0] */ 152*4882a593Smuzhiyun u8 DVP1Driving; /* SR65[3:0], Data and Clock driving */ 153*4882a593Smuzhiyun u8 DFPHigh; /* CR97[3:0] */ 154*4882a593Smuzhiyun u8 DFPLow; /* CR99[3:0] */ 155*4882a593Smuzhiyun 156*4882a593Smuzhiyun }; 157*4882a593Smuzhiyun 158*4882a593Smuzhiyun struct VT1636_DPA_SETTING { 159*4882a593Smuzhiyun u8 CLK_SEL_ST1; 160*4882a593Smuzhiyun u8 CLK_SEL_ST2; 161*4882a593Smuzhiyun }; 162*4882a593Smuzhiyun #endif /* __CHIP_H__ */ 163