1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Silicon Motion SM712 frame buffer device
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * Copyright (C) 2006 Silicon Motion Technology Corp.
5*4882a593Smuzhiyun * Authors: Ge Wang, gewang@siliconmotion.com
6*4882a593Smuzhiyun * Boyod boyod.yang@siliconmotion.com.cn
7*4882a593Smuzhiyun *
8*4882a593Smuzhiyun * Copyright (C) 2009 Lemote, Inc.
9*4882a593Smuzhiyun * Author: Wu Zhangjin, wuzhangjin@gmail.com
10*4882a593Smuzhiyun *
11*4882a593Smuzhiyun * This file is subject to the terms and conditions of the GNU General Public
12*4882a593Smuzhiyun * License. See the file COPYING in the main directory of this archive for
13*4882a593Smuzhiyun * more details.
14*4882a593Smuzhiyun */
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun #define FB_ACCEL_SMI_LYNX 88
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun #define SCREEN_X_RES 1024
19*4882a593Smuzhiyun #define SCREEN_Y_RES_PC 768
20*4882a593Smuzhiyun #define SCREEN_Y_RES_NETBOOK 600
21*4882a593Smuzhiyun #define SCREEN_BPP 16
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun #define dac_reg (0x3c8)
24*4882a593Smuzhiyun #define dac_val (0x3c9)
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun extern void __iomem *smtc_regbaseaddress;
27*4882a593Smuzhiyun #define smtc_mmiowb(dat, reg) writeb(dat, smtc_regbaseaddress + reg)
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun #define smtc_mmiorb(reg) readb(smtc_regbaseaddress + reg)
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun #define SIZE_SR00_SR04 (0x04 - 0x00 + 1)
32*4882a593Smuzhiyun #define SIZE_SR10_SR24 (0x24 - 0x10 + 1)
33*4882a593Smuzhiyun #define SIZE_SR30_SR75 (0x75 - 0x30 + 1)
34*4882a593Smuzhiyun #define SIZE_SR80_SR93 (0x93 - 0x80 + 1)
35*4882a593Smuzhiyun #define SIZE_SRA0_SRAF (0xAF - 0xA0 + 1)
36*4882a593Smuzhiyun #define SIZE_GR00_GR08 (0x08 - 0x00 + 1)
37*4882a593Smuzhiyun #define SIZE_AR00_AR14 (0x14 - 0x00 + 1)
38*4882a593Smuzhiyun #define SIZE_CR00_CR18 (0x18 - 0x00 + 1)
39*4882a593Smuzhiyun #define SIZE_CR30_CR4D (0x4D - 0x30 + 1)
40*4882a593Smuzhiyun #define SIZE_CR90_CRA7 (0xA7 - 0x90 + 1)
41*4882a593Smuzhiyun
smtc_crtcw(int reg,int val)42*4882a593Smuzhiyun static inline void smtc_crtcw(int reg, int val)
43*4882a593Smuzhiyun {
44*4882a593Smuzhiyun smtc_mmiowb(reg, 0x3d4);
45*4882a593Smuzhiyun smtc_mmiowb(val, 0x3d5);
46*4882a593Smuzhiyun }
47*4882a593Smuzhiyun
smtc_grphw(int reg,int val)48*4882a593Smuzhiyun static inline void smtc_grphw(int reg, int val)
49*4882a593Smuzhiyun {
50*4882a593Smuzhiyun smtc_mmiowb(reg, 0x3ce);
51*4882a593Smuzhiyun smtc_mmiowb(val, 0x3cf);
52*4882a593Smuzhiyun }
53*4882a593Smuzhiyun
smtc_attrw(int reg,int val)54*4882a593Smuzhiyun static inline void smtc_attrw(int reg, int val)
55*4882a593Smuzhiyun {
56*4882a593Smuzhiyun smtc_mmiorb(0x3da);
57*4882a593Smuzhiyun smtc_mmiowb(reg, 0x3c0);
58*4882a593Smuzhiyun smtc_mmiorb(0x3c1);
59*4882a593Smuzhiyun smtc_mmiowb(val, 0x3c0);
60*4882a593Smuzhiyun }
61*4882a593Smuzhiyun
smtc_seqw(int reg,int val)62*4882a593Smuzhiyun static inline void smtc_seqw(int reg, int val)
63*4882a593Smuzhiyun {
64*4882a593Smuzhiyun smtc_mmiowb(reg, 0x3c4);
65*4882a593Smuzhiyun smtc_mmiowb(val, 0x3c5);
66*4882a593Smuzhiyun }
67*4882a593Smuzhiyun
smtc_seqr(int reg)68*4882a593Smuzhiyun static inline unsigned int smtc_seqr(int reg)
69*4882a593Smuzhiyun {
70*4882a593Smuzhiyun smtc_mmiowb(reg, 0x3c4);
71*4882a593Smuzhiyun return smtc_mmiorb(0x3c5);
72*4882a593Smuzhiyun }
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun /* The next structure holds all information relevant for a specific video mode.
75*4882a593Smuzhiyun */
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun struct modeinit {
78*4882a593Smuzhiyun int mmsizex;
79*4882a593Smuzhiyun int mmsizey;
80*4882a593Smuzhiyun int bpp;
81*4882a593Smuzhiyun int hz;
82*4882a593Smuzhiyun unsigned char init_misc;
83*4882a593Smuzhiyun unsigned char init_sr00_sr04[SIZE_SR00_SR04];
84*4882a593Smuzhiyun unsigned char init_sr10_sr24[SIZE_SR10_SR24];
85*4882a593Smuzhiyun unsigned char init_sr30_sr75[SIZE_SR30_SR75];
86*4882a593Smuzhiyun unsigned char init_sr80_sr93[SIZE_SR80_SR93];
87*4882a593Smuzhiyun unsigned char init_sra0_sraf[SIZE_SRA0_SRAF];
88*4882a593Smuzhiyun unsigned char init_gr00_gr08[SIZE_GR00_GR08];
89*4882a593Smuzhiyun unsigned char init_ar00_ar14[SIZE_AR00_AR14];
90*4882a593Smuzhiyun unsigned char init_cr00_cr18[SIZE_CR00_CR18];
91*4882a593Smuzhiyun unsigned char init_cr30_cr4d[SIZE_CR30_CR4D];
92*4882a593Smuzhiyun unsigned char init_cr90_cra7[SIZE_CR90_CRA7];
93*4882a593Smuzhiyun };
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun #ifdef __BIG_ENDIAN
96*4882a593Smuzhiyun #define pal_rgb(r, g, b, val) (((r & 0xf800) >> 8) | \
97*4882a593Smuzhiyun ((g & 0xe000) >> 13) | \
98*4882a593Smuzhiyun ((g & 0x1c00) << 3) | \
99*4882a593Smuzhiyun ((b & 0xf800) >> 3))
100*4882a593Smuzhiyun #define big_addr 0x800000
101*4882a593Smuzhiyun #define mmio_addr 0x00800000
102*4882a593Smuzhiyun #define seqw17() smtc_seqw(0x17, 0x30)
103*4882a593Smuzhiyun #define big_pixel_depth(p, d) {if (p == 24) {p = 32; d = 32; } }
104*4882a593Smuzhiyun #define big_swap(p) ((p & 0xff00ff00 >> 8) | (p & 0x00ff00ff << 8))
105*4882a593Smuzhiyun #else
106*4882a593Smuzhiyun #define pal_rgb(r, g, b, val) val
107*4882a593Smuzhiyun #define big_addr 0
108*4882a593Smuzhiyun #define mmio_addr 0x00c00000
109*4882a593Smuzhiyun #define seqw17() do { } while (0)
110*4882a593Smuzhiyun #define big_pixel_depth(p, d) do { } while (0)
111*4882a593Smuzhiyun #define big_swap(p) p
112*4882a593Smuzhiyun #endif
113