xref: /OK3568_Linux_fs/kernel/drivers/video/fbdev/sis/initdef.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /* $XFree86$ */
2*4882a593Smuzhiyun /* $XdotOrg$ */
3*4882a593Smuzhiyun /*
4*4882a593Smuzhiyun  * Global definitions for init.c and init301.c
5*4882a593Smuzhiyun  *
6*4882a593Smuzhiyun  * Copyright (C) 2001-2005 by Thomas Winischhofer, Vienna, Austria
7*4882a593Smuzhiyun  *
8*4882a593Smuzhiyun  * If distributed as part of the Linux kernel, the following license terms
9*4882a593Smuzhiyun  * apply:
10*4882a593Smuzhiyun  *
11*4882a593Smuzhiyun  * * This program is free software; you can redistribute it and/or modify
12*4882a593Smuzhiyun  * * it under the terms of the GNU General Public License as published by
13*4882a593Smuzhiyun  * * the Free Software Foundation; either version 2 of the named License,
14*4882a593Smuzhiyun  * * or any later version.
15*4882a593Smuzhiyun  * *
16*4882a593Smuzhiyun  * * This program is distributed in the hope that it will be useful,
17*4882a593Smuzhiyun  * * but WITHOUT ANY WARRANTY; without even the implied warranty of
18*4882a593Smuzhiyun  * * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19*4882a593Smuzhiyun  * * GNU General Public License for more details.
20*4882a593Smuzhiyun  * *
21*4882a593Smuzhiyun  * * You should have received a copy of the GNU General Public License
22*4882a593Smuzhiyun  * * along with this program; if not, write to the Free Software
23*4882a593Smuzhiyun  * * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA
24*4882a593Smuzhiyun  *
25*4882a593Smuzhiyun  * Otherwise, the following license terms apply:
26*4882a593Smuzhiyun  *
27*4882a593Smuzhiyun  * * Redistribution and use in source and binary forms, with or without
28*4882a593Smuzhiyun  * * modification, are permitted provided that the following conditions
29*4882a593Smuzhiyun  * * are met:
30*4882a593Smuzhiyun  * * 1) Redistributions of source code must retain the above copyright
31*4882a593Smuzhiyun  * *    notice, this list of conditions and the following disclaimer.
32*4882a593Smuzhiyun  * * 2) Redistributions in binary form must reproduce the above copyright
33*4882a593Smuzhiyun  * *    notice, this list of conditions and the following disclaimer in the
34*4882a593Smuzhiyun  * *    documentation and/or other materials provided with the distribution.
35*4882a593Smuzhiyun  * * 3) The name of the author may not be used to endorse or promote products
36*4882a593Smuzhiyun  * *    derived from this software without specific prior written permission.
37*4882a593Smuzhiyun  * *
38*4882a593Smuzhiyun  * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
39*4882a593Smuzhiyun  * * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
40*4882a593Smuzhiyun  * * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
41*4882a593Smuzhiyun  * * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
42*4882a593Smuzhiyun  * * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
43*4882a593Smuzhiyun  * * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
44*4882a593Smuzhiyun  * * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
45*4882a593Smuzhiyun  * * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
46*4882a593Smuzhiyun  * * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
47*4882a593Smuzhiyun  * * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
48*4882a593Smuzhiyun  *
49*4882a593Smuzhiyun  * Author: 	Thomas Winischhofer <thomas@winischhofer.net>
50*4882a593Smuzhiyun  *
51*4882a593Smuzhiyun  */
52*4882a593Smuzhiyun 
53*4882a593Smuzhiyun #ifndef _INITDEF_
54*4882a593Smuzhiyun #define _INITDEF_
55*4882a593Smuzhiyun 
56*4882a593Smuzhiyun #define IS_SIS330		(SiS_Pr->ChipType == SIS_330)
57*4882a593Smuzhiyun #define IS_SIS550		(SiS_Pr->ChipType == SIS_550)
58*4882a593Smuzhiyun #define IS_SIS650		(SiS_Pr->ChipType == SIS_650)  /* All versions, incl 651, M65x */
59*4882a593Smuzhiyun #define IS_SIS740		(SiS_Pr->ChipType == SIS_740)
60*4882a593Smuzhiyun #define IS_SIS651	        (SiS_Pr->SiS_SysFlags & (SF_Is651 | SF_Is652))
61*4882a593Smuzhiyun #define IS_SISM650	        (SiS_Pr->SiS_SysFlags & (SF_IsM650 | SF_IsM652 | SF_IsM653))
62*4882a593Smuzhiyun #define IS_SIS65x               (IS_SIS651 || IS_SISM650)       /* Only special versions of 65x */
63*4882a593Smuzhiyun #define IS_SIS661		(SiS_Pr->ChipType == SIS_661)
64*4882a593Smuzhiyun #define IS_SIS741		(SiS_Pr->ChipType == SIS_741)
65*4882a593Smuzhiyun #define IS_SIS660		(SiS_Pr->ChipType == SIS_660)
66*4882a593Smuzhiyun #define IS_SIS760		(SiS_Pr->ChipType == SIS_760)
67*4882a593Smuzhiyun #define IS_SIS761		(SiS_Pr->ChipType == SIS_761)
68*4882a593Smuzhiyun #define IS_SIS661741660760	(IS_SIS661 || IS_SIS741 || IS_SIS660 || IS_SIS760 || IS_SIS761)
69*4882a593Smuzhiyun #define IS_SIS650740            ((SiS_Pr->ChipType >= SIS_650) && (SiS_Pr->ChipType < SIS_330))
70*4882a593Smuzhiyun #define IS_SIS550650740         (IS_SIS550 || IS_SIS650740)
71*4882a593Smuzhiyun #define IS_SIS650740660         (IS_SIS650 || IS_SIS740 || IS_SIS661741660760)
72*4882a593Smuzhiyun #define IS_SIS550650740660      (IS_SIS550 || IS_SIS650740660)
73*4882a593Smuzhiyun 
74*4882a593Smuzhiyun #define SISGETROMW(x)		(ROMAddr[(x)] | (ROMAddr[(x)+1] << 8))
75*4882a593Smuzhiyun 
76*4882a593Smuzhiyun /* SiS_VBType */
77*4882a593Smuzhiyun #define VB_SIS301		0x0001
78*4882a593Smuzhiyun #define VB_SIS301B		0x0002
79*4882a593Smuzhiyun #define VB_SIS302B		0x0004
80*4882a593Smuzhiyun #define VB_SIS301LV		0x0008
81*4882a593Smuzhiyun #define VB_SIS302LV		0x0010
82*4882a593Smuzhiyun #define VB_SIS302ELV		0x0020
83*4882a593Smuzhiyun #define VB_SIS301C		0x0040
84*4882a593Smuzhiyun #define VB_SIS307T		0x0080
85*4882a593Smuzhiyun #define VB_SIS307LV		0x0100
86*4882a593Smuzhiyun #define VB_UMC			0x4000
87*4882a593Smuzhiyun #define VB_NoLCD        	0x8000
88*4882a593Smuzhiyun #define VB_SIS30xB		(VB_SIS301B | VB_SIS301C | VB_SIS302B | VB_SIS307T)
89*4882a593Smuzhiyun #define VB_SIS30xC		(VB_SIS301C | VB_SIS307T)
90*4882a593Smuzhiyun #define VB_SISTMDS		(VB_SIS301 | VB_SIS301B | VB_SIS301C | VB_SIS302B | VB_SIS307T)
91*4882a593Smuzhiyun #define VB_SISLVDS		(VB_SIS301LV | VB_SIS302LV | VB_SIS302ELV | VB_SIS307LV)
92*4882a593Smuzhiyun #define VB_SIS30xBLV		(VB_SIS30xB | VB_SISLVDS)
93*4882a593Smuzhiyun #define VB_SIS30xCLV		(VB_SIS30xC | VB_SIS302ELV | VB_SIS307LV)
94*4882a593Smuzhiyun #define VB_SISVB		(VB_SIS301 | VB_SIS30xBLV)
95*4882a593Smuzhiyun #define VB_SISLCDA		(VB_SIS302B | VB_SIS301C  | VB_SIS307T  | VB_SISLVDS)
96*4882a593Smuzhiyun #define VB_SISTMDSLCDA		(VB_SIS301C | VB_SIS307T)
97*4882a593Smuzhiyun #define VB_SISPART4SCALER	(VB_SIS301C | VB_SIS307T | VB_SIS302ELV | VB_SIS307LV)
98*4882a593Smuzhiyun #define VB_SISHIVISION		(VB_SIS301 | VB_SIS301B | VB_SIS302B)
99*4882a593Smuzhiyun #define VB_SISYPBPR		(VB_SIS301C | VB_SIS307T  | VB_SIS301LV | VB_SIS302LV | VB_SIS302ELV | VB_SIS307LV)
100*4882a593Smuzhiyun #define VB_SISTAP4SCALER	(VB_SIS301C | VB_SIS307T | VB_SIS302ELV | VB_SIS307LV)
101*4882a593Smuzhiyun #define VB_SISPART4OVERFLOW	(VB_SIS301C | VB_SIS307T | VB_SIS302LV | VB_SIS302ELV | VB_SIS307LV)
102*4882a593Smuzhiyun #define VB_SISPWD		(VB_SIS301C | VB_SIS307T | VB_SISLVDS)
103*4882a593Smuzhiyun #define VB_SISEMI		(VB_SIS302LV | VB_SIS302ELV | VB_SIS307LV)
104*4882a593Smuzhiyun #define VB_SISPOWER		(VB_SIS301C | VB_SIS307T | VB_SIS302LV | VB_SIS302ELV | VB_SIS307LV)
105*4882a593Smuzhiyun #define VB_SISDUALLINK		(VB_SIS302LV | VB_SIS302ELV | VB_SIS307T | VB_SIS307LV)
106*4882a593Smuzhiyun #define VB_SISVGA2		VB_SISTMDS
107*4882a593Smuzhiyun #define VB_SISRAMDAC202		(VB_SIS301C | VB_SIS307T)
108*4882a593Smuzhiyun 
109*4882a593Smuzhiyun /* VBInfo */
110*4882a593Smuzhiyun #define SetSimuScanMode         0x0001   /* CR 30 */
111*4882a593Smuzhiyun #define SwitchCRT2              0x0002
112*4882a593Smuzhiyun #define SetCRT2ToAVIDEO         0x0004
113*4882a593Smuzhiyun #define SetCRT2ToSVIDEO         0x0008
114*4882a593Smuzhiyun #define SetCRT2ToSCART          0x0010
115*4882a593Smuzhiyun #define SetCRT2ToLCD            0x0020
116*4882a593Smuzhiyun #define SetCRT2ToRAMDAC         0x0040
117*4882a593Smuzhiyun #define SetCRT2ToHiVision       0x0080   		/* for SiS bridge */
118*4882a593Smuzhiyun #define SetCRT2ToCHYPbPr       	SetCRT2ToHiVision	/* for Chrontel   */
119*4882a593Smuzhiyun #define SetNTSCTV               0x0000   /* CR 31 */
120*4882a593Smuzhiyun #define SetPALTV                0x0100   		/* Deprecated here, now in TVMode */
121*4882a593Smuzhiyun #define SetInSlaveMode          0x0200
122*4882a593Smuzhiyun #define SetNotSimuMode          0x0400
123*4882a593Smuzhiyun #define SetNotSimuTVMode        SetNotSimuMode
124*4882a593Smuzhiyun #define SetDispDevSwitch        0x0800
125*4882a593Smuzhiyun #define SetCRT2ToYPbPr525750    0x0800
126*4882a593Smuzhiyun #define LoadDACFlag             0x1000
127*4882a593Smuzhiyun #define DisableCRT2Display      0x2000
128*4882a593Smuzhiyun #define DriverMode              0x4000
129*4882a593Smuzhiyun #define HotKeySwitch            0x8000
130*4882a593Smuzhiyun #define SetCRT2ToLCDA           0x8000
131*4882a593Smuzhiyun 
132*4882a593Smuzhiyun /* v-- Needs change in sis_vga.c if changed (GPIO) --v */
133*4882a593Smuzhiyun #define SetCRT2ToTV             (SetCRT2ToYPbPr525750|SetCRT2ToHiVision|SetCRT2ToSCART|SetCRT2ToSVIDEO|SetCRT2ToAVIDEO)
134*4882a593Smuzhiyun #define SetCRT2ToTVNoYPbPrHiVision (SetCRT2ToSCART | SetCRT2ToSVIDEO | SetCRT2ToAVIDEO)
135*4882a593Smuzhiyun #define SetCRT2ToTVNoHiVision  	(SetCRT2ToYPbPr525750 | SetCRT2ToSCART | SetCRT2ToSVIDEO | SetCRT2ToAVIDEO)
136*4882a593Smuzhiyun 
137*4882a593Smuzhiyun /* SiS_ModeType */
138*4882a593Smuzhiyun #define ModeText                0x00
139*4882a593Smuzhiyun #define ModeCGA                 0x01
140*4882a593Smuzhiyun #define ModeEGA                 0x02
141*4882a593Smuzhiyun #define ModeVGA                 0x03
142*4882a593Smuzhiyun #define Mode15Bpp               0x04
143*4882a593Smuzhiyun #define Mode16Bpp               0x05
144*4882a593Smuzhiyun #define Mode24Bpp               0x06
145*4882a593Smuzhiyun #define Mode32Bpp               0x07
146*4882a593Smuzhiyun 
147*4882a593Smuzhiyun #define ModeTypeMask            0x07
148*4882a593Smuzhiyun #define IsTextMode              0x07
149*4882a593Smuzhiyun 
150*4882a593Smuzhiyun #define DACInfoFlag             0x0018
151*4882a593Smuzhiyun #define MemoryInfoFlag          0x01E0
152*4882a593Smuzhiyun #define MemorySizeShift         5
153*4882a593Smuzhiyun 
154*4882a593Smuzhiyun /* modeflag */
155*4882a593Smuzhiyun #define Charx8Dot               0x0200
156*4882a593Smuzhiyun #define LineCompareOff          0x0400
157*4882a593Smuzhiyun #define CRT2Mode                0x0800
158*4882a593Smuzhiyun #define HalfDCLK                0x1000
159*4882a593Smuzhiyun #define NoSupportSimuTV         0x2000
160*4882a593Smuzhiyun #define NoSupportLCDScale	0x4000 /* SiS bridge: No scaling possible (no matter what panel) */
161*4882a593Smuzhiyun #define DoubleScanMode          0x8000
162*4882a593Smuzhiyun 
163*4882a593Smuzhiyun /* Infoflag */
164*4882a593Smuzhiyun #define SupportTV               0x0008
165*4882a593Smuzhiyun #define SupportTV1024           0x0800
166*4882a593Smuzhiyun #define SupportCHTV 		0x0800
167*4882a593Smuzhiyun #define Support64048060Hz       0x0800  /* Special for 640x480 LCD */
168*4882a593Smuzhiyun #define SupportHiVision         0x0010
169*4882a593Smuzhiyun #define SupportYPbPr750p        0x1000
170*4882a593Smuzhiyun #define SupportLCD              0x0020
171*4882a593Smuzhiyun #define SupportRAMDAC2          0x0040	/* All           (<= 100Mhz) */
172*4882a593Smuzhiyun #define SupportRAMDAC2_135      0x0100  /* All except DH (<= 135Mhz) */
173*4882a593Smuzhiyun #define SupportRAMDAC2_162      0x0200  /* B, C          (<= 162Mhz) */
174*4882a593Smuzhiyun #define SupportRAMDAC2_202      0x0400  /* C             (<= 202Mhz) */
175*4882a593Smuzhiyun #define InterlaceMode           0x0080
176*4882a593Smuzhiyun #define SyncPP                  0x0000
177*4882a593Smuzhiyun #define HaveWideTiming		0x2000	/* Have specific wide- and non-wide timing */
178*4882a593Smuzhiyun #define SyncPN                  0x4000
179*4882a593Smuzhiyun #define SyncNP                  0x8000
180*4882a593Smuzhiyun #define SyncNN                  0xc000
181*4882a593Smuzhiyun 
182*4882a593Smuzhiyun /* SetFlag */
183*4882a593Smuzhiyun #define ProgrammingCRT2         0x0001
184*4882a593Smuzhiyun #define LowModeTests		0x0002
185*4882a593Smuzhiyun /* #define TVSimuMode           0x0002 - deprecated */
186*4882a593Smuzhiyun /* #define RPLLDIV2XO           0x0004 - deprecated */
187*4882a593Smuzhiyun #define LCDVESATiming           0x0008
188*4882a593Smuzhiyun #define EnableLVDSDDA           0x0010
189*4882a593Smuzhiyun #define SetDispDevSwitchFlag    0x0020
190*4882a593Smuzhiyun #define CheckWinDos             0x0040
191*4882a593Smuzhiyun #define SetDOSMode              0x0080
192*4882a593Smuzhiyun 
193*4882a593Smuzhiyun /* TVMode flag */
194*4882a593Smuzhiyun #define TVSetPAL		0x0001
195*4882a593Smuzhiyun #define TVSetNTSCJ		0x0002
196*4882a593Smuzhiyun #define TVSetPALM		0x0004
197*4882a593Smuzhiyun #define TVSetPALN		0x0008
198*4882a593Smuzhiyun #define TVSetCHOverScan		0x0010
199*4882a593Smuzhiyun #define TVSetYPbPr525i		0x0020 /* new 0x10 */
200*4882a593Smuzhiyun #define TVSetYPbPr525p		0x0040 /* new 0x20 */
201*4882a593Smuzhiyun #define TVSetYPbPr750p		0x0080 /* new 0x40 */
202*4882a593Smuzhiyun #define TVSetHiVision		0x0100 /* new 0x80; = 1080i, software-wise identical */
203*4882a593Smuzhiyun #define TVSetTVSimuMode		0x0200 /* new 0x200, prev. 0x800 */
204*4882a593Smuzhiyun #define TVRPLLDIV2XO		0x0400 /* prev 0x1000 */
205*4882a593Smuzhiyun #define TVSetNTSC1024		0x0800 /* new 0x100, prev. 0x2000 */
206*4882a593Smuzhiyun #define TVSet525p1024		0x1000 /* TW */
207*4882a593Smuzhiyun #define TVAspect43		0x2000
208*4882a593Smuzhiyun #define TVAspect169		0x4000
209*4882a593Smuzhiyun #define TVAspect43LB		0x8000
210*4882a593Smuzhiyun 
211*4882a593Smuzhiyun /* YPbPr flag (>=315, <661; converted to TVMode) */
212*4882a593Smuzhiyun #define YPbPr525p               0x0001
213*4882a593Smuzhiyun #define YPbPr750p               0x0002
214*4882a593Smuzhiyun #define YPbPr525i               0x0004
215*4882a593Smuzhiyun #define YPbPrHiVision           0x0008
216*4882a593Smuzhiyun #define YPbPrModeMask           (YPbPr750p | YPbPr525p | YPbPr525i | YPbPrHiVision)
217*4882a593Smuzhiyun 
218*4882a593Smuzhiyun /* SysFlags (to identify special versions) */
219*4882a593Smuzhiyun #define SF_Is651                0x0001
220*4882a593Smuzhiyun #define SF_IsM650               0x0002
221*4882a593Smuzhiyun #define SF_Is652		0x0004
222*4882a593Smuzhiyun #define SF_IsM652		0x0008
223*4882a593Smuzhiyun #define SF_IsM653		0x0010
224*4882a593Smuzhiyun #define SF_IsM661		0x0020
225*4882a593Smuzhiyun #define SF_IsM741		0x0040
226*4882a593Smuzhiyun #define SF_IsM760		0x0080
227*4882a593Smuzhiyun #define SF_760UMA		0x4000  /* 76x: We have UMA */
228*4882a593Smuzhiyun #define SF_760LFB		0x8000  /* 76x: We have LFB */
229*4882a593Smuzhiyun 
230*4882a593Smuzhiyun /* CR32 (Newer 630, and 315 series)
231*4882a593Smuzhiyun 
232*4882a593Smuzhiyun    [0]   VB connected with CVBS
233*4882a593Smuzhiyun    [1]   VB connected with SVHS
234*4882a593Smuzhiyun    [2]   VB connected with SCART
235*4882a593Smuzhiyun    [3]   VB connected with LCD
236*4882a593Smuzhiyun    [4]   VB connected with CRT2 (secondary VGA)
237*4882a593Smuzhiyun    [5]   CRT1 monitor is connected
238*4882a593Smuzhiyun    [6]   VB connected with Hi-Vision TV
239*4882a593Smuzhiyun    [7]   <= 330: VB connected with DVI combo connector
240*4882a593Smuzhiyun          >= 661: VB connected to YPbPr
241*4882a593Smuzhiyun */
242*4882a593Smuzhiyun 
243*4882a593Smuzhiyun /* CR35 (300 series only) */
244*4882a593Smuzhiyun #define TVOverScan              0x10
245*4882a593Smuzhiyun #define TVOverScanShift         4
246*4882a593Smuzhiyun 
247*4882a593Smuzhiyun /* CR35 (661 series only)
248*4882a593Smuzhiyun    [0]    1 = PAL, 0 = NTSC
249*4882a593Smuzhiyun    [1]    1 = NTSC-J (if D0 = 0)
250*4882a593Smuzhiyun    [2]    1 = PALM (if D0 = 1)
251*4882a593Smuzhiyun    [3]    1 = PALN (if D0 = 1)
252*4882a593Smuzhiyun    [4]    1 = Overscan (Chrontel only)
253*4882a593Smuzhiyun    [7:5]  (only if D2 in CR38 is set)
254*4882a593Smuzhiyun 	  000  525i
255*4882a593Smuzhiyun 	  001  525p
256*4882a593Smuzhiyun 	  010  750p
257*4882a593Smuzhiyun 	  011  1080i (or HiVision on 301, 301B)
258*4882a593Smuzhiyun */
259*4882a593Smuzhiyun 
260*4882a593Smuzhiyun /* CR37
261*4882a593Smuzhiyun    [0]   Set 24/18 bit (0/1) RGB to LVDS/TMDS transmitter (set by BIOS)
262*4882a593Smuzhiyun    [3:1] External chip
263*4882a593Smuzhiyun          300 series:
264*4882a593Smuzhiyun 	    001   SiS301 (never seen)
265*4882a593Smuzhiyun 	    010   LVDS
266*4882a593Smuzhiyun 	    011   LVDS + Tumpion Zurac
267*4882a593Smuzhiyun 	    100   LVDS + Chrontel 7005
268*4882a593Smuzhiyun 	    110   Chrontel 7005
269*4882a593Smuzhiyun 	  315/330 series
270*4882a593Smuzhiyun 	    001   SiS30x (never seen)
271*4882a593Smuzhiyun 	    010   LVDS
272*4882a593Smuzhiyun 	    011   LVDS + Chrontel 7019
273*4882a593Smuzhiyun 	  660 series [2:1] only:
274*4882a593Smuzhiyun 	     reserved (chip type now in CR38)
275*4882a593Smuzhiyun 	  All other combinations reserved
276*4882a593Smuzhiyun    [3]    661 only: Pass 1:1 data
277*4882a593Smuzhiyun    [4]    LVDS: 0: Panel Link expands / 1: Panel Link does not expand
278*4882a593Smuzhiyun           30x:  0: Bridge scales      / 1: Bridge does not scale = Panel scales (if possible)
279*4882a593Smuzhiyun    [5]    LCD polarity select
280*4882a593Smuzhiyun           0: VESA DMT Standard
281*4882a593Smuzhiyun 	  1: EDID 2.x defined
282*4882a593Smuzhiyun    [6]    LCD horizontal polarity select
283*4882a593Smuzhiyun           0: High active
284*4882a593Smuzhiyun 	  1: Low active
285*4882a593Smuzhiyun    [7]    LCD vertical polarity select
286*4882a593Smuzhiyun           0: High active
287*4882a593Smuzhiyun 	  1: Low active
288*4882a593Smuzhiyun */
289*4882a593Smuzhiyun 
290*4882a593Smuzhiyun /* CR37: LCDInfo */
291*4882a593Smuzhiyun #define LCDRGB18Bit           0x0001
292*4882a593Smuzhiyun #define LCDNonExpanding       0x0010
293*4882a593Smuzhiyun #define LCDSync               0x0020
294*4882a593Smuzhiyun #define LCDPass11             0x0100   /* 0: center screen, 1: Pass 1:1 data */
295*4882a593Smuzhiyun #define LCDDualLink	      0x0200
296*4882a593Smuzhiyun 
297*4882a593Smuzhiyun #define DontExpandLCD	      LCDNonExpanding
298*4882a593Smuzhiyun #define LCDNonExpandingShift       4
299*4882a593Smuzhiyun #define DontExpandLCDShift    LCDNonExpandingShift
300*4882a593Smuzhiyun #define LCDSyncBit            0x00e0
301*4882a593Smuzhiyun #define LCDSyncShift               6
302*4882a593Smuzhiyun 
303*4882a593Smuzhiyun /* CR38 (315 series) */
304*4882a593Smuzhiyun #define EnableDualEdge 		0x01
305*4882a593Smuzhiyun #define SetToLCDA		0x02   /* LCD channel A (301C/302B/30x(E)LV and 650+LVDS only) */
306*4882a593Smuzhiyun #define EnableCHScart           0x04   /* Scart on Ch7019 (unofficial definition - TW) */
307*4882a593Smuzhiyun #define EnableCHYPbPr           0x08   /* YPbPr on Ch7019 (480i HDTV); only on 650/Ch7019 systems */
308*4882a593Smuzhiyun #define EnableSiSYPbPr          0x08   /* Enable YPbPr mode (30xLV/301C only) */
309*4882a593Smuzhiyun #define EnableYPbPr525i         0x00   /* Enable 525i YPbPr mode (30xLV/301C only) (mask 0x30) */
310*4882a593Smuzhiyun #define EnableYPbPr525p         0x10   /* Enable 525p YPbPr mode (30xLV/301C only) (mask 0x30) */
311*4882a593Smuzhiyun #define EnableYPbPr750p         0x20   /* Enable 750p YPbPr mode (30xLV/301C only) (mask 0x30) */
312*4882a593Smuzhiyun #define EnableYPbPr1080i        0x30   /* Enable 1080i YPbPr mode (30xLV/301C only) (mask 0x30) */
313*4882a593Smuzhiyun #define EnablePALM              0x40   /* 1 = Set PALM */
314*4882a593Smuzhiyun #define EnablePALN              0x80   /* 1 = Set PALN */
315*4882a593Smuzhiyun #define EnableNTSCJ             EnablePALM  /* Not BIOS */
316*4882a593Smuzhiyun 
317*4882a593Smuzhiyun /* CR38 (661 and later)
318*4882a593Smuzhiyun   D[7:5]  000 No VB
319*4882a593Smuzhiyun           001 301 series VB
320*4882a593Smuzhiyun 	  010 LVDS
321*4882a593Smuzhiyun 	  011 Chrontel 7019
322*4882a593Smuzhiyun 	  100 Conexant
323*4882a593Smuzhiyun   D2      Enable YPbPr output (see CR35)
324*4882a593Smuzhiyun   D[1:0]  LCDA (like before)
325*4882a593Smuzhiyun */
326*4882a593Smuzhiyun 
327*4882a593Smuzhiyun #define EnablePALMN             0x40   /* Romflag: 1 = Allow PALM/PALN */
328*4882a593Smuzhiyun 
329*4882a593Smuzhiyun /* CR39 (650 only) */
330*4882a593Smuzhiyun #define LCDPass1_1		0x01   /* 0: center screen, 1: pass 1:1 data output  */
331*4882a593Smuzhiyun #define Enable302LV_DualLink    0x04   /* 302LV only; enable dual link */
332*4882a593Smuzhiyun 
333*4882a593Smuzhiyun /* CR39 (661 and later)
334*4882a593Smuzhiyun    D[7]   LVDS (SiS or third party)
335*4882a593Smuzhiyun    D[1:0] YPbPr Aspect Ratio
336*4882a593Smuzhiyun           00 4:3 letterbox
337*4882a593Smuzhiyun 	  01 4:3
338*4882a593Smuzhiyun 	  10 16:9
339*4882a593Smuzhiyun 	  11 4:3
340*4882a593Smuzhiyun */
341*4882a593Smuzhiyun 
342*4882a593Smuzhiyun /* CR3B (651+301C)
343*4882a593Smuzhiyun    D[1:0] YPbPr Aspect Ratio
344*4882a593Smuzhiyun           ?
345*4882a593Smuzhiyun */
346*4882a593Smuzhiyun 
347*4882a593Smuzhiyun /* CR79 (315/330 series only; not 661 and later)
348*4882a593Smuzhiyun    [3-0] Notify driver
349*4882a593Smuzhiyun          0001 Mode Switch event (set by BIOS)
350*4882a593Smuzhiyun 	 0010 Epansion On/Off event
351*4882a593Smuzhiyun 	 0011 TV UnderScan/OverScan event
352*4882a593Smuzhiyun 	 0100 Set Brightness event
353*4882a593Smuzhiyun 	 0101 Set Contrast event
354*4882a593Smuzhiyun 	 0110 Set Mute event
355*4882a593Smuzhiyun 	 0111 Set Volume Up/Down event
356*4882a593Smuzhiyun    [4]   Enable Backlight Control by BIOS/driver
357*4882a593Smuzhiyun          (set by driver; set means that the BIOS should
358*4882a593Smuzhiyun 	 not touch the backlight registers because eg.
359*4882a593Smuzhiyun 	 the driver already switched off the backlight)
360*4882a593Smuzhiyun    [5]   PAL/NTSC (set by BIOS)
361*4882a593Smuzhiyun    [6]   Expansion On/Off (set by BIOS; copied to CR32[4])
362*4882a593Smuzhiyun    [7]   TV UnderScan/OverScan (set by BIOS)
363*4882a593Smuzhiyun */
364*4882a593Smuzhiyun 
365*4882a593Smuzhiyun /* CR7C - 661 and later
366*4882a593Smuzhiyun    [7]   DualEdge enabled (or: to be enabled)
367*4882a593Smuzhiyun    [6]   CRT2 = TV/LCD/VGA enabled (or: to be enabled)
368*4882a593Smuzhiyun    [5]   Init done (set at end of SiS_Init)
369*4882a593Smuzhiyun    {4]   LVDS LCD capabilities
370*4882a593Smuzhiyun    [3]   LVDS LCD capabilities
371*4882a593Smuzhiyun    [2]   LVDS LCD capabilities (PWD)
372*4882a593Smuzhiyun    [1]   LVDS LCD capabilities (PWD)
373*4882a593Smuzhiyun    [0]   LVDS=1, TMDS=0 (SiS or third party)
374*4882a593Smuzhiyun */
375*4882a593Smuzhiyun 
376*4882a593Smuzhiyun /* CR7E - 661 and later
377*4882a593Smuzhiyun    VBType:
378*4882a593Smuzhiyun    [7] LVDS (third party)
379*4882a593Smuzhiyun    [3] 301C
380*4882a593Smuzhiyun    [2] 302LV
381*4882a593Smuzhiyun    [1] 301LV
382*4882a593Smuzhiyun    [0] 301B
383*4882a593Smuzhiyun */
384*4882a593Smuzhiyun 
385*4882a593Smuzhiyun /* LCDResInfo */
386*4882a593Smuzhiyun #define Panel300_800x600        0x01	/* CR36 */
387*4882a593Smuzhiyun #define Panel300_1024x768       0x02
388*4882a593Smuzhiyun #define Panel300_1280x1024      0x03
389*4882a593Smuzhiyun #define Panel300_1280x960       0x04
390*4882a593Smuzhiyun #define Panel300_640x480        0x05
391*4882a593Smuzhiyun #define Panel300_1024x600       0x06
392*4882a593Smuzhiyun #define Panel300_1152x768       0x07
393*4882a593Smuzhiyun #define Panel300_1280x768       0x0a
394*4882a593Smuzhiyun #define Panel300_Custom		0x0f
395*4882a593Smuzhiyun #define Panel300_Barco1366      0x10
396*4882a593Smuzhiyun 
397*4882a593Smuzhiyun #define Panel310_800x600        0x01
398*4882a593Smuzhiyun #define Panel310_1024x768       0x02
399*4882a593Smuzhiyun #define Panel310_1280x1024      0x03
400*4882a593Smuzhiyun #define Panel310_640x480        0x04
401*4882a593Smuzhiyun #define Panel310_1024x600       0x05
402*4882a593Smuzhiyun #define Panel310_1152x864       0x06
403*4882a593Smuzhiyun #define Panel310_1280x960       0x07
404*4882a593Smuzhiyun #define Panel310_1152x768       0x08	/* LVDS only */
405*4882a593Smuzhiyun #define Panel310_1400x1050      0x09
406*4882a593Smuzhiyun #define Panel310_1280x768       0x0a
407*4882a593Smuzhiyun #define Panel310_1600x1200      0x0b
408*4882a593Smuzhiyun #define Panel310_320x240_2      0x0c    /* xSTN */
409*4882a593Smuzhiyun #define Panel310_320x240_3      0x0d    /* xSTN */
410*4882a593Smuzhiyun #define Panel310_320x240_1      0x0e    /* xSTN - This is fake, can be any */
411*4882a593Smuzhiyun #define Panel310_Custom		0x0f
412*4882a593Smuzhiyun 
413*4882a593Smuzhiyun #define Panel661_800x600        0x01
414*4882a593Smuzhiyun #define Panel661_1024x768       0x02
415*4882a593Smuzhiyun #define Panel661_1280x1024      0x03
416*4882a593Smuzhiyun #define Panel661_640x480        0x04
417*4882a593Smuzhiyun #define Panel661_1024x600       0x05
418*4882a593Smuzhiyun #define Panel661_1152x864       0x06
419*4882a593Smuzhiyun #define Panel661_1280x960       0x07
420*4882a593Smuzhiyun #define Panel661_1280x854       0x08
421*4882a593Smuzhiyun #define Panel661_1400x1050      0x09
422*4882a593Smuzhiyun #define Panel661_1280x768       0x0a
423*4882a593Smuzhiyun #define Panel661_1600x1200      0x0b
424*4882a593Smuzhiyun #define Panel661_1280x800       0x0c
425*4882a593Smuzhiyun #define Panel661_1680x1050      0x0d
426*4882a593Smuzhiyun #define Panel661_1280x720       0x0e
427*4882a593Smuzhiyun #define Panel661_Custom		0x0f
428*4882a593Smuzhiyun 
429*4882a593Smuzhiyun #define Panel_800x600           0x01	/* Unified values */
430*4882a593Smuzhiyun #define Panel_1024x768          0x02    /* MUST match BIOS values from 0-e */
431*4882a593Smuzhiyun #define Panel_1280x1024         0x03
432*4882a593Smuzhiyun #define Panel_640x480           0x04
433*4882a593Smuzhiyun #define Panel_1024x600          0x05
434*4882a593Smuzhiyun #define Panel_1152x864          0x06
435*4882a593Smuzhiyun #define Panel_1280x960          0x07
436*4882a593Smuzhiyun #define Panel_1152x768          0x08	/* LVDS only */
437*4882a593Smuzhiyun #define Panel_1400x1050         0x09
438*4882a593Smuzhiyun #define Panel_1280x768          0x0a    /* 30xB/C and LVDS only (BIOS: all) */
439*4882a593Smuzhiyun #define Panel_1600x1200         0x0b
440*4882a593Smuzhiyun #define Panel_1280x800		0x0c    /* 661etc (TMDS) */
441*4882a593Smuzhiyun #define Panel_1680x1050         0x0d    /* 661etc  */
442*4882a593Smuzhiyun #define Panel_1280x720		0x0e    /* 661etc  */
443*4882a593Smuzhiyun #define Panel_Custom		0x0f	/* MUST BE 0x0f (for DVI DDC detection) */
444*4882a593Smuzhiyun #define Panel_320x240_1         0x10    /* SiS 550 xSTN */
445*4882a593Smuzhiyun #define Panel_Barco1366         0x11
446*4882a593Smuzhiyun #define Panel_848x480		0x12
447*4882a593Smuzhiyun #define Panel_320x240_2		0x13    /* SiS 550 xSTN */
448*4882a593Smuzhiyun #define Panel_320x240_3		0x14    /* SiS 550 xSTN */
449*4882a593Smuzhiyun #define Panel_1280x768_2        0x15	/* 30xLV */
450*4882a593Smuzhiyun #define Panel_1280x768_3        0x16    /* (unused) */
451*4882a593Smuzhiyun #define Panel_1280x800_2	0x17    /* 30xLV */
452*4882a593Smuzhiyun #define Panel_856x480		0x18
453*4882a593Smuzhiyun #define Panel_1280x854		0x19	/* 661etc */
454*4882a593Smuzhiyun 
455*4882a593Smuzhiyun /* Index in ModeResInfo table */
456*4882a593Smuzhiyun #define SIS_RI_320x200    0
457*4882a593Smuzhiyun #define SIS_RI_320x240    1
458*4882a593Smuzhiyun #define SIS_RI_320x400    2
459*4882a593Smuzhiyun #define SIS_RI_400x300    3
460*4882a593Smuzhiyun #define SIS_RI_512x384    4
461*4882a593Smuzhiyun #define SIS_RI_640x400    5
462*4882a593Smuzhiyun #define SIS_RI_640x480    6
463*4882a593Smuzhiyun #define SIS_RI_800x600    7
464*4882a593Smuzhiyun #define SIS_RI_1024x768   8
465*4882a593Smuzhiyun #define SIS_RI_1280x1024  9
466*4882a593Smuzhiyun #define SIS_RI_1600x1200 10
467*4882a593Smuzhiyun #define SIS_RI_1920x1440 11
468*4882a593Smuzhiyun #define SIS_RI_2048x1536 12
469*4882a593Smuzhiyun #define SIS_RI_720x480   13
470*4882a593Smuzhiyun #define SIS_RI_720x576   14
471*4882a593Smuzhiyun #define SIS_RI_1280x960  15
472*4882a593Smuzhiyun #define SIS_RI_800x480   16
473*4882a593Smuzhiyun #define SIS_RI_1024x576  17
474*4882a593Smuzhiyun #define SIS_RI_1280x720  18
475*4882a593Smuzhiyun #define SIS_RI_856x480   19
476*4882a593Smuzhiyun #define SIS_RI_1280x768  20
477*4882a593Smuzhiyun #define SIS_RI_1400x1050 21
478*4882a593Smuzhiyun #define SIS_RI_1152x864  22  /* Up to here SiS conforming */
479*4882a593Smuzhiyun #define SIS_RI_848x480   23
480*4882a593Smuzhiyun #define SIS_RI_1360x768  24
481*4882a593Smuzhiyun #define SIS_RI_1024x600  25
482*4882a593Smuzhiyun #define SIS_RI_1152x768  26
483*4882a593Smuzhiyun #define SIS_RI_768x576   27
484*4882a593Smuzhiyun #define SIS_RI_1360x1024 28
485*4882a593Smuzhiyun #define SIS_RI_1680x1050 29
486*4882a593Smuzhiyun #define SIS_RI_1280x800  30
487*4882a593Smuzhiyun #define SIS_RI_1920x1080 31
488*4882a593Smuzhiyun #define SIS_RI_960x540   32
489*4882a593Smuzhiyun #define SIS_RI_960x600   33
490*4882a593Smuzhiyun #define SIS_RI_1280x854  34
491*4882a593Smuzhiyun 
492*4882a593Smuzhiyun /* CR5F */
493*4882a593Smuzhiyun #define IsM650                  0x80
494*4882a593Smuzhiyun 
495*4882a593Smuzhiyun /* Timing data */
496*4882a593Smuzhiyun #define NTSCHT                  1716
497*4882a593Smuzhiyun #define NTSC2HT                 1920
498*4882a593Smuzhiyun #define NTSCVT                  525
499*4882a593Smuzhiyun #define PALHT                   1728
500*4882a593Smuzhiyun #define PALVT                   625
501*4882a593Smuzhiyun #define StHiTVHT                892
502*4882a593Smuzhiyun #define StHiTVVT                1126
503*4882a593Smuzhiyun #define StHiTextTVHT            1000
504*4882a593Smuzhiyun #define StHiTextTVVT            1126
505*4882a593Smuzhiyun #define ExtHiTVHT               2100
506*4882a593Smuzhiyun #define ExtHiTVVT               1125
507*4882a593Smuzhiyun 
508*4882a593Smuzhiyun /* Indices in (VB)VCLKData tables */
509*4882a593Smuzhiyun 
510*4882a593Smuzhiyun #define VCLK28                  0x00   /* Index in VCLKData table (300 and 315) */
511*4882a593Smuzhiyun #define VCLK40                  0x04   /* Index in VCLKData table (300 and 315) */
512*4882a593Smuzhiyun #define VCLK65_300              0x09   /* Index in VCLKData table (300) */
513*4882a593Smuzhiyun #define VCLK108_2_300           0x14   /* Index in VCLKData table (300) */
514*4882a593Smuzhiyun #define VCLK81_300		0x3f   /* Index in VCLKData table (300) */
515*4882a593Smuzhiyun #define VCLK108_3_300           0x42   /* Index in VCLKData table (300) */
516*4882a593Smuzhiyun #define VCLK100_300             0x43   /* Index in VCLKData table (300) */
517*4882a593Smuzhiyun #define VCLK34_300              0x3d   /* Index in VCLKData table (300) */
518*4882a593Smuzhiyun #define VCLK_CUSTOM_300		0x47
519*4882a593Smuzhiyun 
520*4882a593Smuzhiyun #define VCLK65_315              0x0b   /* Indices in (VB)VCLKData table (315) */
521*4882a593Smuzhiyun #define VCLK108_2_315           0x19
522*4882a593Smuzhiyun #define VCLK81_315		0x5b
523*4882a593Smuzhiyun #define VCLK162_315             0x5e
524*4882a593Smuzhiyun #define VCLK108_3_315           0x45
525*4882a593Smuzhiyun #define VCLK100_315             0x46
526*4882a593Smuzhiyun #define VCLK34_315              0x55
527*4882a593Smuzhiyun #define VCLK68_315		0x0d
528*4882a593Smuzhiyun #define VCLK_1280x800_315_2	0x5c
529*4882a593Smuzhiyun #define VCLK121_315		0x5d
530*4882a593Smuzhiyun #define VCLK130_315		0x72
531*4882a593Smuzhiyun #define VCLK_1280x720		0x5f
532*4882a593Smuzhiyun #define VCLK_1280x768_2		0x60
533*4882a593Smuzhiyun #define VCLK_1280x768_3		0x61   /* (unused?) */
534*4882a593Smuzhiyun #define VCLK_CUSTOM_315		0x62
535*4882a593Smuzhiyun #define VCLK_1280x720_2		0x63
536*4882a593Smuzhiyun #define VCLK_720x480		0x67
537*4882a593Smuzhiyun #define VCLK_720x576		0x68
538*4882a593Smuzhiyun #define VCLK_768x576		0x68
539*4882a593Smuzhiyun #define VCLK_848x480		0x65
540*4882a593Smuzhiyun #define VCLK_856x480		0x66
541*4882a593Smuzhiyun #define VCLK_800x480		0x65
542*4882a593Smuzhiyun #define VCLK_1024x576		0x51
543*4882a593Smuzhiyun #define VCLK_1152x864		0x64
544*4882a593Smuzhiyun #define VCLK_1360x768		0x58
545*4882a593Smuzhiyun #define VCLK_1280x800_315	0x6c
546*4882a593Smuzhiyun #define VCLK_1280x854		0x76
547*4882a593Smuzhiyun 
548*4882a593Smuzhiyun #define TVCLKBASE_300		0x21   /* Indices on TV clocks in VCLKData table (300) */
549*4882a593Smuzhiyun #define TVCLKBASE_315	        0x3a   /* Indices on TV clocks in (VB)VCLKData table (315) */
550*4882a593Smuzhiyun #define TVVCLKDIV2              0x00   /* Index relative to TVCLKBASE */
551*4882a593Smuzhiyun #define TVVCLK                  0x01   /* Index relative to TVCLKBASE */
552*4882a593Smuzhiyun #define HiTVVCLKDIV2            0x02   /* Index relative to TVCLKBASE */
553*4882a593Smuzhiyun #define HiTVVCLK                0x03   /* Index relative to TVCLKBASE */
554*4882a593Smuzhiyun #define HiTVSimuVCLK            0x04   /* Index relative to TVCLKBASE */
555*4882a593Smuzhiyun #define HiTVTextVCLK            0x05   /* Index relative to TVCLKBASE */
556*4882a593Smuzhiyun #define YPbPr750pVCLK		0x25   /* Index relative to TVCLKBASE; was 0x0f NOT relative */
557*4882a593Smuzhiyun 
558*4882a593Smuzhiyun /* ------------------------------ */
559*4882a593Smuzhiyun 
560*4882a593Smuzhiyun #define SetSCARTOutput          0x01
561*4882a593Smuzhiyun 
562*4882a593Smuzhiyun #define HotPlugFunction         0x08
563*4882a593Smuzhiyun 
564*4882a593Smuzhiyun #define StStructSize            0x06
565*4882a593Smuzhiyun 
566*4882a593Smuzhiyun #define SIS_VIDEO_CAPTURE       0x00 - 0x30
567*4882a593Smuzhiyun #define SIS_VIDEO_PLAYBACK      0x02 - 0x30
568*4882a593Smuzhiyun #define SIS_CRT2_PORT_04        0x04 - 0x30
569*4882a593Smuzhiyun #define SIS_CRT2_PORT_10        0x10 - 0x30
570*4882a593Smuzhiyun #define SIS_CRT2_PORT_12        0x12 - 0x30
571*4882a593Smuzhiyun #define SIS_CRT2_PORT_14        0x14 - 0x30
572*4882a593Smuzhiyun 
573*4882a593Smuzhiyun #define ADR_CRT2PtrData         0x20E
574*4882a593Smuzhiyun #define offset_Zurac            0x210   /* TW: Trumpion Zurac data pointer */
575*4882a593Smuzhiyun #define ADR_LVDSDesPtrData      0x212
576*4882a593Smuzhiyun #define ADR_LVDSCRT1DataPtr     0x214
577*4882a593Smuzhiyun #define ADR_CHTVVCLKPtr         0x216
578*4882a593Smuzhiyun #define ADR_CHTVRegDataPtr      0x218
579*4882a593Smuzhiyun 
580*4882a593Smuzhiyun #define LCDDataLen              8
581*4882a593Smuzhiyun #define HiTVDataLen             12
582*4882a593Smuzhiyun #define TVDataLen               16
583*4882a593Smuzhiyun 
584*4882a593Smuzhiyun #define LVDSDataLen             6
585*4882a593Smuzhiyun #define LVDSDesDataLen          3
586*4882a593Smuzhiyun #define ActiveNonExpanding      0x40
587*4882a593Smuzhiyun #define ActiveNonExpandingShift 6
588*4882a593Smuzhiyun #define ActivePAL               0x20
589*4882a593Smuzhiyun #define ActivePALShift          5
590*4882a593Smuzhiyun #define ModeSwitchStatus        0x0F
591*4882a593Smuzhiyun #define SoftTVType              0x40
592*4882a593Smuzhiyun #define SoftSettingAddr         0x52
593*4882a593Smuzhiyun #define ModeSettingAddr         0x53
594*4882a593Smuzhiyun 
595*4882a593Smuzhiyun #define _PanelType00             0x00
596*4882a593Smuzhiyun #define _PanelType01             0x08
597*4882a593Smuzhiyun #define _PanelType02             0x10
598*4882a593Smuzhiyun #define _PanelType03             0x18
599*4882a593Smuzhiyun #define _PanelType04             0x20
600*4882a593Smuzhiyun #define _PanelType05             0x28
601*4882a593Smuzhiyun #define _PanelType06             0x30
602*4882a593Smuzhiyun #define _PanelType07             0x38
603*4882a593Smuzhiyun #define _PanelType08             0x40
604*4882a593Smuzhiyun #define _PanelType09             0x48
605*4882a593Smuzhiyun #define _PanelType0A             0x50
606*4882a593Smuzhiyun #define _PanelType0B             0x58
607*4882a593Smuzhiyun #define _PanelType0C             0x60
608*4882a593Smuzhiyun #define _PanelType0D             0x68
609*4882a593Smuzhiyun #define _PanelType0E             0x70
610*4882a593Smuzhiyun #define _PanelType0F             0x78
611*4882a593Smuzhiyun 
612*4882a593Smuzhiyun #define PRIMARY_VGA       	0     /* 1: SiS is primary vga 0:SiS is secondary vga */
613*4882a593Smuzhiyun 
614*4882a593Smuzhiyun #define BIOSIDCodeAddr          0x235  /* Offsets to ptrs in BIOS image */
615*4882a593Smuzhiyun #define OEMUtilIDCodeAddr       0x237
616*4882a593Smuzhiyun #define VBModeIDTableAddr       0x239
617*4882a593Smuzhiyun #define OEMTVPtrAddr            0x241
618*4882a593Smuzhiyun #define PhaseTableAddr          0x243
619*4882a593Smuzhiyun #define NTSCFilterTableAddr     0x245
620*4882a593Smuzhiyun #define PALFilterTableAddr      0x247
621*4882a593Smuzhiyun #define OEMLCDPtr_1Addr         0x249
622*4882a593Smuzhiyun #define OEMLCDPtr_2Addr         0x24B
623*4882a593Smuzhiyun #define LCDHPosTable_1Addr      0x24D
624*4882a593Smuzhiyun #define LCDHPosTable_2Addr      0x24F
625*4882a593Smuzhiyun #define LCDVPosTable_1Addr      0x251
626*4882a593Smuzhiyun #define LCDVPosTable_2Addr      0x253
627*4882a593Smuzhiyun #define OEMLCDPIDTableAddr      0x255
628*4882a593Smuzhiyun 
629*4882a593Smuzhiyun #define VBModeStructSize        5
630*4882a593Smuzhiyun #define PhaseTableSize          4
631*4882a593Smuzhiyun #define FilterTableSize         4
632*4882a593Smuzhiyun #define LCDHPosTableSize        7
633*4882a593Smuzhiyun #define LCDVPosTableSize        5
634*4882a593Smuzhiyun #define OEMLVDSPIDTableSize     4
635*4882a593Smuzhiyun #define LVDSHPosTableSize       4
636*4882a593Smuzhiyun #define LVDSVPosTableSize       6
637*4882a593Smuzhiyun 
638*4882a593Smuzhiyun #define VB_ModeID               0
639*4882a593Smuzhiyun #define VB_TVTableIndex         1
640*4882a593Smuzhiyun #define VB_LCDTableIndex        2
641*4882a593Smuzhiyun #define VB_LCDHIndex            3
642*4882a593Smuzhiyun #define VB_LCDVIndex            4
643*4882a593Smuzhiyun 
644*4882a593Smuzhiyun #define OEMLCDEnable            0x0001
645*4882a593Smuzhiyun #define OEMLCDDelayEnable       0x0002
646*4882a593Smuzhiyun #define OEMLCDPOSEnable         0x0004
647*4882a593Smuzhiyun #define OEMTVEnable             0x0100
648*4882a593Smuzhiyun #define OEMTVDelayEnable        0x0200
649*4882a593Smuzhiyun #define OEMTVFlickerEnable      0x0400
650*4882a593Smuzhiyun #define OEMTVPhaseEnable        0x0800
651*4882a593Smuzhiyun #define OEMTVFilterEnable       0x1000
652*4882a593Smuzhiyun 
653*4882a593Smuzhiyun #define OEMLCDPanelIDSupport    0x0080
654*4882a593Smuzhiyun 
655*4882a593Smuzhiyun /*
656*4882a593Smuzhiyun   =============================================================
657*4882a593Smuzhiyun    		  for 315 series (old data layout)
658*4882a593Smuzhiyun   =============================================================
659*4882a593Smuzhiyun */
660*4882a593Smuzhiyun #define SoftDRAMType        0x80
661*4882a593Smuzhiyun #define SoftSetting_OFFSET  0x52
662*4882a593Smuzhiyun #define SR07_OFFSET  0x7C
663*4882a593Smuzhiyun #define SR15_OFFSET  0x7D
664*4882a593Smuzhiyun #define SR16_OFFSET  0x81
665*4882a593Smuzhiyun #define SR17_OFFSET  0x85
666*4882a593Smuzhiyun #define SR19_OFFSET  0x8D
667*4882a593Smuzhiyun #define SR1F_OFFSET  0x99
668*4882a593Smuzhiyun #define SR21_OFFSET  0x9A
669*4882a593Smuzhiyun #define SR22_OFFSET  0x9B
670*4882a593Smuzhiyun #define SR23_OFFSET  0x9C
671*4882a593Smuzhiyun #define SR24_OFFSET  0x9D
672*4882a593Smuzhiyun #define SR25_OFFSET  0x9E
673*4882a593Smuzhiyun #define SR31_OFFSET  0x9F
674*4882a593Smuzhiyun #define SR32_OFFSET  0xA0
675*4882a593Smuzhiyun #define SR33_OFFSET  0xA1
676*4882a593Smuzhiyun 
677*4882a593Smuzhiyun #define CR40_OFFSET  0xA2
678*4882a593Smuzhiyun #define SR25_1_OFFSET  0xF6
679*4882a593Smuzhiyun #define CR49_OFFSET  0xF7
680*4882a593Smuzhiyun 
681*4882a593Smuzhiyun #define VB310Data_1_2_Offset  0xB6
682*4882a593Smuzhiyun #define VB310Data_4_D_Offset  0xB7
683*4882a593Smuzhiyun #define VB310Data_4_E_Offset  0xB8
684*4882a593Smuzhiyun #define VB310Data_4_10_Offset 0xBB
685*4882a593Smuzhiyun 
686*4882a593Smuzhiyun #define RGBSenseDataOffset    0xBD
687*4882a593Smuzhiyun #define YCSenseDataOffset     0xBF
688*4882a593Smuzhiyun #define VideoSenseDataOffset  0xC1
689*4882a593Smuzhiyun #define OutputSelectOffset    0xF3
690*4882a593Smuzhiyun 
691*4882a593Smuzhiyun #define ECLK_MCLK_DISTANCE  0x14
692*4882a593Smuzhiyun #define VBIOSTablePointerStart    0x100
693*4882a593Smuzhiyun #define StandTablePtrOffset       VBIOSTablePointerStart+0x02
694*4882a593Smuzhiyun #define EModeIDTablePtrOffset     VBIOSTablePointerStart+0x04
695*4882a593Smuzhiyun #define CRT1TablePtrOffset        VBIOSTablePointerStart+0x06
696*4882a593Smuzhiyun #define ScreenOffsetPtrOffset     VBIOSTablePointerStart+0x08
697*4882a593Smuzhiyun #define VCLKDataPtrOffset         VBIOSTablePointerStart+0x0A
698*4882a593Smuzhiyun #define MCLKDataPtrOffset         VBIOSTablePointerStart+0x0E
699*4882a593Smuzhiyun #define CRT2PtrDataPtrOffset      VBIOSTablePointerStart+0x10
700*4882a593Smuzhiyun #define TVAntiFlickPtrOffset      VBIOSTablePointerStart+0x12
701*4882a593Smuzhiyun #define TVDelayPtr1Offset         VBIOSTablePointerStart+0x14
702*4882a593Smuzhiyun #define TVPhaseIncrPtr1Offset     VBIOSTablePointerStart+0x16
703*4882a593Smuzhiyun #define TVYFilterPtr1Offset       VBIOSTablePointerStart+0x18
704*4882a593Smuzhiyun #define LCDDelayPtr1Offset        VBIOSTablePointerStart+0x20
705*4882a593Smuzhiyun #define TVEdgePtr1Offset          VBIOSTablePointerStart+0x24
706*4882a593Smuzhiyun #define CRT2Delay1Offset          VBIOSTablePointerStart+0x28
707*4882a593Smuzhiyun 
708*4882a593Smuzhiyun #endif
709