1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * linux/drivers/video/savagefb.h -- S3 Savage Framebuffer Driver
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * Copyright (c) 2001 Denis Oliver Kropp <dok@convergence.de>
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * This file is subject to the terms and conditions of the GNU General
7*4882a593Smuzhiyun * Public License. See the file COPYING in the main directory of this
8*4882a593Smuzhiyun * archive for more details.
9*4882a593Smuzhiyun */
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun #ifndef __SAVAGEFB_H__
13*4882a593Smuzhiyun #define __SAVAGEFB_H__
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun #include <linux/i2c.h>
16*4882a593Smuzhiyun #include <linux/i2c-algo-bit.h>
17*4882a593Smuzhiyun #include <linux/mutex.h>
18*4882a593Smuzhiyun #include <video/vga.h>
19*4882a593Smuzhiyun #include "../edid.h"
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun #ifdef SAVAGEFB_DEBUG
22*4882a593Smuzhiyun # define DBG(x) printk (KERN_DEBUG "savagefb: %s\n", (x));
23*4882a593Smuzhiyun #else
24*4882a593Smuzhiyun # define DBG(x) no_printk(x)
25*4882a593Smuzhiyun # define SavagePrintRegs(...)
26*4882a593Smuzhiyun #endif
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun #define PCI_CHIP_SAVAGE4 0x8a22
30*4882a593Smuzhiyun #define PCI_CHIP_SAVAGE3D 0x8a20
31*4882a593Smuzhiyun #define PCI_CHIP_SAVAGE3D_MV 0x8a21
32*4882a593Smuzhiyun #define PCI_CHIP_SAVAGE2000 0x9102
33*4882a593Smuzhiyun #define PCI_CHIP_SAVAGE_MX_MV 0x8c10
34*4882a593Smuzhiyun #define PCI_CHIP_SAVAGE_MX 0x8c11
35*4882a593Smuzhiyun #define PCI_CHIP_SAVAGE_IX_MV 0x8c12
36*4882a593Smuzhiyun #define PCI_CHIP_SAVAGE_IX 0x8c13
37*4882a593Smuzhiyun #define PCI_CHIP_PROSAVAGE_PM 0x8a25
38*4882a593Smuzhiyun #define PCI_CHIP_PROSAVAGE_KM 0x8a26
39*4882a593Smuzhiyun #define PCI_CHIP_S3TWISTER_P 0x8d01
40*4882a593Smuzhiyun #define PCI_CHIP_S3TWISTER_K 0x8d02
41*4882a593Smuzhiyun #define PCI_CHIP_PROSAVAGE_DDR 0x8d03
42*4882a593Smuzhiyun #define PCI_CHIP_PROSAVAGE_DDRK 0x8d04
43*4882a593Smuzhiyun #define PCI_CHIP_SUPSAV_MX128 0x8c22
44*4882a593Smuzhiyun #define PCI_CHIP_SUPSAV_MX64 0x8c24
45*4882a593Smuzhiyun #define PCI_CHIP_SUPSAV_MX64C 0x8c26
46*4882a593Smuzhiyun #define PCI_CHIP_SUPSAV_IX128SDR 0x8c2a
47*4882a593Smuzhiyun #define PCI_CHIP_SUPSAV_IX128DDR 0x8c2b
48*4882a593Smuzhiyun #define PCI_CHIP_SUPSAV_IX64SDR 0x8c2c
49*4882a593Smuzhiyun #define PCI_CHIP_SUPSAV_IX64DDR 0x8c2d
50*4882a593Smuzhiyun #define PCI_CHIP_SUPSAV_IXCSDR 0x8c2e
51*4882a593Smuzhiyun #define PCI_CHIP_SUPSAV_IXCDDR 0x8c2f
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun #define S3_SAVAGE_SERIES(chip) ((chip>=S3_SAVAGE3D) && (chip<=S3_SAVAGE2000))
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun #define S3_SAVAGE3D_SERIES(chip) ((chip>=S3_SAVAGE3D) && (chip<=S3_SAVAGE_MX))
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun #define S3_SAVAGE4_SERIES(chip) ((chip>=S3_SAVAGE4) && (chip<=S3_PROSAVAGEDDR))
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun #define S3_SAVAGE_MOBILE_SERIES(chip) ((chip==S3_SAVAGE_MX) || (chip==S3_SUPERSAVAGE))
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun #define S3_MOBILE_TWISTER_SERIES(chip) ((chip==S3_TWISTER) || (chip==S3_PROSAVAGEDDR))
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun /* Chip tags. These are used to group the adapters into
65*4882a593Smuzhiyun * related families.
66*4882a593Smuzhiyun */
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun typedef enum {
69*4882a593Smuzhiyun S3_UNKNOWN = 0,
70*4882a593Smuzhiyun S3_SAVAGE3D,
71*4882a593Smuzhiyun S3_SAVAGE_MX,
72*4882a593Smuzhiyun S3_SAVAGE4,
73*4882a593Smuzhiyun S3_PROSAVAGE,
74*4882a593Smuzhiyun S3_TWISTER,
75*4882a593Smuzhiyun S3_PROSAVAGEDDR,
76*4882a593Smuzhiyun S3_SUPERSAVAGE,
77*4882a593Smuzhiyun S3_SAVAGE2000,
78*4882a593Smuzhiyun S3_LAST
79*4882a593Smuzhiyun } savage_chipset;
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun #define BIOS_BSIZE 1024
82*4882a593Smuzhiyun #define BIOS_BASE 0xc0000
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun #define SAVAGE_NEWMMIO_REGBASE_S3 0x1000000 /* 16MB */
85*4882a593Smuzhiyun #define SAVAGE_NEWMMIO_REGBASE_S4 0x0000000
86*4882a593Smuzhiyun #define SAVAGE_NEWMMIO_REGSIZE 0x0080000 /* 512kb */
87*4882a593Smuzhiyun #define SAVAGE_NEWMMIO_VGABASE 0x8000
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun #define BASE_FREQ 14318
90*4882a593Smuzhiyun #define HALF_BASE_FREQ 7159
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun #define FIFO_CONTROL_REG 0x8200
93*4882a593Smuzhiyun #define MIU_CONTROL_REG 0x8204
94*4882a593Smuzhiyun #define STREAMS_TIMEOUT_REG 0x8208
95*4882a593Smuzhiyun #define MISC_TIMEOUT_REG 0x820c
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun #define MONO_PAT_0 0xa4e8
98*4882a593Smuzhiyun #define MONO_PAT_1 0xa4ec
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun #define MAXFIFO 0x7f00
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun #define BCI_CMD_NOP 0x40000000
103*4882a593Smuzhiyun #define BCI_CMD_SETREG 0x96000000
104*4882a593Smuzhiyun #define BCI_CMD_RECT 0x48000000
105*4882a593Smuzhiyun #define BCI_CMD_RECT_XP 0x01000000
106*4882a593Smuzhiyun #define BCI_CMD_RECT_YP 0x02000000
107*4882a593Smuzhiyun #define BCI_CMD_SEND_COLOR 0x00008000
108*4882a593Smuzhiyun #define BCI_CMD_DEST_GBD 0x00000000
109*4882a593Smuzhiyun #define BCI_CMD_SRC_GBD 0x00000020
110*4882a593Smuzhiyun #define BCI_CMD_SRC_SOLID 0x00000000
111*4882a593Smuzhiyun #define BCI_CMD_SRC_MONO 0x00000060
112*4882a593Smuzhiyun #define BCI_CMD_CLIP_NEW 0x00006000
113*4882a593Smuzhiyun #define BCI_CMD_CLIP_LR 0x00004000
114*4882a593Smuzhiyun
115*4882a593Smuzhiyun #define BCI_CLIP_LR(l, r) ((((r) << 16) | (l)) & 0x0FFF0FFF)
116*4882a593Smuzhiyun #define BCI_CLIP_TL(t, l) ((((t) << 16) | (l)) & 0x0FFF0FFF)
117*4882a593Smuzhiyun #define BCI_CLIP_BR(b, r) ((((b) << 16) | (r)) & 0x0FFF0FFF)
118*4882a593Smuzhiyun #define BCI_W_H(w, h) (((h) << 16) | ((w) & 0xFFF))
119*4882a593Smuzhiyun #define BCI_X_Y(x, y) (((y) << 16) | ((x) & 0xFFF))
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun #define BCI_GBD1 0xE0
122*4882a593Smuzhiyun #define BCI_GBD2 0xE1
123*4882a593Smuzhiyun
124*4882a593Smuzhiyun #define BCI_BUFFER_OFFSET 0x10000
125*4882a593Smuzhiyun #define BCI_SIZE 0x4000
126*4882a593Smuzhiyun
127*4882a593Smuzhiyun #define BCI_SEND(dw) writel(dw, par->bci_base + par->bci_ptr++)
128*4882a593Smuzhiyun
129*4882a593Smuzhiyun #define BCI_CMD_GET_ROP(cmd) (((cmd) >> 16) & 0xFF)
130*4882a593Smuzhiyun #define BCI_CMD_SET_ROP(cmd, rop) ((cmd) |= ((rop & 0xFF) << 16))
131*4882a593Smuzhiyun #define BCI_CMD_SEND_COLOR 0x00008000
132*4882a593Smuzhiyun
133*4882a593Smuzhiyun #define DISP_CRT 1
134*4882a593Smuzhiyun #define DISP_LCD 2
135*4882a593Smuzhiyun #define DISP_DFP 3
136*4882a593Smuzhiyun
137*4882a593Smuzhiyun struct xtimings {
138*4882a593Smuzhiyun unsigned int Clock;
139*4882a593Smuzhiyun unsigned int HDisplay;
140*4882a593Smuzhiyun unsigned int HSyncStart;
141*4882a593Smuzhiyun unsigned int HSyncEnd;
142*4882a593Smuzhiyun unsigned int HTotal;
143*4882a593Smuzhiyun unsigned int HAdjusted;
144*4882a593Smuzhiyun unsigned int VDisplay;
145*4882a593Smuzhiyun unsigned int VSyncStart;
146*4882a593Smuzhiyun unsigned int VSyncEnd;
147*4882a593Smuzhiyun unsigned int VTotal;
148*4882a593Smuzhiyun unsigned int sync;
149*4882a593Smuzhiyun int dblscan;
150*4882a593Smuzhiyun int interlaced;
151*4882a593Smuzhiyun };
152*4882a593Smuzhiyun
153*4882a593Smuzhiyun struct savage_reg {
154*4882a593Smuzhiyun unsigned char MiscOutReg; /* Misc */
155*4882a593Smuzhiyun unsigned char CRTC[25]; /* Crtc Controller */
156*4882a593Smuzhiyun unsigned char Sequencer[5]; /* Video Sequencer */
157*4882a593Smuzhiyun unsigned char Graphics[9]; /* Video Graphics */
158*4882a593Smuzhiyun unsigned char Attribute[21]; /* Video Attribute */
159*4882a593Smuzhiyun
160*4882a593Smuzhiyun unsigned int mode, refresh;
161*4882a593Smuzhiyun unsigned char SR08, SR0E, SR0F;
162*4882a593Smuzhiyun unsigned char SR10, SR11, SR12, SR13, SR15, SR18, SR29, SR30;
163*4882a593Smuzhiyun unsigned char SR54[8];
164*4882a593Smuzhiyun unsigned char Clock;
165*4882a593Smuzhiyun unsigned char CR31, CR32, CR33, CR34, CR36, CR3A, CR3B, CR3C;
166*4882a593Smuzhiyun unsigned char CR40, CR41, CR42, CR43, CR45;
167*4882a593Smuzhiyun unsigned char CR50, CR51, CR53, CR55, CR58, CR5B, CR5D, CR5E;
168*4882a593Smuzhiyun unsigned char CR60, CR63, CR65, CR66, CR67, CR68, CR69, CR6D, CR6F;
169*4882a593Smuzhiyun unsigned char CR86, CR88;
170*4882a593Smuzhiyun unsigned char CR90, CR91, CRB0;
171*4882a593Smuzhiyun unsigned int STREAMS[22]; /* yuck, streams regs */
172*4882a593Smuzhiyun unsigned int MMPR0, MMPR1, MMPR2, MMPR3;
173*4882a593Smuzhiyun };
174*4882a593Smuzhiyun /* --------------------------------------------------------------------- */
175*4882a593Smuzhiyun
176*4882a593Smuzhiyun #define NR_PALETTE 256
177*4882a593Smuzhiyun
178*4882a593Smuzhiyun
179*4882a593Smuzhiyun struct savagefb_par;
180*4882a593Smuzhiyun
181*4882a593Smuzhiyun struct savagefb_i2c_chan {
182*4882a593Smuzhiyun struct savagefb_par *par;
183*4882a593Smuzhiyun struct i2c_adapter adapter;
184*4882a593Smuzhiyun struct i2c_algo_bit_data algo;
185*4882a593Smuzhiyun volatile u8 __iomem *ioaddr;
186*4882a593Smuzhiyun u32 reg;
187*4882a593Smuzhiyun };
188*4882a593Smuzhiyun
189*4882a593Smuzhiyun struct savagefb_par {
190*4882a593Smuzhiyun struct pci_dev *pcidev;
191*4882a593Smuzhiyun savage_chipset chip;
192*4882a593Smuzhiyun struct savagefb_i2c_chan chan;
193*4882a593Smuzhiyun struct savage_reg state;
194*4882a593Smuzhiyun struct savage_reg save;
195*4882a593Smuzhiyun struct savage_reg initial;
196*4882a593Smuzhiyun struct vgastate vgastate;
197*4882a593Smuzhiyun struct mutex open_lock;
198*4882a593Smuzhiyun unsigned char *edid;
199*4882a593Smuzhiyun u32 pseudo_palette[16];
200*4882a593Smuzhiyun u32 open_count;
201*4882a593Smuzhiyun int paletteEnabled;
202*4882a593Smuzhiyun int pm_state;
203*4882a593Smuzhiyun int display_type;
204*4882a593Smuzhiyun int dvi;
205*4882a593Smuzhiyun int crtonly;
206*4882a593Smuzhiyun int dacSpeedBpp;
207*4882a593Smuzhiyun int maxClock;
208*4882a593Smuzhiyun int minClock;
209*4882a593Smuzhiyun int numClocks;
210*4882a593Smuzhiyun int clock[4];
211*4882a593Smuzhiyun int MCLK, REFCLK, LCDclk;
212*4882a593Smuzhiyun struct {
213*4882a593Smuzhiyun void __iomem *vbase;
214*4882a593Smuzhiyun u32 pbase;
215*4882a593Smuzhiyun u32 len;
216*4882a593Smuzhiyun int wc_cookie;
217*4882a593Smuzhiyun } video;
218*4882a593Smuzhiyun
219*4882a593Smuzhiyun struct {
220*4882a593Smuzhiyun void __iomem *vbase;
221*4882a593Smuzhiyun u32 pbase;
222*4882a593Smuzhiyun u32 len;
223*4882a593Smuzhiyun } mmio;
224*4882a593Smuzhiyun
225*4882a593Smuzhiyun volatile u32 __iomem *bci_base;
226*4882a593Smuzhiyun unsigned int bci_ptr;
227*4882a593Smuzhiyun u32 cob_offset;
228*4882a593Smuzhiyun u32 cob_size;
229*4882a593Smuzhiyun int cob_index;
230*4882a593Smuzhiyun
231*4882a593Smuzhiyun void (*SavageWaitIdle) (struct savagefb_par *par);
232*4882a593Smuzhiyun void (*SavageWaitFifo) (struct savagefb_par *par, int space);
233*4882a593Smuzhiyun
234*4882a593Smuzhiyun int HorizScaleFactor;
235*4882a593Smuzhiyun
236*4882a593Smuzhiyun /* Panels size */
237*4882a593Smuzhiyun int SavagePanelWidth;
238*4882a593Smuzhiyun int SavagePanelHeight;
239*4882a593Smuzhiyun
240*4882a593Smuzhiyun struct {
241*4882a593Smuzhiyun u16 red, green, blue, transp;
242*4882a593Smuzhiyun } palette[NR_PALETTE];
243*4882a593Smuzhiyun
244*4882a593Smuzhiyun int depth;
245*4882a593Smuzhiyun int vwidth;
246*4882a593Smuzhiyun };
247*4882a593Smuzhiyun
248*4882a593Smuzhiyun #define BCI_BD_BW_DISABLE 0x10000000
249*4882a593Smuzhiyun #define BCI_BD_SET_BPP(bd, bpp) ((bd) |= (((bpp) & 0xFF) << 16))
250*4882a593Smuzhiyun #define BCI_BD_SET_STRIDE(bd, st) ((bd) |= ((st) & 0xFFFF))
251*4882a593Smuzhiyun
252*4882a593Smuzhiyun
253*4882a593Smuzhiyun /* IO functions */
savage_in8(u32 addr,struct savagefb_par * par)254*4882a593Smuzhiyun static inline u8 savage_in8(u32 addr, struct savagefb_par *par)
255*4882a593Smuzhiyun {
256*4882a593Smuzhiyun return readb(par->mmio.vbase + addr);
257*4882a593Smuzhiyun }
258*4882a593Smuzhiyun
savage_in16(u32 addr,struct savagefb_par * par)259*4882a593Smuzhiyun static inline u16 savage_in16(u32 addr, struct savagefb_par *par)
260*4882a593Smuzhiyun {
261*4882a593Smuzhiyun return readw(par->mmio.vbase + addr);
262*4882a593Smuzhiyun }
263*4882a593Smuzhiyun
savage_in32(u32 addr,struct savagefb_par * par)264*4882a593Smuzhiyun static inline u32 savage_in32(u32 addr, struct savagefb_par *par)
265*4882a593Smuzhiyun {
266*4882a593Smuzhiyun return readl(par->mmio.vbase + addr);
267*4882a593Smuzhiyun }
268*4882a593Smuzhiyun
savage_out8(u32 addr,u8 val,struct savagefb_par * par)269*4882a593Smuzhiyun static inline void savage_out8(u32 addr, u8 val, struct savagefb_par *par)
270*4882a593Smuzhiyun {
271*4882a593Smuzhiyun writeb(val, par->mmio.vbase + addr);
272*4882a593Smuzhiyun }
273*4882a593Smuzhiyun
savage_out16(u32 addr,u16 val,struct savagefb_par * par)274*4882a593Smuzhiyun static inline void savage_out16(u32 addr, u16 val, struct savagefb_par *par)
275*4882a593Smuzhiyun {
276*4882a593Smuzhiyun writew(val, par->mmio.vbase + addr);
277*4882a593Smuzhiyun }
278*4882a593Smuzhiyun
savage_out32(u32 addr,u32 val,struct savagefb_par * par)279*4882a593Smuzhiyun static inline void savage_out32(u32 addr, u32 val, struct savagefb_par *par)
280*4882a593Smuzhiyun {
281*4882a593Smuzhiyun writel(val, par->mmio.vbase + addr);
282*4882a593Smuzhiyun }
283*4882a593Smuzhiyun
vga_in8(int addr,struct savagefb_par * par)284*4882a593Smuzhiyun static inline u8 vga_in8(int addr, struct savagefb_par *par)
285*4882a593Smuzhiyun {
286*4882a593Smuzhiyun return savage_in8(0x8000 + addr, par);
287*4882a593Smuzhiyun }
288*4882a593Smuzhiyun
vga_in16(int addr,struct savagefb_par * par)289*4882a593Smuzhiyun static inline u16 vga_in16(int addr, struct savagefb_par *par)
290*4882a593Smuzhiyun {
291*4882a593Smuzhiyun return savage_in16(0x8000 + addr, par);
292*4882a593Smuzhiyun }
293*4882a593Smuzhiyun
vga_in32(int addr,struct savagefb_par * par)294*4882a593Smuzhiyun static inline u8 vga_in32(int addr, struct savagefb_par *par)
295*4882a593Smuzhiyun {
296*4882a593Smuzhiyun return savage_in32(0x8000 + addr, par);
297*4882a593Smuzhiyun }
298*4882a593Smuzhiyun
vga_out8(int addr,u8 val,struct savagefb_par * par)299*4882a593Smuzhiyun static inline void vga_out8(int addr, u8 val, struct savagefb_par *par)
300*4882a593Smuzhiyun {
301*4882a593Smuzhiyun savage_out8(0x8000 + addr, val, par);
302*4882a593Smuzhiyun }
303*4882a593Smuzhiyun
vga_out16(int addr,u16 val,struct savagefb_par * par)304*4882a593Smuzhiyun static inline void vga_out16(int addr, u16 val, struct savagefb_par *par)
305*4882a593Smuzhiyun {
306*4882a593Smuzhiyun savage_out16(0x8000 + addr, val, par);
307*4882a593Smuzhiyun }
308*4882a593Smuzhiyun
vga_out32(int addr,u32 val,struct savagefb_par * par)309*4882a593Smuzhiyun static inline void vga_out32(int addr, u32 val, struct savagefb_par *par)
310*4882a593Smuzhiyun {
311*4882a593Smuzhiyun savage_out32(0x8000 + addr, val, par);
312*4882a593Smuzhiyun }
313*4882a593Smuzhiyun
VGArCR(u8 index,struct savagefb_par * par)314*4882a593Smuzhiyun static inline u8 VGArCR (u8 index, struct savagefb_par *par)
315*4882a593Smuzhiyun {
316*4882a593Smuzhiyun vga_out8(0x3d4, index, par);
317*4882a593Smuzhiyun return vga_in8(0x3d5, par);
318*4882a593Smuzhiyun }
319*4882a593Smuzhiyun
VGArGR(u8 index,struct savagefb_par * par)320*4882a593Smuzhiyun static inline u8 VGArGR (u8 index, struct savagefb_par *par)
321*4882a593Smuzhiyun {
322*4882a593Smuzhiyun vga_out8(0x3ce, index, par);
323*4882a593Smuzhiyun return vga_in8(0x3cf, par);
324*4882a593Smuzhiyun }
325*4882a593Smuzhiyun
VGArSEQ(u8 index,struct savagefb_par * par)326*4882a593Smuzhiyun static inline u8 VGArSEQ (u8 index, struct savagefb_par *par)
327*4882a593Smuzhiyun {
328*4882a593Smuzhiyun vga_out8(0x3c4, index, par);
329*4882a593Smuzhiyun return vga_in8(0x3c5, par);
330*4882a593Smuzhiyun }
331*4882a593Smuzhiyun
VGAwCR(u8 index,u8 val,struct savagefb_par * par)332*4882a593Smuzhiyun static inline void VGAwCR(u8 index, u8 val, struct savagefb_par *par)
333*4882a593Smuzhiyun {
334*4882a593Smuzhiyun vga_out8(0x3d4, index, par);
335*4882a593Smuzhiyun vga_out8(0x3d5, val, par);
336*4882a593Smuzhiyun }
337*4882a593Smuzhiyun
VGAwGR(u8 index,u8 val,struct savagefb_par * par)338*4882a593Smuzhiyun static inline void VGAwGR(u8 index, u8 val, struct savagefb_par *par)
339*4882a593Smuzhiyun {
340*4882a593Smuzhiyun vga_out8(0x3ce, index, par);
341*4882a593Smuzhiyun vga_out8(0x3cf, val, par);
342*4882a593Smuzhiyun }
343*4882a593Smuzhiyun
VGAwSEQ(u8 index,u8 val,struct savagefb_par * par)344*4882a593Smuzhiyun static inline void VGAwSEQ(u8 index, u8 val, struct savagefb_par *par)
345*4882a593Smuzhiyun {
346*4882a593Smuzhiyun vga_out8(0x3c4, index, par);
347*4882a593Smuzhiyun vga_out8 (0x3c5, val, par);
348*4882a593Smuzhiyun }
349*4882a593Smuzhiyun
VGAenablePalette(struct savagefb_par * par)350*4882a593Smuzhiyun static inline void VGAenablePalette(struct savagefb_par *par)
351*4882a593Smuzhiyun {
352*4882a593Smuzhiyun vga_in8(0x3da, par);
353*4882a593Smuzhiyun vga_out8(0x3c0, 0x00, par);
354*4882a593Smuzhiyun par->paletteEnabled = 1;
355*4882a593Smuzhiyun }
356*4882a593Smuzhiyun
VGAdisablePalette(struct savagefb_par * par)357*4882a593Smuzhiyun static inline void VGAdisablePalette(struct savagefb_par *par)
358*4882a593Smuzhiyun {
359*4882a593Smuzhiyun vga_in8(0x3da, par);
360*4882a593Smuzhiyun vga_out8(0x3c0, 0x20, par);
361*4882a593Smuzhiyun par->paletteEnabled = 0;
362*4882a593Smuzhiyun }
363*4882a593Smuzhiyun
VGAwATTR(u8 index,u8 value,struct savagefb_par * par)364*4882a593Smuzhiyun static inline void VGAwATTR(u8 index, u8 value, struct savagefb_par *par)
365*4882a593Smuzhiyun {
366*4882a593Smuzhiyun if (par->paletteEnabled)
367*4882a593Smuzhiyun index &= ~0x20;
368*4882a593Smuzhiyun else
369*4882a593Smuzhiyun index |= 0x20;
370*4882a593Smuzhiyun
371*4882a593Smuzhiyun vga_in8(0x3da, par);
372*4882a593Smuzhiyun vga_out8(0x3c0, index, par);
373*4882a593Smuzhiyun vga_out8 (0x3c0, value, par);
374*4882a593Smuzhiyun }
375*4882a593Smuzhiyun
VGAwMISC(u8 value,struct savagefb_par * par)376*4882a593Smuzhiyun static inline void VGAwMISC(u8 value, struct savagefb_par *par)
377*4882a593Smuzhiyun {
378*4882a593Smuzhiyun vga_out8(0x3c2, value, par);
379*4882a593Smuzhiyun }
380*4882a593Smuzhiyun
381*4882a593Smuzhiyun #ifndef CONFIG_FB_SAVAGE_ACCEL
382*4882a593Smuzhiyun #define savagefb_set_clip(x)
383*4882a593Smuzhiyun #endif
384*4882a593Smuzhiyun
VerticalRetraceWait(struct savagefb_par * par)385*4882a593Smuzhiyun static inline void VerticalRetraceWait(struct savagefb_par *par)
386*4882a593Smuzhiyun {
387*4882a593Smuzhiyun vga_out8(0x3d4, 0x17, par);
388*4882a593Smuzhiyun if (vga_in8(0x3d5, par) & 0x80) {
389*4882a593Smuzhiyun while ((vga_in8(0x3da, par) & 0x08) == 0x08);
390*4882a593Smuzhiyun while ((vga_in8(0x3da, par) & 0x08) == 0x00);
391*4882a593Smuzhiyun }
392*4882a593Smuzhiyun }
393*4882a593Smuzhiyun
394*4882a593Smuzhiyun extern int savagefb_probe_i2c_connector(struct fb_info *info,
395*4882a593Smuzhiyun u8 **out_edid);
396*4882a593Smuzhiyun extern void savagefb_create_i2c_busses(struct fb_info *info);
397*4882a593Smuzhiyun extern void savagefb_delete_i2c_busses(struct fb_info *info);
398*4882a593Smuzhiyun extern int savagefb_sync(struct fb_info *info);
399*4882a593Smuzhiyun extern void savagefb_copyarea(struct fb_info *info,
400*4882a593Smuzhiyun const struct fb_copyarea *region);
401*4882a593Smuzhiyun extern void savagefb_fillrect(struct fb_info *info,
402*4882a593Smuzhiyun const struct fb_fillrect *rect);
403*4882a593Smuzhiyun extern void savagefb_imageblit(struct fb_info *info,
404*4882a593Smuzhiyun const struct fb_image *image);
405*4882a593Smuzhiyun
406*4882a593Smuzhiyun
407*4882a593Smuzhiyun #endif /* __SAVAGEFB_H__ */
408