1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * linux/drivers/video/sa1100fb.h 3*4882a593Smuzhiyun * -- StrongARM 1100 LCD Controller Frame Buffer Device 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 1999 Eric A. Thomas 6*4882a593Smuzhiyun * Based on acornfb.c Copyright (C) Russell King. 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * This file is subject to the terms and conditions of the GNU General Public 9*4882a593Smuzhiyun * License. See the file COPYING in the main directory of this archive 10*4882a593Smuzhiyun * for more details. 11*4882a593Smuzhiyun */ 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun struct gpio_desc; 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #define LCCR0 0x0000 /* LCD Control Reg. 0 */ 16*4882a593Smuzhiyun #define LCSR 0x0004 /* LCD Status Reg. */ 17*4882a593Smuzhiyun #define DBAR1 0x0010 /* LCD DMA Base Address Reg. channel 1 */ 18*4882a593Smuzhiyun #define DCAR1 0x0014 /* LCD DMA Current Address Reg. channel 1 */ 19*4882a593Smuzhiyun #define DBAR2 0x0018 /* LCD DMA Base Address Reg. channel 2 */ 20*4882a593Smuzhiyun #define DCAR2 0x001C /* LCD DMA Current Address Reg. channel 2 */ 21*4882a593Smuzhiyun #define LCCR1 0x0020 /* LCD Control Reg. 1 */ 22*4882a593Smuzhiyun #define LCCR2 0x0024 /* LCD Control Reg. 2 */ 23*4882a593Smuzhiyun #define LCCR3 0x0028 /* LCD Control Reg. 3 */ 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun /* Shadows for LCD controller registers */ 26*4882a593Smuzhiyun struct sa1100fb_lcd_reg { 27*4882a593Smuzhiyun unsigned long lccr0; 28*4882a593Smuzhiyun unsigned long lccr1; 29*4882a593Smuzhiyun unsigned long lccr2; 30*4882a593Smuzhiyun unsigned long lccr3; 31*4882a593Smuzhiyun }; 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun struct sa1100fb_info { 34*4882a593Smuzhiyun struct fb_info fb; 35*4882a593Smuzhiyun struct device *dev; 36*4882a593Smuzhiyun const struct sa1100fb_rgb *rgb[NR_RGB]; 37*4882a593Smuzhiyun void __iomem *base; 38*4882a593Smuzhiyun struct gpio_desc *shannon_lcden; 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun /* 41*4882a593Smuzhiyun * These are the addresses we mapped 42*4882a593Smuzhiyun * the framebuffer memory region to. 43*4882a593Smuzhiyun */ 44*4882a593Smuzhiyun dma_addr_t map_dma; 45*4882a593Smuzhiyun u_char * map_cpu; 46*4882a593Smuzhiyun u_int map_size; 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun u_char * screen_cpu; 49*4882a593Smuzhiyun dma_addr_t screen_dma; 50*4882a593Smuzhiyun u16 * palette_cpu; 51*4882a593Smuzhiyun dma_addr_t palette_dma; 52*4882a593Smuzhiyun u_int palette_size; 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun dma_addr_t dbar1; 55*4882a593Smuzhiyun dma_addr_t dbar2; 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun u_int reg_lccr0; 58*4882a593Smuzhiyun u_int reg_lccr1; 59*4882a593Smuzhiyun u_int reg_lccr2; 60*4882a593Smuzhiyun u_int reg_lccr3; 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun volatile u_char state; 63*4882a593Smuzhiyun volatile u_char task_state; 64*4882a593Smuzhiyun struct mutex ctrlr_lock; 65*4882a593Smuzhiyun wait_queue_head_t ctrlr_wait; 66*4882a593Smuzhiyun struct work_struct task; 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun #ifdef CONFIG_CPU_FREQ 69*4882a593Smuzhiyun struct notifier_block freq_transition; 70*4882a593Smuzhiyun #endif 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun const struct sa1100fb_mach_info *inf; 73*4882a593Smuzhiyun struct clk *clk; 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun u32 pseudo_palette[16]; 76*4882a593Smuzhiyun }; 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun #define TO_INF(ptr,member) container_of(ptr,struct sa1100fb_info,member) 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun #define SA1100_PALETTE_MODE_VAL(bpp) (((bpp) & 0x018) << 9) 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun /* 83*4882a593Smuzhiyun * These are the actions for set_ctrlr_state 84*4882a593Smuzhiyun */ 85*4882a593Smuzhiyun #define C_DISABLE (0) 86*4882a593Smuzhiyun #define C_ENABLE (1) 87*4882a593Smuzhiyun #define C_DISABLE_CLKCHANGE (2) 88*4882a593Smuzhiyun #define C_ENABLE_CLKCHANGE (3) 89*4882a593Smuzhiyun #define C_REENABLE (4) 90*4882a593Smuzhiyun #define C_DISABLE_PM (5) 91*4882a593Smuzhiyun #define C_ENABLE_PM (6) 92*4882a593Smuzhiyun #define C_STARTUP (7) 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun #define SA1100_NAME "SA1100" 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun /* 97*4882a593Smuzhiyun * Minimum X and Y resolutions 98*4882a593Smuzhiyun */ 99*4882a593Smuzhiyun #define MIN_XRES 64 100*4882a593Smuzhiyun #define MIN_YRES 64 101*4882a593Smuzhiyun 102