1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk> 4*4882a593Smuzhiyun * http://www.simtec.co.uk/products/SWLINUX/ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef ___ASM_ARCH_REGS_LCD_H 8*4882a593Smuzhiyun #define ___ASM_ARCH_REGS_LCD_H 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun /* 11*4882a593Smuzhiyun * a couple of values are used as platform data in 12*4882a593Smuzhiyun * include/linux/platform_data/fb-s3c2410.h and not 13*4882a593Smuzhiyun * duplicated here. 14*4882a593Smuzhiyun */ 15*4882a593Smuzhiyun #include <linux/platform_data/fb-s3c2410.h> 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun #define S3C2410_LCDREG(x) (x) 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun /* LCD control registers */ 20*4882a593Smuzhiyun #define S3C2410_LCDCON1 S3C2410_LCDREG(0x00) 21*4882a593Smuzhiyun #define S3C2410_LCDCON2 S3C2410_LCDREG(0x04) 22*4882a593Smuzhiyun #define S3C2410_LCDCON3 S3C2410_LCDREG(0x08) 23*4882a593Smuzhiyun #define S3C2410_LCDCON4 S3C2410_LCDREG(0x0C) 24*4882a593Smuzhiyun #define S3C2410_LCDCON5 S3C2410_LCDREG(0x10) 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun #define S3C2410_LCDCON1_CLKVAL(x) ((x) << 8) 27*4882a593Smuzhiyun #define S3C2410_LCDCON1_MMODE (1<<7) 28*4882a593Smuzhiyun #define S3C2410_LCDCON1_DSCAN4 (0<<5) 29*4882a593Smuzhiyun #define S3C2410_LCDCON1_STN4 (1<<5) 30*4882a593Smuzhiyun #define S3C2410_LCDCON1_STN8 (2<<5) 31*4882a593Smuzhiyun #define S3C2410_LCDCON1_TFT (3<<5) 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun #define S3C2410_LCDCON1_STN1BPP (0<<1) 34*4882a593Smuzhiyun #define S3C2410_LCDCON1_STN2GREY (1<<1) 35*4882a593Smuzhiyun #define S3C2410_LCDCON1_STN4GREY (2<<1) 36*4882a593Smuzhiyun #define S3C2410_LCDCON1_STN8BPP (3<<1) 37*4882a593Smuzhiyun #define S3C2410_LCDCON1_STN12BPP (4<<1) 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun #define S3C2410_LCDCON1_ENVID (1) 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun #define S3C2410_LCDCON1_MODEMASK 0x1E 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun #define S3C2410_LCDCON2_VBPD(x) ((x) << 24) 44*4882a593Smuzhiyun #define S3C2410_LCDCON2_LINEVAL(x) ((x) << 14) 45*4882a593Smuzhiyun #define S3C2410_LCDCON2_VFPD(x) ((x) << 6) 46*4882a593Smuzhiyun #define S3C2410_LCDCON2_VSPW(x) ((x) << 0) 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun #define S3C2410_LCDCON2_GET_VBPD(x) ( ((x) >> 24) & 0xFF) 49*4882a593Smuzhiyun #define S3C2410_LCDCON2_GET_VFPD(x) ( ((x) >> 6) & 0xFF) 50*4882a593Smuzhiyun #define S3C2410_LCDCON2_GET_VSPW(x) ( ((x) >> 0) & 0x3F) 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun #define S3C2410_LCDCON3_HBPD(x) ((x) << 19) 53*4882a593Smuzhiyun #define S3C2410_LCDCON3_WDLY(x) ((x) << 19) 54*4882a593Smuzhiyun #define S3C2410_LCDCON3_HOZVAL(x) ((x) << 8) 55*4882a593Smuzhiyun #define S3C2410_LCDCON3_HFPD(x) ((x) << 0) 56*4882a593Smuzhiyun #define S3C2410_LCDCON3_LINEBLANK(x)((x) << 0) 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun #define S3C2410_LCDCON3_GET_HBPD(x) ( ((x) >> 19) & 0x7F) 59*4882a593Smuzhiyun #define S3C2410_LCDCON3_GET_HFPD(x) ( ((x) >> 0) & 0xFF) 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun /* LDCCON4 changes for STN mode on the S3C2412 */ 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun #define S3C2410_LCDCON4_MVAL(x) ((x) << 8) 64*4882a593Smuzhiyun #define S3C2410_LCDCON4_HSPW(x) ((x) << 0) 65*4882a593Smuzhiyun #define S3C2410_LCDCON4_WLH(x) ((x) << 0) 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun #define S3C2410_LCDCON4_GET_HSPW(x) ( ((x) >> 0) & 0xFF) 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun /* framebuffer start addressed */ 70*4882a593Smuzhiyun #define S3C2410_LCDSADDR1 S3C2410_LCDREG(0x14) 71*4882a593Smuzhiyun #define S3C2410_LCDSADDR2 S3C2410_LCDREG(0x18) 72*4882a593Smuzhiyun #define S3C2410_LCDSADDR3 S3C2410_LCDREG(0x1C) 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun #define S3C2410_LCDBANK(x) ((x) << 21) 75*4882a593Smuzhiyun #define S3C2410_LCDBASEU(x) (x) 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun #define S3C2410_OFFSIZE(x) ((x) << 11) 78*4882a593Smuzhiyun #define S3C2410_PAGEWIDTH(x) (x) 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun /* colour lookup and miscellaneous controls */ 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun #define S3C2410_REDLUT S3C2410_LCDREG(0x20) 83*4882a593Smuzhiyun #define S3C2410_GREENLUT S3C2410_LCDREG(0x24) 84*4882a593Smuzhiyun #define S3C2410_BLUELUT S3C2410_LCDREG(0x28) 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun #define S3C2410_DITHMODE S3C2410_LCDREG(0x4C) 87*4882a593Smuzhiyun #define S3C2410_TPAL S3C2410_LCDREG(0x50) 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun #define S3C2410_TPAL_EN (1<<24) 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun /* interrupt info */ 92*4882a593Smuzhiyun #define S3C2410_LCDINTPND S3C2410_LCDREG(0x54) 93*4882a593Smuzhiyun #define S3C2410_LCDSRCPND S3C2410_LCDREG(0x58) 94*4882a593Smuzhiyun #define S3C2410_LCDINTMSK S3C2410_LCDREG(0x5C) 95*4882a593Smuzhiyun #define S3C2410_LCDINT_FIWSEL (1<<2) 96*4882a593Smuzhiyun #define S3C2410_LCDINT_FRSYNC (1<<1) 97*4882a593Smuzhiyun #define S3C2410_LCDINT_FICNT (1<<0) 98*4882a593Smuzhiyun 99*4882a593Smuzhiyun /* s3c2442 extra stn registers */ 100*4882a593Smuzhiyun 101*4882a593Smuzhiyun #define S3C2442_REDLUT S3C2410_LCDREG(0x20) 102*4882a593Smuzhiyun #define S3C2442_GREENLUT S3C2410_LCDREG(0x24) 103*4882a593Smuzhiyun #define S3C2442_BLUELUT S3C2410_LCDREG(0x28) 104*4882a593Smuzhiyun #define S3C2442_DITHMODE S3C2410_LCDREG(0x20) 105*4882a593Smuzhiyun 106*4882a593Smuzhiyun #define S3C2410_LPCSEL S3C2410_LCDREG(0x60) 107*4882a593Smuzhiyun 108*4882a593Smuzhiyun #define S3C2410_TFTPAL(x) S3C2410_LCDREG((0x400 + (x)*4)) 109*4882a593Smuzhiyun 110*4882a593Smuzhiyun /* S3C2412 registers */ 111*4882a593Smuzhiyun 112*4882a593Smuzhiyun #define S3C2412_TPAL S3C2410_LCDREG(0x20) 113*4882a593Smuzhiyun 114*4882a593Smuzhiyun #define S3C2412_LCDINTPND S3C2410_LCDREG(0x24) 115*4882a593Smuzhiyun #define S3C2412_LCDSRCPND S3C2410_LCDREG(0x28) 116*4882a593Smuzhiyun #define S3C2412_LCDINTMSK S3C2410_LCDREG(0x2C) 117*4882a593Smuzhiyun 118*4882a593Smuzhiyun #define S3C2412_TCONSEL S3C2410_LCDREG(0x30) 119*4882a593Smuzhiyun 120*4882a593Smuzhiyun #define S3C2412_LCDCON6 S3C2410_LCDREG(0x34) 121*4882a593Smuzhiyun #define S3C2412_LCDCON7 S3C2410_LCDREG(0x38) 122*4882a593Smuzhiyun #define S3C2412_LCDCON8 S3C2410_LCDREG(0x3C) 123*4882a593Smuzhiyun #define S3C2412_LCDCON9 S3C2410_LCDREG(0x40) 124*4882a593Smuzhiyun 125*4882a593Smuzhiyun #define S3C2412_REDLUT(x) S3C2410_LCDREG(0x44 + ((x)*4)) 126*4882a593Smuzhiyun #define S3C2412_GREENLUT(x) S3C2410_LCDREG(0x60 + ((x)*4)) 127*4882a593Smuzhiyun #define S3C2412_BLUELUT(x) S3C2410_LCDREG(0x98 + ((x)*4)) 128*4882a593Smuzhiyun 129*4882a593Smuzhiyun #define S3C2412_FRCPAT(x) S3C2410_LCDREG(0xB4 + ((x)*4)) 130*4882a593Smuzhiyun 131*4882a593Smuzhiyun /* general registers */ 132*4882a593Smuzhiyun 133*4882a593Smuzhiyun /* base of the LCD registers, where INTPND, INTSRC and then INTMSK 134*4882a593Smuzhiyun * are available. */ 135*4882a593Smuzhiyun 136*4882a593Smuzhiyun #define S3C2410_LCDINTBASE S3C2410_LCDREG(0x54) 137*4882a593Smuzhiyun #define S3C2412_LCDINTBASE S3C2410_LCDREG(0x24) 138*4882a593Smuzhiyun 139*4882a593Smuzhiyun #define S3C24XX_LCDINTPND (0x00) 140*4882a593Smuzhiyun #define S3C24XX_LCDSRCPND (0x04) 141*4882a593Smuzhiyun #define S3C24XX_LCDINTMSK (0x08) 142*4882a593Smuzhiyun 143*4882a593Smuzhiyun #endif /* ___ASM_ARCH_REGS_LCD_H */ 144