1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun #ifndef __RIVAFB_H 3*4882a593Smuzhiyun #define __RIVAFB_H 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun #include <linux/fb.h> 6*4882a593Smuzhiyun #include <video/vga.h> 7*4882a593Smuzhiyun #include <linux/i2c.h> 8*4882a593Smuzhiyun #include <linux/i2c-algo-bit.h> 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #include "riva_hw.h" 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun /* GGI compatibility macros */ 13*4882a593Smuzhiyun #define NUM_SEQ_REGS 0x05 14*4882a593Smuzhiyun #define NUM_CRT_REGS 0x41 15*4882a593Smuzhiyun #define NUM_GRC_REGS 0x09 16*4882a593Smuzhiyun #define NUM_ATC_REGS 0x15 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun /* I2C */ 19*4882a593Smuzhiyun #define DDC_SCL_READ_MASK (1 << 2) 20*4882a593Smuzhiyun #define DDC_SCL_WRITE_MASK (1 << 5) 21*4882a593Smuzhiyun #define DDC_SDA_READ_MASK (1 << 3) 22*4882a593Smuzhiyun #define DDC_SDA_WRITE_MASK (1 << 4) 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun /* holds the state of the VGA core and extended Riva hw state from riva_hw.c. 25*4882a593Smuzhiyun * From KGI originally. */ 26*4882a593Smuzhiyun struct riva_regs { 27*4882a593Smuzhiyun u8 attr[NUM_ATC_REGS]; 28*4882a593Smuzhiyun u8 crtc[NUM_CRT_REGS]; 29*4882a593Smuzhiyun u8 gra[NUM_GRC_REGS]; 30*4882a593Smuzhiyun u8 seq[NUM_SEQ_REGS]; 31*4882a593Smuzhiyun u8 misc_output; 32*4882a593Smuzhiyun RIVA_HW_STATE ext; 33*4882a593Smuzhiyun }; 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun struct riva_par; 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun struct riva_i2c_chan { 38*4882a593Smuzhiyun struct riva_par *par; 39*4882a593Smuzhiyun unsigned long ddc_base; 40*4882a593Smuzhiyun struct i2c_adapter adapter; 41*4882a593Smuzhiyun struct i2c_algo_bit_data algo; 42*4882a593Smuzhiyun }; 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun struct riva_par { 45*4882a593Smuzhiyun RIVA_HW_INST riva; /* interface to riva_hw.c */ 46*4882a593Smuzhiyun u32 pseudo_palette[16]; /* default palette */ 47*4882a593Smuzhiyun u32 palette[16]; /* for Riva128 */ 48*4882a593Smuzhiyun u8 __iomem *ctrl_base; /* virtual control register base addr */ 49*4882a593Smuzhiyun unsigned dclk_max; /* max DCLK */ 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun struct riva_regs initial_state; /* initial startup video mode */ 52*4882a593Smuzhiyun struct riva_regs current_state; 53*4882a593Smuzhiyun #ifdef CONFIG_X86 54*4882a593Smuzhiyun struct vgastate state; 55*4882a593Smuzhiyun #endif 56*4882a593Smuzhiyun struct mutex open_lock; 57*4882a593Smuzhiyun unsigned int ref_count; 58*4882a593Smuzhiyun unsigned char *EDID; 59*4882a593Smuzhiyun unsigned int Chipset; 60*4882a593Smuzhiyun int forceCRTC; 61*4882a593Smuzhiyun Bool SecondCRTC; 62*4882a593Smuzhiyun int FlatPanel; 63*4882a593Smuzhiyun struct pci_dev *pdev; 64*4882a593Smuzhiyun int cursor_reset; 65*4882a593Smuzhiyun int wc_cookie; 66*4882a593Smuzhiyun struct riva_i2c_chan chan[3]; 67*4882a593Smuzhiyun }; 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun void riva_common_setup(struct riva_par *); 70*4882a593Smuzhiyun unsigned long riva_get_memlen(struct riva_par *); 71*4882a593Smuzhiyun unsigned long riva_get_maxdclk(struct riva_par *); 72*4882a593Smuzhiyun void riva_delete_i2c_busses(struct riva_par *par); 73*4882a593Smuzhiyun void riva_create_i2c_busses(struct riva_par *par); 74*4882a593Smuzhiyun int riva_probe_i2c_connector(struct riva_par *par, int conn, u8 **out_edid); 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun #endif /* __RIVAFB_H */ 77