1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * drivers/video/pvr2fb.c
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Frame buffer and fbcon support for the NEC PowerVR2 found within the Sega
6*4882a593Smuzhiyun * Dreamcast.
7*4882a593Smuzhiyun *
8*4882a593Smuzhiyun * Copyright (c) 2001 M. R. Brown <mrbrown@0xd6.org>
9*4882a593Smuzhiyun * Copyright (c) 2001 - 2008 Paul Mundt <lethal@linux-sh.org>
10*4882a593Smuzhiyun *
11*4882a593Smuzhiyun * This driver is mostly based on the excellent amifb and vfb sources. It uses
12*4882a593Smuzhiyun * an odd scheme for converting hardware values to/from framebuffer values,
13*4882a593Smuzhiyun * here are some hacked-up formulas:
14*4882a593Smuzhiyun *
15*4882a593Smuzhiyun * The Dreamcast has screen offsets from each side of its four borders and
16*4882a593Smuzhiyun * the start offsets of the display window. I used these values to calculate
17*4882a593Smuzhiyun * 'pseudo' values (think of them as placeholders) for the fb video mode, so
18*4882a593Smuzhiyun * that when it came time to convert these values back into their hardware
19*4882a593Smuzhiyun * values, I could just add mode- specific offsets to get the correct mode
20*4882a593Smuzhiyun * settings:
21*4882a593Smuzhiyun *
22*4882a593Smuzhiyun * left_margin = diwstart_h - borderstart_h;
23*4882a593Smuzhiyun * right_margin = borderstop_h - (diwstart_h + xres);
24*4882a593Smuzhiyun * upper_margin = diwstart_v - borderstart_v;
25*4882a593Smuzhiyun * lower_margin = borderstop_v - (diwstart_h + yres);
26*4882a593Smuzhiyun *
27*4882a593Smuzhiyun * hsync_len = borderstart_h + (hsync_total - borderstop_h);
28*4882a593Smuzhiyun * vsync_len = borderstart_v + (vsync_total - borderstop_v);
29*4882a593Smuzhiyun *
30*4882a593Smuzhiyun * Then, when it's time to convert back to hardware settings, the only
31*4882a593Smuzhiyun * constants are the borderstart_* offsets, all other values are derived from
32*4882a593Smuzhiyun * the fb video mode:
33*4882a593Smuzhiyun *
34*4882a593Smuzhiyun * // PAL
35*4882a593Smuzhiyun * borderstart_h = 116;
36*4882a593Smuzhiyun * borderstart_v = 44;
37*4882a593Smuzhiyun * ...
38*4882a593Smuzhiyun * borderstop_h = borderstart_h + hsync_total - hsync_len;
39*4882a593Smuzhiyun * ...
40*4882a593Smuzhiyun * diwstart_v = borderstart_v - upper_margin;
41*4882a593Smuzhiyun *
42*4882a593Smuzhiyun * However, in the current implementation, the borderstart values haven't had
43*4882a593Smuzhiyun * the benefit of being fully researched, so some modes may be broken.
44*4882a593Smuzhiyun */
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun #undef DEBUG
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun #include <linux/module.h>
49*4882a593Smuzhiyun #include <linux/kernel.h>
50*4882a593Smuzhiyun #include <linux/errno.h>
51*4882a593Smuzhiyun #include <linux/string.h>
52*4882a593Smuzhiyun #include <linux/mm.h>
53*4882a593Smuzhiyun #include <linux/slab.h>
54*4882a593Smuzhiyun #include <linux/delay.h>
55*4882a593Smuzhiyun #include <linux/interrupt.h>
56*4882a593Smuzhiyun #include <linux/fb.h>
57*4882a593Smuzhiyun #include <linux/init.h>
58*4882a593Smuzhiyun #include <linux/pci.h>
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun #ifdef CONFIG_SH_DREAMCAST
61*4882a593Smuzhiyun #include <asm/machvec.h>
62*4882a593Smuzhiyun #include <mach-dreamcast/mach/sysasic.h>
63*4882a593Smuzhiyun #endif
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun #ifdef CONFIG_PVR2_DMA
66*4882a593Smuzhiyun #include <linux/pagemap.h>
67*4882a593Smuzhiyun #include <mach/dma.h>
68*4882a593Smuzhiyun #include <asm/dma.h>
69*4882a593Smuzhiyun #endif
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun #ifdef CONFIG_SH_STORE_QUEUES
72*4882a593Smuzhiyun #include <linux/uaccess.h>
73*4882a593Smuzhiyun #include <cpu/sq.h>
74*4882a593Smuzhiyun #endif
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun #ifndef PCI_DEVICE_ID_NEC_NEON250
77*4882a593Smuzhiyun # define PCI_DEVICE_ID_NEC_NEON250 0x0067
78*4882a593Smuzhiyun #endif
79*4882a593Smuzhiyun
80*4882a593Smuzhiyun /* 2D video registers */
81*4882a593Smuzhiyun #define DISP_BASE par->mmio_base
82*4882a593Smuzhiyun #define DISP_BRDRCOLR (DISP_BASE + 0x40)
83*4882a593Smuzhiyun #define DISP_DIWMODE (DISP_BASE + 0x44)
84*4882a593Smuzhiyun #define DISP_DIWADDRL (DISP_BASE + 0x50)
85*4882a593Smuzhiyun #define DISP_DIWADDRS (DISP_BASE + 0x54)
86*4882a593Smuzhiyun #define DISP_DIWSIZE (DISP_BASE + 0x5c)
87*4882a593Smuzhiyun #define DISP_SYNCCONF (DISP_BASE + 0xd0)
88*4882a593Smuzhiyun #define DISP_BRDRHORZ (DISP_BASE + 0xd4)
89*4882a593Smuzhiyun #define DISP_SYNCSIZE (DISP_BASE + 0xd8)
90*4882a593Smuzhiyun #define DISP_BRDRVERT (DISP_BASE + 0xdc)
91*4882a593Smuzhiyun #define DISP_DIWCONF (DISP_BASE + 0xe8)
92*4882a593Smuzhiyun #define DISP_DIWHSTRT (DISP_BASE + 0xec)
93*4882a593Smuzhiyun #define DISP_DIWVSTRT (DISP_BASE + 0xf0)
94*4882a593Smuzhiyun #define DISP_PIXDEPTH (DISP_BASE + 0x108)
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun /* Pixel clocks, one for TV output, doubled for VGA output */
97*4882a593Smuzhiyun #define TV_CLK 74239
98*4882a593Smuzhiyun #define VGA_CLK 37119
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun /* This is for 60Hz - the VTOTAL is doubled for interlaced modes */
101*4882a593Smuzhiyun #define PAL_HTOTAL 863
102*4882a593Smuzhiyun #define PAL_VTOTAL 312
103*4882a593Smuzhiyun #define NTSC_HTOTAL 857
104*4882a593Smuzhiyun #define NTSC_VTOTAL 262
105*4882a593Smuzhiyun
106*4882a593Smuzhiyun /* Supported cable types */
107*4882a593Smuzhiyun enum { CT_VGA, CT_NONE, CT_RGB, CT_COMPOSITE };
108*4882a593Smuzhiyun
109*4882a593Smuzhiyun /* Supported video output types */
110*4882a593Smuzhiyun enum { VO_PAL, VO_NTSC, VO_VGA };
111*4882a593Smuzhiyun
112*4882a593Smuzhiyun /* Supported palette types */
113*4882a593Smuzhiyun enum { PAL_ARGB1555, PAL_RGB565, PAL_ARGB4444, PAL_ARGB8888 };
114*4882a593Smuzhiyun
115*4882a593Smuzhiyun struct pvr2_params { unsigned int val; char *name; };
116*4882a593Smuzhiyun static struct pvr2_params cables[] = {
117*4882a593Smuzhiyun { CT_VGA, "VGA" }, { CT_RGB, "RGB" }, { CT_COMPOSITE, "COMPOSITE" },
118*4882a593Smuzhiyun };
119*4882a593Smuzhiyun
120*4882a593Smuzhiyun static struct pvr2_params outputs[] = {
121*4882a593Smuzhiyun { VO_PAL, "PAL" }, { VO_NTSC, "NTSC" }, { VO_VGA, "VGA" },
122*4882a593Smuzhiyun };
123*4882a593Smuzhiyun
124*4882a593Smuzhiyun /*
125*4882a593Smuzhiyun * This describes the current video mode
126*4882a593Smuzhiyun */
127*4882a593Smuzhiyun
128*4882a593Smuzhiyun static struct pvr2fb_par {
129*4882a593Smuzhiyun unsigned int hsync_total; /* Clocks/line */
130*4882a593Smuzhiyun unsigned int vsync_total; /* Lines/field */
131*4882a593Smuzhiyun unsigned int borderstart_h;
132*4882a593Smuzhiyun unsigned int borderstop_h;
133*4882a593Smuzhiyun unsigned int borderstart_v;
134*4882a593Smuzhiyun unsigned int borderstop_v;
135*4882a593Smuzhiyun unsigned int diwstart_h; /* Horizontal offset of the display field */
136*4882a593Smuzhiyun unsigned int diwstart_v; /* Vertical offset of the display field, for
137*4882a593Smuzhiyun interlaced modes, this is the long field */
138*4882a593Smuzhiyun unsigned long disp_start; /* Address of image within VRAM */
139*4882a593Smuzhiyun unsigned char is_interlaced; /* Is the display interlaced? */
140*4882a593Smuzhiyun unsigned char is_doublescan; /* Are scanlines output twice? (doublescan) */
141*4882a593Smuzhiyun unsigned char is_lowres; /* Is horizontal pixel-doubling enabled? */
142*4882a593Smuzhiyun
143*4882a593Smuzhiyun void __iomem *mmio_base; /* MMIO base */
144*4882a593Smuzhiyun u32 palette[16];
145*4882a593Smuzhiyun } *currentpar;
146*4882a593Smuzhiyun
147*4882a593Smuzhiyun static struct fb_info *fb_info;
148*4882a593Smuzhiyun
149*4882a593Smuzhiyun static struct fb_fix_screeninfo pvr2_fix = {
150*4882a593Smuzhiyun .id = "NEC PowerVR2",
151*4882a593Smuzhiyun .type = FB_TYPE_PACKED_PIXELS,
152*4882a593Smuzhiyun .visual = FB_VISUAL_TRUECOLOR,
153*4882a593Smuzhiyun .ypanstep = 1,
154*4882a593Smuzhiyun .ywrapstep = 1,
155*4882a593Smuzhiyun .accel = FB_ACCEL_NONE,
156*4882a593Smuzhiyun };
157*4882a593Smuzhiyun
158*4882a593Smuzhiyun static const struct fb_var_screeninfo pvr2_var = {
159*4882a593Smuzhiyun .xres = 640,
160*4882a593Smuzhiyun .yres = 480,
161*4882a593Smuzhiyun .xres_virtual = 640,
162*4882a593Smuzhiyun .yres_virtual = 480,
163*4882a593Smuzhiyun .bits_per_pixel =16,
164*4882a593Smuzhiyun .red = { 11, 5, 0 },
165*4882a593Smuzhiyun .green = { 5, 6, 0 },
166*4882a593Smuzhiyun .blue = { 0, 5, 0 },
167*4882a593Smuzhiyun .activate = FB_ACTIVATE_NOW,
168*4882a593Smuzhiyun .height = -1,
169*4882a593Smuzhiyun .width = -1,
170*4882a593Smuzhiyun .vmode = FB_VMODE_NONINTERLACED,
171*4882a593Smuzhiyun };
172*4882a593Smuzhiyun
173*4882a593Smuzhiyun static int cable_type = CT_VGA;
174*4882a593Smuzhiyun static int video_output = VO_VGA;
175*4882a593Smuzhiyun
176*4882a593Smuzhiyun static int nopan = 0;
177*4882a593Smuzhiyun static int nowrap = 1;
178*4882a593Smuzhiyun
179*4882a593Smuzhiyun /*
180*4882a593Smuzhiyun * We do all updating, blanking, etc. during the vertical retrace period
181*4882a593Smuzhiyun */
182*4882a593Smuzhiyun static unsigned int do_vmode_full = 0; /* Change the video mode */
183*4882a593Smuzhiyun static unsigned int do_vmode_pan = 0; /* Update the video mode */
184*4882a593Smuzhiyun static short do_blank = 0; /* (Un)Blank the screen */
185*4882a593Smuzhiyun
186*4882a593Smuzhiyun static unsigned int is_blanked = 0; /* Is the screen blanked? */
187*4882a593Smuzhiyun
188*4882a593Smuzhiyun #ifdef CONFIG_SH_STORE_QUEUES
189*4882a593Smuzhiyun static unsigned long pvr2fb_map;
190*4882a593Smuzhiyun #endif
191*4882a593Smuzhiyun
192*4882a593Smuzhiyun #ifdef CONFIG_PVR2_DMA
193*4882a593Smuzhiyun static unsigned int shdma = PVR2_CASCADE_CHAN;
194*4882a593Smuzhiyun static unsigned int pvr2dma = ONCHIP_NR_DMA_CHANNELS;
195*4882a593Smuzhiyun #endif
196*4882a593Smuzhiyun
197*4882a593Smuzhiyun static struct fb_videomode pvr2_modedb[] = {
198*4882a593Smuzhiyun /*
199*4882a593Smuzhiyun * Broadcast video modes (PAL and NTSC). I'm unfamiliar with
200*4882a593Smuzhiyun * PAL-M and PAL-N, but from what I've read both modes parallel PAL and
201*4882a593Smuzhiyun * NTSC, so it shouldn't be a problem (I hope).
202*4882a593Smuzhiyun */
203*4882a593Smuzhiyun
204*4882a593Smuzhiyun {
205*4882a593Smuzhiyun /* 640x480 @ 60Hz interlaced (NTSC) */
206*4882a593Smuzhiyun "ntsc_640x480i", 60, 640, 480, TV_CLK, 38, 33, 0, 18, 146, 26,
207*4882a593Smuzhiyun FB_SYNC_BROADCAST, FB_VMODE_INTERLACED | FB_VMODE_YWRAP
208*4882a593Smuzhiyun }, {
209*4882a593Smuzhiyun /* 640x240 @ 60Hz (NTSC) */
210*4882a593Smuzhiyun /* XXX: Broken! Don't use... */
211*4882a593Smuzhiyun "ntsc_640x240", 60, 640, 240, TV_CLK, 38, 33, 0, 0, 146, 22,
212*4882a593Smuzhiyun FB_SYNC_BROADCAST, FB_VMODE_YWRAP
213*4882a593Smuzhiyun }, {
214*4882a593Smuzhiyun /* 640x480 @ 60hz (VGA) */
215*4882a593Smuzhiyun "vga_640x480", 60, 640, 480, VGA_CLK, 38, 33, 0, 18, 146, 26,
216*4882a593Smuzhiyun 0, FB_VMODE_YWRAP
217*4882a593Smuzhiyun },
218*4882a593Smuzhiyun };
219*4882a593Smuzhiyun
220*4882a593Smuzhiyun #define NUM_TOTAL_MODES ARRAY_SIZE(pvr2_modedb)
221*4882a593Smuzhiyun
222*4882a593Smuzhiyun #define DEFMODE_NTSC 0
223*4882a593Smuzhiyun #define DEFMODE_PAL 0
224*4882a593Smuzhiyun #define DEFMODE_VGA 2
225*4882a593Smuzhiyun
226*4882a593Smuzhiyun static int defmode = DEFMODE_NTSC;
227*4882a593Smuzhiyun static char *mode_option = NULL;
228*4882a593Smuzhiyun
pvr2fb_set_pal_type(unsigned int type)229*4882a593Smuzhiyun static inline void pvr2fb_set_pal_type(unsigned int type)
230*4882a593Smuzhiyun {
231*4882a593Smuzhiyun struct pvr2fb_par *par = (struct pvr2fb_par *)fb_info->par;
232*4882a593Smuzhiyun
233*4882a593Smuzhiyun fb_writel(type, par->mmio_base + 0x108);
234*4882a593Smuzhiyun }
235*4882a593Smuzhiyun
pvr2fb_set_pal_entry(struct pvr2fb_par * par,unsigned int regno,unsigned int val)236*4882a593Smuzhiyun static inline void pvr2fb_set_pal_entry(struct pvr2fb_par *par,
237*4882a593Smuzhiyun unsigned int regno,
238*4882a593Smuzhiyun unsigned int val)
239*4882a593Smuzhiyun {
240*4882a593Smuzhiyun fb_writel(val, par->mmio_base + 0x1000 + (4 * regno));
241*4882a593Smuzhiyun }
242*4882a593Smuzhiyun
pvr2fb_blank(int blank,struct fb_info * info)243*4882a593Smuzhiyun static int pvr2fb_blank(int blank, struct fb_info *info)
244*4882a593Smuzhiyun {
245*4882a593Smuzhiyun do_blank = blank ? blank : -1;
246*4882a593Smuzhiyun return 0;
247*4882a593Smuzhiyun }
248*4882a593Smuzhiyun
get_line_length(int xres_virtual,int bpp)249*4882a593Smuzhiyun static inline unsigned long get_line_length(int xres_virtual, int bpp)
250*4882a593Smuzhiyun {
251*4882a593Smuzhiyun return (unsigned long)((((xres_virtual*bpp)+31)&~31) >> 3);
252*4882a593Smuzhiyun }
253*4882a593Smuzhiyun
set_color_bitfields(struct fb_var_screeninfo * var)254*4882a593Smuzhiyun static void set_color_bitfields(struct fb_var_screeninfo *var)
255*4882a593Smuzhiyun {
256*4882a593Smuzhiyun switch (var->bits_per_pixel) {
257*4882a593Smuzhiyun case 16: /* RGB 565 */
258*4882a593Smuzhiyun pvr2fb_set_pal_type(PAL_RGB565);
259*4882a593Smuzhiyun var->red.offset = 11; var->red.length = 5;
260*4882a593Smuzhiyun var->green.offset = 5; var->green.length = 6;
261*4882a593Smuzhiyun var->blue.offset = 0; var->blue.length = 5;
262*4882a593Smuzhiyun var->transp.offset = 0; var->transp.length = 0;
263*4882a593Smuzhiyun break;
264*4882a593Smuzhiyun case 24: /* RGB 888 */
265*4882a593Smuzhiyun var->red.offset = 16; var->red.length = 8;
266*4882a593Smuzhiyun var->green.offset = 8; var->green.length = 8;
267*4882a593Smuzhiyun var->blue.offset = 0; var->blue.length = 8;
268*4882a593Smuzhiyun var->transp.offset = 0; var->transp.length = 0;
269*4882a593Smuzhiyun break;
270*4882a593Smuzhiyun case 32: /* ARGB 8888 */
271*4882a593Smuzhiyun pvr2fb_set_pal_type(PAL_ARGB8888);
272*4882a593Smuzhiyun var->red.offset = 16; var->red.length = 8;
273*4882a593Smuzhiyun var->green.offset = 8; var->green.length = 8;
274*4882a593Smuzhiyun var->blue.offset = 0; var->blue.length = 8;
275*4882a593Smuzhiyun var->transp.offset = 24; var->transp.length = 8;
276*4882a593Smuzhiyun break;
277*4882a593Smuzhiyun }
278*4882a593Smuzhiyun }
279*4882a593Smuzhiyun
pvr2fb_setcolreg(unsigned int regno,unsigned int red,unsigned int green,unsigned int blue,unsigned int transp,struct fb_info * info)280*4882a593Smuzhiyun static int pvr2fb_setcolreg(unsigned int regno, unsigned int red,
281*4882a593Smuzhiyun unsigned int green, unsigned int blue,
282*4882a593Smuzhiyun unsigned int transp, struct fb_info *info)
283*4882a593Smuzhiyun {
284*4882a593Smuzhiyun struct pvr2fb_par *par = (struct pvr2fb_par *)info->par;
285*4882a593Smuzhiyun unsigned int tmp;
286*4882a593Smuzhiyun
287*4882a593Smuzhiyun if (regno > info->cmap.len)
288*4882a593Smuzhiyun return 1;
289*4882a593Smuzhiyun
290*4882a593Smuzhiyun /*
291*4882a593Smuzhiyun * We only support the hardware palette for 16 and 32bpp. It's also
292*4882a593Smuzhiyun * expected that the palette format has been set by the time we get
293*4882a593Smuzhiyun * here, so we don't waste time setting it again.
294*4882a593Smuzhiyun */
295*4882a593Smuzhiyun switch (info->var.bits_per_pixel) {
296*4882a593Smuzhiyun case 16: /* RGB 565 */
297*4882a593Smuzhiyun tmp = (red & 0xf800) |
298*4882a593Smuzhiyun ((green & 0xfc00) >> 5) |
299*4882a593Smuzhiyun ((blue & 0xf800) >> 11);
300*4882a593Smuzhiyun
301*4882a593Smuzhiyun pvr2fb_set_pal_entry(par, regno, tmp);
302*4882a593Smuzhiyun break;
303*4882a593Smuzhiyun case 24: /* RGB 888 */
304*4882a593Smuzhiyun red >>= 8; green >>= 8; blue >>= 8;
305*4882a593Smuzhiyun tmp = (red << 16) | (green << 8) | blue;
306*4882a593Smuzhiyun break;
307*4882a593Smuzhiyun case 32: /* ARGB 8888 */
308*4882a593Smuzhiyun red >>= 8; green >>= 8; blue >>= 8;
309*4882a593Smuzhiyun tmp = (transp << 24) | (red << 16) | (green << 8) | blue;
310*4882a593Smuzhiyun
311*4882a593Smuzhiyun pvr2fb_set_pal_entry(par, regno, tmp);
312*4882a593Smuzhiyun break;
313*4882a593Smuzhiyun default:
314*4882a593Smuzhiyun pr_debug("Invalid bit depth %d?!?\n", info->var.bits_per_pixel);
315*4882a593Smuzhiyun return 1;
316*4882a593Smuzhiyun }
317*4882a593Smuzhiyun
318*4882a593Smuzhiyun if (regno < 16)
319*4882a593Smuzhiyun ((u32*)(info->pseudo_palette))[regno] = tmp;
320*4882a593Smuzhiyun
321*4882a593Smuzhiyun return 0;
322*4882a593Smuzhiyun }
323*4882a593Smuzhiyun
324*4882a593Smuzhiyun /*
325*4882a593Smuzhiyun * Determine the cable type and initialize the cable output format. Don't do
326*4882a593Smuzhiyun * anything if the cable type has been overidden (via "cable:XX").
327*4882a593Smuzhiyun */
328*4882a593Smuzhiyun
329*4882a593Smuzhiyun #define PCTRA ((void __iomem *)0xff80002c)
330*4882a593Smuzhiyun #define PDTRA ((void __iomem *)0xff800030)
331*4882a593Smuzhiyun #define VOUTC ((void __iomem *)0xa0702c00)
332*4882a593Smuzhiyun
pvr2_init_cable(void)333*4882a593Smuzhiyun static int pvr2_init_cable(void)
334*4882a593Smuzhiyun {
335*4882a593Smuzhiyun if (cable_type < 0) {
336*4882a593Smuzhiyun fb_writel((fb_readl(PCTRA) & 0xfff0ffff) | 0x000a0000,
337*4882a593Smuzhiyun PCTRA);
338*4882a593Smuzhiyun cable_type = (fb_readw(PDTRA) >> 8) & 3;
339*4882a593Smuzhiyun }
340*4882a593Smuzhiyun
341*4882a593Smuzhiyun /* Now select the output format (either composite or other) */
342*4882a593Smuzhiyun /* XXX: Save the previous val first, as this reg is also AICA
343*4882a593Smuzhiyun related */
344*4882a593Smuzhiyun if (cable_type == CT_COMPOSITE)
345*4882a593Smuzhiyun fb_writel(3 << 8, VOUTC);
346*4882a593Smuzhiyun else if (cable_type == CT_RGB)
347*4882a593Smuzhiyun fb_writel(1 << 9, VOUTC);
348*4882a593Smuzhiyun else
349*4882a593Smuzhiyun fb_writel(0, VOUTC);
350*4882a593Smuzhiyun
351*4882a593Smuzhiyun return cable_type;
352*4882a593Smuzhiyun }
353*4882a593Smuzhiyun
pvr2fb_set_par(struct fb_info * info)354*4882a593Smuzhiyun static int pvr2fb_set_par(struct fb_info *info)
355*4882a593Smuzhiyun {
356*4882a593Smuzhiyun struct pvr2fb_par *par = (struct pvr2fb_par *)info->par;
357*4882a593Smuzhiyun struct fb_var_screeninfo *var = &info->var;
358*4882a593Smuzhiyun unsigned long line_length;
359*4882a593Smuzhiyun unsigned int vtotal;
360*4882a593Smuzhiyun
361*4882a593Smuzhiyun /*
362*4882a593Smuzhiyun * XXX: It's possible that a user could use a VGA box, change the cable
363*4882a593Smuzhiyun * type in hardware (i.e. switch from VGA<->composite), then change
364*4882a593Smuzhiyun * modes (i.e. switching to another VT). If that happens we should
365*4882a593Smuzhiyun * automagically change the output format to cope, but currently I
366*4882a593Smuzhiyun * don't have a VGA box to make sure this works properly.
367*4882a593Smuzhiyun */
368*4882a593Smuzhiyun cable_type = pvr2_init_cable();
369*4882a593Smuzhiyun if (cable_type == CT_VGA && video_output != VO_VGA)
370*4882a593Smuzhiyun video_output = VO_VGA;
371*4882a593Smuzhiyun
372*4882a593Smuzhiyun var->vmode &= FB_VMODE_MASK;
373*4882a593Smuzhiyun if (var->vmode & FB_VMODE_INTERLACED && video_output != VO_VGA)
374*4882a593Smuzhiyun par->is_interlaced = 1;
375*4882a593Smuzhiyun /*
376*4882a593Smuzhiyun * XXX: Need to be more creative with this (i.e. allow doublecan for
377*4882a593Smuzhiyun * PAL/NTSC output).
378*4882a593Smuzhiyun */
379*4882a593Smuzhiyun if (var->vmode & FB_VMODE_DOUBLE && video_output == VO_VGA)
380*4882a593Smuzhiyun par->is_doublescan = 1;
381*4882a593Smuzhiyun
382*4882a593Smuzhiyun par->hsync_total = var->left_margin + var->xres + var->right_margin +
383*4882a593Smuzhiyun var->hsync_len;
384*4882a593Smuzhiyun par->vsync_total = var->upper_margin + var->yres + var->lower_margin +
385*4882a593Smuzhiyun var->vsync_len;
386*4882a593Smuzhiyun
387*4882a593Smuzhiyun if (var->sync & FB_SYNC_BROADCAST) {
388*4882a593Smuzhiyun vtotal = par->vsync_total;
389*4882a593Smuzhiyun if (par->is_interlaced)
390*4882a593Smuzhiyun vtotal /= 2;
391*4882a593Smuzhiyun if (vtotal > (PAL_VTOTAL + NTSC_VTOTAL)/2) {
392*4882a593Smuzhiyun /* XXX: Check for start values here... */
393*4882a593Smuzhiyun /* XXX: Check hardware for PAL-compatibility */
394*4882a593Smuzhiyun par->borderstart_h = 116;
395*4882a593Smuzhiyun par->borderstart_v = 44;
396*4882a593Smuzhiyun } else {
397*4882a593Smuzhiyun /* NTSC video output */
398*4882a593Smuzhiyun par->borderstart_h = 126;
399*4882a593Smuzhiyun par->borderstart_v = 18;
400*4882a593Smuzhiyun }
401*4882a593Smuzhiyun } else {
402*4882a593Smuzhiyun /* VGA mode */
403*4882a593Smuzhiyun /* XXX: What else needs to be checked? */
404*4882a593Smuzhiyun /*
405*4882a593Smuzhiyun * XXX: We have a little freedom in VGA modes, what ranges
406*4882a593Smuzhiyun * should be here (i.e. hsync/vsync totals, etc.)?
407*4882a593Smuzhiyun */
408*4882a593Smuzhiyun par->borderstart_h = 126;
409*4882a593Smuzhiyun par->borderstart_v = 40;
410*4882a593Smuzhiyun }
411*4882a593Smuzhiyun
412*4882a593Smuzhiyun /* Calculate the remainding offsets */
413*4882a593Smuzhiyun par->diwstart_h = par->borderstart_h + var->left_margin;
414*4882a593Smuzhiyun par->diwstart_v = par->borderstart_v + var->upper_margin;
415*4882a593Smuzhiyun par->borderstop_h = par->diwstart_h + var->xres +
416*4882a593Smuzhiyun var->right_margin;
417*4882a593Smuzhiyun par->borderstop_v = par->diwstart_v + var->yres +
418*4882a593Smuzhiyun var->lower_margin;
419*4882a593Smuzhiyun
420*4882a593Smuzhiyun if (!par->is_interlaced)
421*4882a593Smuzhiyun par->borderstop_v /= 2;
422*4882a593Smuzhiyun if (info->var.xres < 640)
423*4882a593Smuzhiyun par->is_lowres = 1;
424*4882a593Smuzhiyun
425*4882a593Smuzhiyun line_length = get_line_length(var->xres_virtual, var->bits_per_pixel);
426*4882a593Smuzhiyun par->disp_start = info->fix.smem_start + (line_length * var->yoffset) * line_length;
427*4882a593Smuzhiyun info->fix.line_length = line_length;
428*4882a593Smuzhiyun return 0;
429*4882a593Smuzhiyun }
430*4882a593Smuzhiyun
pvr2fb_check_var(struct fb_var_screeninfo * var,struct fb_info * info)431*4882a593Smuzhiyun static int pvr2fb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
432*4882a593Smuzhiyun {
433*4882a593Smuzhiyun struct pvr2fb_par *par = (struct pvr2fb_par *)info->par;
434*4882a593Smuzhiyun unsigned int vtotal, hsync_total;
435*4882a593Smuzhiyun unsigned long line_length;
436*4882a593Smuzhiyun
437*4882a593Smuzhiyun if (var->pixclock != TV_CLK && var->pixclock != VGA_CLK) {
438*4882a593Smuzhiyun pr_debug("Invalid pixclock value %d\n", var->pixclock);
439*4882a593Smuzhiyun return -EINVAL;
440*4882a593Smuzhiyun }
441*4882a593Smuzhiyun
442*4882a593Smuzhiyun if (var->xres < 320)
443*4882a593Smuzhiyun var->xres = 320;
444*4882a593Smuzhiyun if (var->yres < 240)
445*4882a593Smuzhiyun var->yres = 240;
446*4882a593Smuzhiyun if (var->xres_virtual < var->xres)
447*4882a593Smuzhiyun var->xres_virtual = var->xres;
448*4882a593Smuzhiyun if (var->yres_virtual < var->yres)
449*4882a593Smuzhiyun var->yres_virtual = var->yres;
450*4882a593Smuzhiyun
451*4882a593Smuzhiyun if (var->bits_per_pixel <= 16)
452*4882a593Smuzhiyun var->bits_per_pixel = 16;
453*4882a593Smuzhiyun else if (var->bits_per_pixel <= 24)
454*4882a593Smuzhiyun var->bits_per_pixel = 24;
455*4882a593Smuzhiyun else if (var->bits_per_pixel <= 32)
456*4882a593Smuzhiyun var->bits_per_pixel = 32;
457*4882a593Smuzhiyun
458*4882a593Smuzhiyun set_color_bitfields(var);
459*4882a593Smuzhiyun
460*4882a593Smuzhiyun if (var->vmode & FB_VMODE_YWRAP) {
461*4882a593Smuzhiyun if (var->xoffset || var->yoffset >= var->yres_virtual) {
462*4882a593Smuzhiyun var->xoffset = var->yoffset = 0;
463*4882a593Smuzhiyun } else {
464*4882a593Smuzhiyun if (var->xoffset > var->xres_virtual - var->xres ||
465*4882a593Smuzhiyun var->yoffset > var->yres_virtual - var->yres)
466*4882a593Smuzhiyun var->xoffset = var->yoffset = 0;
467*4882a593Smuzhiyun }
468*4882a593Smuzhiyun } else {
469*4882a593Smuzhiyun var->xoffset = var->yoffset = 0;
470*4882a593Smuzhiyun }
471*4882a593Smuzhiyun
472*4882a593Smuzhiyun /*
473*4882a593Smuzhiyun * XXX: Need to be more creative with this (i.e. allow doublecan for
474*4882a593Smuzhiyun * PAL/NTSC output).
475*4882a593Smuzhiyun */
476*4882a593Smuzhiyun if (var->yres < 480 && video_output == VO_VGA)
477*4882a593Smuzhiyun var->vmode |= FB_VMODE_DOUBLE;
478*4882a593Smuzhiyun
479*4882a593Smuzhiyun if (video_output != VO_VGA) {
480*4882a593Smuzhiyun var->sync |= FB_SYNC_BROADCAST;
481*4882a593Smuzhiyun var->vmode |= FB_VMODE_INTERLACED;
482*4882a593Smuzhiyun } else {
483*4882a593Smuzhiyun var->sync &= ~FB_SYNC_BROADCAST;
484*4882a593Smuzhiyun var->vmode &= ~FB_VMODE_INTERLACED;
485*4882a593Smuzhiyun var->vmode |= FB_VMODE_NONINTERLACED;
486*4882a593Smuzhiyun }
487*4882a593Smuzhiyun
488*4882a593Smuzhiyun if ((var->activate & FB_ACTIVATE_MASK) != FB_ACTIVATE_TEST) {
489*4882a593Smuzhiyun var->right_margin = par->borderstop_h -
490*4882a593Smuzhiyun (par->diwstart_h + var->xres);
491*4882a593Smuzhiyun var->left_margin = par->diwstart_h - par->borderstart_h;
492*4882a593Smuzhiyun var->hsync_len = par->borderstart_h +
493*4882a593Smuzhiyun (par->hsync_total - par->borderstop_h);
494*4882a593Smuzhiyun
495*4882a593Smuzhiyun var->upper_margin = par->diwstart_v - par->borderstart_v;
496*4882a593Smuzhiyun var->lower_margin = par->borderstop_v -
497*4882a593Smuzhiyun (par->diwstart_v + var->yres);
498*4882a593Smuzhiyun var->vsync_len = par->borderstop_v +
499*4882a593Smuzhiyun (par->vsync_total - par->borderstop_v);
500*4882a593Smuzhiyun }
501*4882a593Smuzhiyun
502*4882a593Smuzhiyun hsync_total = var->left_margin + var->xres + var->right_margin +
503*4882a593Smuzhiyun var->hsync_len;
504*4882a593Smuzhiyun vtotal = var->upper_margin + var->yres + var->lower_margin +
505*4882a593Smuzhiyun var->vsync_len;
506*4882a593Smuzhiyun
507*4882a593Smuzhiyun if (var->sync & FB_SYNC_BROADCAST) {
508*4882a593Smuzhiyun if (var->vmode & FB_VMODE_INTERLACED)
509*4882a593Smuzhiyun vtotal /= 2;
510*4882a593Smuzhiyun if (vtotal > (PAL_VTOTAL + NTSC_VTOTAL)/2) {
511*4882a593Smuzhiyun /* PAL video output */
512*4882a593Smuzhiyun /* XXX: Should be using a range here ... ? */
513*4882a593Smuzhiyun if (hsync_total != PAL_HTOTAL) {
514*4882a593Smuzhiyun pr_debug("invalid hsync total for PAL\n");
515*4882a593Smuzhiyun return -EINVAL;
516*4882a593Smuzhiyun }
517*4882a593Smuzhiyun } else {
518*4882a593Smuzhiyun /* NTSC video output */
519*4882a593Smuzhiyun if (hsync_total != NTSC_HTOTAL) {
520*4882a593Smuzhiyun pr_debug("invalid hsync total for NTSC\n");
521*4882a593Smuzhiyun return -EINVAL;
522*4882a593Smuzhiyun }
523*4882a593Smuzhiyun }
524*4882a593Smuzhiyun }
525*4882a593Smuzhiyun
526*4882a593Smuzhiyun /* Check memory sizes */
527*4882a593Smuzhiyun line_length = get_line_length(var->xres_virtual, var->bits_per_pixel);
528*4882a593Smuzhiyun if (line_length * var->yres_virtual > info->fix.smem_len)
529*4882a593Smuzhiyun return -ENOMEM;
530*4882a593Smuzhiyun
531*4882a593Smuzhiyun return 0;
532*4882a593Smuzhiyun }
533*4882a593Smuzhiyun
pvr2_update_display(struct fb_info * info)534*4882a593Smuzhiyun static void pvr2_update_display(struct fb_info *info)
535*4882a593Smuzhiyun {
536*4882a593Smuzhiyun struct pvr2fb_par *par = (struct pvr2fb_par *) info->par;
537*4882a593Smuzhiyun struct fb_var_screeninfo *var = &info->var;
538*4882a593Smuzhiyun
539*4882a593Smuzhiyun /* Update the start address of the display image */
540*4882a593Smuzhiyun fb_writel(par->disp_start, DISP_DIWADDRL);
541*4882a593Smuzhiyun fb_writel(par->disp_start +
542*4882a593Smuzhiyun get_line_length(var->xoffset+var->xres, var->bits_per_pixel),
543*4882a593Smuzhiyun DISP_DIWADDRS);
544*4882a593Smuzhiyun }
545*4882a593Smuzhiyun
546*4882a593Smuzhiyun /*
547*4882a593Smuzhiyun * Initialize the video mode. Currently, the 16bpp and 24bpp modes aren't
548*4882a593Smuzhiyun * very stable. It's probably due to the fact that a lot of the 2D video
549*4882a593Smuzhiyun * registers are still undocumented.
550*4882a593Smuzhiyun */
551*4882a593Smuzhiyun
pvr2_init_display(struct fb_info * info)552*4882a593Smuzhiyun static void pvr2_init_display(struct fb_info *info)
553*4882a593Smuzhiyun {
554*4882a593Smuzhiyun struct pvr2fb_par *par = (struct pvr2fb_par *) info->par;
555*4882a593Smuzhiyun struct fb_var_screeninfo *var = &info->var;
556*4882a593Smuzhiyun unsigned int diw_height, diw_width, diw_modulo = 1;
557*4882a593Smuzhiyun unsigned int bytesperpixel = var->bits_per_pixel >> 3;
558*4882a593Smuzhiyun
559*4882a593Smuzhiyun /* hsync and vsync totals */
560*4882a593Smuzhiyun fb_writel((par->vsync_total << 16) | par->hsync_total, DISP_SYNCSIZE);
561*4882a593Smuzhiyun
562*4882a593Smuzhiyun /* column height, modulo, row width */
563*4882a593Smuzhiyun /* since we're "panning" within vram, we need to offset things based
564*4882a593Smuzhiyun * on the offset from the virtual x start to our real gfx. */
565*4882a593Smuzhiyun if (video_output != VO_VGA && par->is_interlaced)
566*4882a593Smuzhiyun diw_modulo += info->fix.line_length / 4;
567*4882a593Smuzhiyun diw_height = (par->is_interlaced ? var->yres / 2 : var->yres);
568*4882a593Smuzhiyun diw_width = get_line_length(var->xres, var->bits_per_pixel) / 4;
569*4882a593Smuzhiyun fb_writel((diw_modulo << 20) | (--diw_height << 10) | --diw_width,
570*4882a593Smuzhiyun DISP_DIWSIZE);
571*4882a593Smuzhiyun
572*4882a593Smuzhiyun /* display address, long and short fields */
573*4882a593Smuzhiyun fb_writel(par->disp_start, DISP_DIWADDRL);
574*4882a593Smuzhiyun fb_writel(par->disp_start +
575*4882a593Smuzhiyun get_line_length(var->xoffset+var->xres, var->bits_per_pixel),
576*4882a593Smuzhiyun DISP_DIWADDRS);
577*4882a593Smuzhiyun
578*4882a593Smuzhiyun /* border horizontal, border vertical, border color */
579*4882a593Smuzhiyun fb_writel((par->borderstart_h << 16) | par->borderstop_h, DISP_BRDRHORZ);
580*4882a593Smuzhiyun fb_writel((par->borderstart_v << 16) | par->borderstop_v, DISP_BRDRVERT);
581*4882a593Smuzhiyun fb_writel(0, DISP_BRDRCOLR);
582*4882a593Smuzhiyun
583*4882a593Smuzhiyun /* display window start position */
584*4882a593Smuzhiyun fb_writel(par->diwstart_h, DISP_DIWHSTRT);
585*4882a593Smuzhiyun fb_writel((par->diwstart_v << 16) | par->diwstart_v, DISP_DIWVSTRT);
586*4882a593Smuzhiyun
587*4882a593Smuzhiyun /* misc. settings */
588*4882a593Smuzhiyun fb_writel((0x16 << 16) | par->is_lowres, DISP_DIWCONF);
589*4882a593Smuzhiyun
590*4882a593Smuzhiyun /* clock doubler (for VGA), scan doubler, display enable */
591*4882a593Smuzhiyun fb_writel(((video_output == VO_VGA) << 23) |
592*4882a593Smuzhiyun (par->is_doublescan << 1) | 1, DISP_DIWMODE);
593*4882a593Smuzhiyun
594*4882a593Smuzhiyun /* bits per pixel */
595*4882a593Smuzhiyun fb_writel(fb_readl(DISP_DIWMODE) | (--bytesperpixel << 2), DISP_DIWMODE);
596*4882a593Smuzhiyun fb_writel(bytesperpixel << 2, DISP_PIXDEPTH);
597*4882a593Smuzhiyun
598*4882a593Smuzhiyun /* video enable, color sync, interlace,
599*4882a593Smuzhiyun * hsync and vsync polarity (currently unused) */
600*4882a593Smuzhiyun fb_writel(0x100 | ((par->is_interlaced /*|4*/) << 4), DISP_SYNCCONF);
601*4882a593Smuzhiyun }
602*4882a593Smuzhiyun
603*4882a593Smuzhiyun /* Simulate blanking by making the border cover the entire screen */
604*4882a593Smuzhiyun
605*4882a593Smuzhiyun #define BLANK_BIT (1<<3)
606*4882a593Smuzhiyun
pvr2_do_blank(void)607*4882a593Smuzhiyun static void pvr2_do_blank(void)
608*4882a593Smuzhiyun {
609*4882a593Smuzhiyun struct pvr2fb_par *par = currentpar;
610*4882a593Smuzhiyun unsigned long diwconf;
611*4882a593Smuzhiyun
612*4882a593Smuzhiyun diwconf = fb_readl(DISP_DIWCONF);
613*4882a593Smuzhiyun if (do_blank > 0)
614*4882a593Smuzhiyun fb_writel(diwconf | BLANK_BIT, DISP_DIWCONF);
615*4882a593Smuzhiyun else
616*4882a593Smuzhiyun fb_writel(diwconf & ~BLANK_BIT, DISP_DIWCONF);
617*4882a593Smuzhiyun
618*4882a593Smuzhiyun is_blanked = do_blank > 0 ? do_blank : 0;
619*4882a593Smuzhiyun }
620*4882a593Smuzhiyun
pvr2fb_interrupt(int irq,void * dev_id)621*4882a593Smuzhiyun static irqreturn_t __maybe_unused pvr2fb_interrupt(int irq, void *dev_id)
622*4882a593Smuzhiyun {
623*4882a593Smuzhiyun struct fb_info *info = dev_id;
624*4882a593Smuzhiyun
625*4882a593Smuzhiyun if (do_vmode_pan || do_vmode_full)
626*4882a593Smuzhiyun pvr2_update_display(info);
627*4882a593Smuzhiyun if (do_vmode_full)
628*4882a593Smuzhiyun pvr2_init_display(info);
629*4882a593Smuzhiyun if (do_vmode_pan)
630*4882a593Smuzhiyun do_vmode_pan = 0;
631*4882a593Smuzhiyun if (do_vmode_full)
632*4882a593Smuzhiyun do_vmode_full = 0;
633*4882a593Smuzhiyun if (do_blank) {
634*4882a593Smuzhiyun pvr2_do_blank();
635*4882a593Smuzhiyun do_blank = 0;
636*4882a593Smuzhiyun }
637*4882a593Smuzhiyun return IRQ_HANDLED;
638*4882a593Smuzhiyun }
639*4882a593Smuzhiyun
640*4882a593Smuzhiyun #ifdef CONFIG_PVR2_DMA
pvr2fb_write(struct fb_info * info,const char * buf,size_t count,loff_t * ppos)641*4882a593Smuzhiyun static ssize_t pvr2fb_write(struct fb_info *info, const char *buf,
642*4882a593Smuzhiyun size_t count, loff_t *ppos)
643*4882a593Smuzhiyun {
644*4882a593Smuzhiyun unsigned long dst, start, end, len;
645*4882a593Smuzhiyun unsigned int nr_pages;
646*4882a593Smuzhiyun struct page **pages;
647*4882a593Smuzhiyun int ret, i;
648*4882a593Smuzhiyun
649*4882a593Smuzhiyun nr_pages = (count + PAGE_SIZE - 1) >> PAGE_SHIFT;
650*4882a593Smuzhiyun
651*4882a593Smuzhiyun pages = kmalloc_array(nr_pages, sizeof(struct page *), GFP_KERNEL);
652*4882a593Smuzhiyun if (!pages)
653*4882a593Smuzhiyun return -ENOMEM;
654*4882a593Smuzhiyun
655*4882a593Smuzhiyun ret = pin_user_pages_fast((unsigned long)buf, nr_pages, FOLL_WRITE, pages);
656*4882a593Smuzhiyun if (ret < nr_pages) {
657*4882a593Smuzhiyun if (ret < 0) {
658*4882a593Smuzhiyun /*
659*4882a593Smuzhiyun * Clamp the unsigned nr_pages to zero so that the
660*4882a593Smuzhiyun * error handling works. And leave ret at whatever
661*4882a593Smuzhiyun * -errno value was returned from GUP.
662*4882a593Smuzhiyun */
663*4882a593Smuzhiyun nr_pages = 0;
664*4882a593Smuzhiyun } else {
665*4882a593Smuzhiyun nr_pages = ret;
666*4882a593Smuzhiyun /*
667*4882a593Smuzhiyun * Use -EINVAL to represent a mildly desperate guess at
668*4882a593Smuzhiyun * why we got fewer pages (maybe even zero pages) than
669*4882a593Smuzhiyun * requested.
670*4882a593Smuzhiyun */
671*4882a593Smuzhiyun ret = -EINVAL;
672*4882a593Smuzhiyun }
673*4882a593Smuzhiyun goto out_unmap;
674*4882a593Smuzhiyun }
675*4882a593Smuzhiyun
676*4882a593Smuzhiyun dma_configure_channel(shdma, 0x12c1);
677*4882a593Smuzhiyun
678*4882a593Smuzhiyun dst = (unsigned long)fb_info->screen_base + *ppos;
679*4882a593Smuzhiyun start = (unsigned long)page_address(pages[0]);
680*4882a593Smuzhiyun end = (unsigned long)page_address(pages[nr_pages]);
681*4882a593Smuzhiyun len = nr_pages << PAGE_SHIFT;
682*4882a593Smuzhiyun
683*4882a593Smuzhiyun /* Half-assed contig check */
684*4882a593Smuzhiyun if (start + len == end) {
685*4882a593Smuzhiyun /* As we do this in one shot, it's either all or nothing.. */
686*4882a593Smuzhiyun if ((*ppos + len) > fb_info->fix.smem_len) {
687*4882a593Smuzhiyun ret = -ENOSPC;
688*4882a593Smuzhiyun goto out_unmap;
689*4882a593Smuzhiyun }
690*4882a593Smuzhiyun
691*4882a593Smuzhiyun dma_write(shdma, start, 0, len);
692*4882a593Smuzhiyun dma_write(pvr2dma, 0, dst, len);
693*4882a593Smuzhiyun dma_wait_for_completion(pvr2dma);
694*4882a593Smuzhiyun
695*4882a593Smuzhiyun goto out;
696*4882a593Smuzhiyun }
697*4882a593Smuzhiyun
698*4882a593Smuzhiyun /* Not contiguous, writeout per-page instead.. */
699*4882a593Smuzhiyun for (i = 0; i < nr_pages; i++, dst += PAGE_SIZE) {
700*4882a593Smuzhiyun if ((*ppos + (i << PAGE_SHIFT)) > fb_info->fix.smem_len) {
701*4882a593Smuzhiyun ret = -ENOSPC;
702*4882a593Smuzhiyun goto out_unmap;
703*4882a593Smuzhiyun }
704*4882a593Smuzhiyun
705*4882a593Smuzhiyun dma_write_page(shdma, (unsigned long)page_address(pages[i]), 0);
706*4882a593Smuzhiyun dma_write_page(pvr2dma, 0, dst);
707*4882a593Smuzhiyun dma_wait_for_completion(pvr2dma);
708*4882a593Smuzhiyun }
709*4882a593Smuzhiyun
710*4882a593Smuzhiyun out:
711*4882a593Smuzhiyun *ppos += count;
712*4882a593Smuzhiyun ret = count;
713*4882a593Smuzhiyun
714*4882a593Smuzhiyun out_unmap:
715*4882a593Smuzhiyun unpin_user_pages(pages, nr_pages);
716*4882a593Smuzhiyun kfree(pages);
717*4882a593Smuzhiyun
718*4882a593Smuzhiyun return ret;
719*4882a593Smuzhiyun }
720*4882a593Smuzhiyun #endif /* CONFIG_PVR2_DMA */
721*4882a593Smuzhiyun
722*4882a593Smuzhiyun static const struct fb_ops pvr2fb_ops = {
723*4882a593Smuzhiyun .owner = THIS_MODULE,
724*4882a593Smuzhiyun .fb_setcolreg = pvr2fb_setcolreg,
725*4882a593Smuzhiyun .fb_blank = pvr2fb_blank,
726*4882a593Smuzhiyun .fb_check_var = pvr2fb_check_var,
727*4882a593Smuzhiyun .fb_set_par = pvr2fb_set_par,
728*4882a593Smuzhiyun #ifdef CONFIG_PVR2_DMA
729*4882a593Smuzhiyun .fb_write = pvr2fb_write,
730*4882a593Smuzhiyun #endif
731*4882a593Smuzhiyun .fb_fillrect = cfb_fillrect,
732*4882a593Smuzhiyun .fb_copyarea = cfb_copyarea,
733*4882a593Smuzhiyun .fb_imageblit = cfb_imageblit,
734*4882a593Smuzhiyun };
735*4882a593Smuzhiyun
736*4882a593Smuzhiyun #ifndef MODULE
pvr2_get_param_val(const struct pvr2_params * p,const char * s,int size)737*4882a593Smuzhiyun static int pvr2_get_param_val(const struct pvr2_params *p, const char *s,
738*4882a593Smuzhiyun int size)
739*4882a593Smuzhiyun {
740*4882a593Smuzhiyun int i;
741*4882a593Smuzhiyun
742*4882a593Smuzhiyun for (i = 0; i < size; i++) {
743*4882a593Smuzhiyun if (!strncasecmp(p[i].name, s, strlen(s)))
744*4882a593Smuzhiyun return p[i].val;
745*4882a593Smuzhiyun }
746*4882a593Smuzhiyun return -1;
747*4882a593Smuzhiyun }
748*4882a593Smuzhiyun #endif
749*4882a593Smuzhiyun
pvr2_get_param_name(const struct pvr2_params * p,int val,int size)750*4882a593Smuzhiyun static char *pvr2_get_param_name(const struct pvr2_params *p, int val,
751*4882a593Smuzhiyun int size)
752*4882a593Smuzhiyun {
753*4882a593Smuzhiyun int i;
754*4882a593Smuzhiyun
755*4882a593Smuzhiyun for (i = 0; i < size; i++) {
756*4882a593Smuzhiyun if (p[i].val == val)
757*4882a593Smuzhiyun return p[i].name;
758*4882a593Smuzhiyun }
759*4882a593Smuzhiyun return NULL;
760*4882a593Smuzhiyun }
761*4882a593Smuzhiyun
762*4882a593Smuzhiyun /**
763*4882a593Smuzhiyun * pvr2fb_common_init
764*4882a593Smuzhiyun *
765*4882a593Smuzhiyun * Common init code for the PVR2 chips.
766*4882a593Smuzhiyun *
767*4882a593Smuzhiyun * This mostly takes care of the common aspects of the fb setup and
768*4882a593Smuzhiyun * registration. It's expected that the board-specific init code has
769*4882a593Smuzhiyun * already setup pvr2_fix with something meaningful at this point.
770*4882a593Smuzhiyun *
771*4882a593Smuzhiyun * Device info reporting is also done here, as well as picking a sane
772*4882a593Smuzhiyun * default from the modedb. For board-specific modelines, simply define
773*4882a593Smuzhiyun * a per-board modedb.
774*4882a593Smuzhiyun *
775*4882a593Smuzhiyun * Also worth noting is that the cable and video output types are likely
776*4882a593Smuzhiyun * always going to be VGA for the PCI-based PVR2 boards, but we leave this
777*4882a593Smuzhiyun * in for flexibility anyways. Who knows, maybe someone has tv-out on a
778*4882a593Smuzhiyun * PCI-based version of these things ;-)
779*4882a593Smuzhiyun */
pvr2fb_common_init(void)780*4882a593Smuzhiyun static int __maybe_unused pvr2fb_common_init(void)
781*4882a593Smuzhiyun {
782*4882a593Smuzhiyun struct pvr2fb_par *par = currentpar;
783*4882a593Smuzhiyun unsigned long modememused, rev;
784*4882a593Smuzhiyun
785*4882a593Smuzhiyun fb_info->screen_base = ioremap(pvr2_fix.smem_start,
786*4882a593Smuzhiyun pvr2_fix.smem_len);
787*4882a593Smuzhiyun
788*4882a593Smuzhiyun if (!fb_info->screen_base) {
789*4882a593Smuzhiyun printk(KERN_ERR "pvr2fb: Failed to remap smem space\n");
790*4882a593Smuzhiyun goto out_err;
791*4882a593Smuzhiyun }
792*4882a593Smuzhiyun
793*4882a593Smuzhiyun par->mmio_base = ioremap(pvr2_fix.mmio_start,
794*4882a593Smuzhiyun pvr2_fix.mmio_len);
795*4882a593Smuzhiyun if (!par->mmio_base) {
796*4882a593Smuzhiyun printk(KERN_ERR "pvr2fb: Failed to remap mmio space\n");
797*4882a593Smuzhiyun goto out_err;
798*4882a593Smuzhiyun }
799*4882a593Smuzhiyun
800*4882a593Smuzhiyun fb_memset(fb_info->screen_base, 0, pvr2_fix.smem_len);
801*4882a593Smuzhiyun
802*4882a593Smuzhiyun pvr2_fix.ypanstep = nopan ? 0 : 1;
803*4882a593Smuzhiyun pvr2_fix.ywrapstep = nowrap ? 0 : 1;
804*4882a593Smuzhiyun
805*4882a593Smuzhiyun fb_info->fbops = &pvr2fb_ops;
806*4882a593Smuzhiyun fb_info->fix = pvr2_fix;
807*4882a593Smuzhiyun fb_info->par = currentpar;
808*4882a593Smuzhiyun fb_info->pseudo_palette = currentpar->palette;
809*4882a593Smuzhiyun fb_info->flags = FBINFO_DEFAULT | FBINFO_HWACCEL_YPAN;
810*4882a593Smuzhiyun
811*4882a593Smuzhiyun if (video_output == VO_VGA)
812*4882a593Smuzhiyun defmode = DEFMODE_VGA;
813*4882a593Smuzhiyun
814*4882a593Smuzhiyun if (!mode_option)
815*4882a593Smuzhiyun mode_option = "640x480@60";
816*4882a593Smuzhiyun
817*4882a593Smuzhiyun if (!fb_find_mode(&fb_info->var, fb_info, mode_option, pvr2_modedb,
818*4882a593Smuzhiyun NUM_TOTAL_MODES, &pvr2_modedb[defmode], 16))
819*4882a593Smuzhiyun fb_info->var = pvr2_var;
820*4882a593Smuzhiyun
821*4882a593Smuzhiyun fb_alloc_cmap(&fb_info->cmap, 256, 0);
822*4882a593Smuzhiyun
823*4882a593Smuzhiyun if (register_framebuffer(fb_info) < 0)
824*4882a593Smuzhiyun goto out_err;
825*4882a593Smuzhiyun /*Must write PIXDEPTH to register before anything is displayed - so force init */
826*4882a593Smuzhiyun pvr2_init_display(fb_info);
827*4882a593Smuzhiyun
828*4882a593Smuzhiyun modememused = get_line_length(fb_info->var.xres_virtual,
829*4882a593Smuzhiyun fb_info->var.bits_per_pixel);
830*4882a593Smuzhiyun modememused *= fb_info->var.yres_virtual;
831*4882a593Smuzhiyun
832*4882a593Smuzhiyun rev = fb_readl(par->mmio_base + 0x04);
833*4882a593Smuzhiyun
834*4882a593Smuzhiyun fb_info(fb_info, "%s (rev %ld.%ld) frame buffer device, using %ldk/%ldk of video memory\n",
835*4882a593Smuzhiyun fb_info->fix.id, (rev >> 4) & 0x0f, rev & 0x0f,
836*4882a593Smuzhiyun modememused >> 10,
837*4882a593Smuzhiyun (unsigned long)(fb_info->fix.smem_len >> 10));
838*4882a593Smuzhiyun fb_info(fb_info, "Mode %dx%d-%d pitch = %ld cable: %s video output: %s\n",
839*4882a593Smuzhiyun fb_info->var.xres, fb_info->var.yres,
840*4882a593Smuzhiyun fb_info->var.bits_per_pixel,
841*4882a593Smuzhiyun get_line_length(fb_info->var.xres, fb_info->var.bits_per_pixel),
842*4882a593Smuzhiyun pvr2_get_param_name(cables, cable_type, 3),
843*4882a593Smuzhiyun pvr2_get_param_name(outputs, video_output, 3));
844*4882a593Smuzhiyun
845*4882a593Smuzhiyun #ifdef CONFIG_SH_STORE_QUEUES
846*4882a593Smuzhiyun fb_notice(fb_info, "registering with SQ API\n");
847*4882a593Smuzhiyun
848*4882a593Smuzhiyun pvr2fb_map = sq_remap(fb_info->fix.smem_start, fb_info->fix.smem_len,
849*4882a593Smuzhiyun fb_info->fix.id, PAGE_SHARED);
850*4882a593Smuzhiyun
851*4882a593Smuzhiyun fb_notice(fb_info, "Mapped video memory to SQ addr 0x%lx\n",
852*4882a593Smuzhiyun pvr2fb_map);
853*4882a593Smuzhiyun #endif
854*4882a593Smuzhiyun
855*4882a593Smuzhiyun return 0;
856*4882a593Smuzhiyun
857*4882a593Smuzhiyun out_err:
858*4882a593Smuzhiyun if (fb_info->screen_base)
859*4882a593Smuzhiyun iounmap(fb_info->screen_base);
860*4882a593Smuzhiyun if (par->mmio_base)
861*4882a593Smuzhiyun iounmap(par->mmio_base);
862*4882a593Smuzhiyun
863*4882a593Smuzhiyun return -ENXIO;
864*4882a593Smuzhiyun }
865*4882a593Smuzhiyun
866*4882a593Smuzhiyun #ifdef CONFIG_SH_DREAMCAST
pvr2fb_dc_init(void)867*4882a593Smuzhiyun static int __init pvr2fb_dc_init(void)
868*4882a593Smuzhiyun {
869*4882a593Smuzhiyun if (!mach_is_dreamcast())
870*4882a593Smuzhiyun return -ENXIO;
871*4882a593Smuzhiyun
872*4882a593Smuzhiyun /* Make a guess at the monitor based on the attached cable */
873*4882a593Smuzhiyun if (pvr2_init_cable() == CT_VGA) {
874*4882a593Smuzhiyun fb_info->monspecs.hfmin = 30000;
875*4882a593Smuzhiyun fb_info->monspecs.hfmax = 70000;
876*4882a593Smuzhiyun fb_info->monspecs.vfmin = 60;
877*4882a593Smuzhiyun fb_info->monspecs.vfmax = 60;
878*4882a593Smuzhiyun } else {
879*4882a593Smuzhiyun /* Not VGA, using a TV (taken from acornfb) */
880*4882a593Smuzhiyun fb_info->monspecs.hfmin = 15469;
881*4882a593Smuzhiyun fb_info->monspecs.hfmax = 15781;
882*4882a593Smuzhiyun fb_info->monspecs.vfmin = 49;
883*4882a593Smuzhiyun fb_info->monspecs.vfmax = 51;
884*4882a593Smuzhiyun }
885*4882a593Smuzhiyun
886*4882a593Smuzhiyun /*
887*4882a593Smuzhiyun * XXX: This needs to pull default video output via BIOS or other means
888*4882a593Smuzhiyun */
889*4882a593Smuzhiyun if (video_output < 0) {
890*4882a593Smuzhiyun if (cable_type == CT_VGA) {
891*4882a593Smuzhiyun video_output = VO_VGA;
892*4882a593Smuzhiyun } else {
893*4882a593Smuzhiyun video_output = VO_NTSC;
894*4882a593Smuzhiyun }
895*4882a593Smuzhiyun }
896*4882a593Smuzhiyun
897*4882a593Smuzhiyun /*
898*4882a593Smuzhiyun * Nothing exciting about the DC PVR2 .. only a measly 8MiB.
899*4882a593Smuzhiyun */
900*4882a593Smuzhiyun pvr2_fix.smem_start = 0xa5000000; /* RAM starts here */
901*4882a593Smuzhiyun pvr2_fix.smem_len = 8 << 20;
902*4882a593Smuzhiyun
903*4882a593Smuzhiyun pvr2_fix.mmio_start = 0xa05f8000; /* registers start here */
904*4882a593Smuzhiyun pvr2_fix.mmio_len = 0x2000;
905*4882a593Smuzhiyun
906*4882a593Smuzhiyun if (request_irq(HW_EVENT_VSYNC, pvr2fb_interrupt, IRQF_SHARED,
907*4882a593Smuzhiyun "pvr2 VBL handler", fb_info)) {
908*4882a593Smuzhiyun return -EBUSY;
909*4882a593Smuzhiyun }
910*4882a593Smuzhiyun
911*4882a593Smuzhiyun #ifdef CONFIG_PVR2_DMA
912*4882a593Smuzhiyun if (request_dma(pvr2dma, "pvr2") != 0) {
913*4882a593Smuzhiyun free_irq(HW_EVENT_VSYNC, fb_info);
914*4882a593Smuzhiyun return -EBUSY;
915*4882a593Smuzhiyun }
916*4882a593Smuzhiyun #endif
917*4882a593Smuzhiyun
918*4882a593Smuzhiyun return pvr2fb_common_init();
919*4882a593Smuzhiyun }
920*4882a593Smuzhiyun
pvr2fb_dc_exit(void)921*4882a593Smuzhiyun static void pvr2fb_dc_exit(void)
922*4882a593Smuzhiyun {
923*4882a593Smuzhiyun if (fb_info->screen_base) {
924*4882a593Smuzhiyun iounmap(fb_info->screen_base);
925*4882a593Smuzhiyun fb_info->screen_base = NULL;
926*4882a593Smuzhiyun }
927*4882a593Smuzhiyun if (currentpar->mmio_base) {
928*4882a593Smuzhiyun iounmap(currentpar->mmio_base);
929*4882a593Smuzhiyun currentpar->mmio_base = NULL;
930*4882a593Smuzhiyun }
931*4882a593Smuzhiyun
932*4882a593Smuzhiyun free_irq(HW_EVENT_VSYNC, fb_info);
933*4882a593Smuzhiyun #ifdef CONFIG_PVR2_DMA
934*4882a593Smuzhiyun free_dma(pvr2dma);
935*4882a593Smuzhiyun #endif
936*4882a593Smuzhiyun }
937*4882a593Smuzhiyun #endif /* CONFIG_SH_DREAMCAST */
938*4882a593Smuzhiyun
939*4882a593Smuzhiyun #ifdef CONFIG_PCI
pvr2fb_pci_probe(struct pci_dev * pdev,const struct pci_device_id * ent)940*4882a593Smuzhiyun static int pvr2fb_pci_probe(struct pci_dev *pdev,
941*4882a593Smuzhiyun const struct pci_device_id *ent)
942*4882a593Smuzhiyun {
943*4882a593Smuzhiyun int ret;
944*4882a593Smuzhiyun
945*4882a593Smuzhiyun ret = pci_enable_device(pdev);
946*4882a593Smuzhiyun if (ret) {
947*4882a593Smuzhiyun printk(KERN_ERR "pvr2fb: PCI enable failed\n");
948*4882a593Smuzhiyun return ret;
949*4882a593Smuzhiyun }
950*4882a593Smuzhiyun
951*4882a593Smuzhiyun ret = pci_request_regions(pdev, "pvr2fb");
952*4882a593Smuzhiyun if (ret) {
953*4882a593Smuzhiyun printk(KERN_ERR "pvr2fb: PCI request regions failed\n");
954*4882a593Smuzhiyun return ret;
955*4882a593Smuzhiyun }
956*4882a593Smuzhiyun
957*4882a593Smuzhiyun /*
958*4882a593Smuzhiyun * Slightly more exciting than the DC PVR2 .. 16MiB!
959*4882a593Smuzhiyun */
960*4882a593Smuzhiyun pvr2_fix.smem_start = pci_resource_start(pdev, 0);
961*4882a593Smuzhiyun pvr2_fix.smem_len = pci_resource_len(pdev, 0);
962*4882a593Smuzhiyun
963*4882a593Smuzhiyun pvr2_fix.mmio_start = pci_resource_start(pdev, 1);
964*4882a593Smuzhiyun pvr2_fix.mmio_len = pci_resource_len(pdev, 1);
965*4882a593Smuzhiyun
966*4882a593Smuzhiyun fb_info->device = &pdev->dev;
967*4882a593Smuzhiyun
968*4882a593Smuzhiyun return pvr2fb_common_init();
969*4882a593Smuzhiyun }
970*4882a593Smuzhiyun
pvr2fb_pci_remove(struct pci_dev * pdev)971*4882a593Smuzhiyun static void pvr2fb_pci_remove(struct pci_dev *pdev)
972*4882a593Smuzhiyun {
973*4882a593Smuzhiyun if (fb_info->screen_base) {
974*4882a593Smuzhiyun iounmap(fb_info->screen_base);
975*4882a593Smuzhiyun fb_info->screen_base = NULL;
976*4882a593Smuzhiyun }
977*4882a593Smuzhiyun if (currentpar->mmio_base) {
978*4882a593Smuzhiyun iounmap(currentpar->mmio_base);
979*4882a593Smuzhiyun currentpar->mmio_base = NULL;
980*4882a593Smuzhiyun }
981*4882a593Smuzhiyun
982*4882a593Smuzhiyun pci_release_regions(pdev);
983*4882a593Smuzhiyun }
984*4882a593Smuzhiyun
985*4882a593Smuzhiyun static const struct pci_device_id pvr2fb_pci_tbl[] = {
986*4882a593Smuzhiyun { PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_NEON250,
987*4882a593Smuzhiyun PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
988*4882a593Smuzhiyun { 0, },
989*4882a593Smuzhiyun };
990*4882a593Smuzhiyun
991*4882a593Smuzhiyun MODULE_DEVICE_TABLE(pci, pvr2fb_pci_tbl);
992*4882a593Smuzhiyun
993*4882a593Smuzhiyun static struct pci_driver pvr2fb_pci_driver = {
994*4882a593Smuzhiyun .name = "pvr2fb",
995*4882a593Smuzhiyun .id_table = pvr2fb_pci_tbl,
996*4882a593Smuzhiyun .probe = pvr2fb_pci_probe,
997*4882a593Smuzhiyun .remove = pvr2fb_pci_remove,
998*4882a593Smuzhiyun };
999*4882a593Smuzhiyun
pvr2fb_pci_init(void)1000*4882a593Smuzhiyun static int __init pvr2fb_pci_init(void)
1001*4882a593Smuzhiyun {
1002*4882a593Smuzhiyun return pci_register_driver(&pvr2fb_pci_driver);
1003*4882a593Smuzhiyun }
1004*4882a593Smuzhiyun
pvr2fb_pci_exit(void)1005*4882a593Smuzhiyun static void pvr2fb_pci_exit(void)
1006*4882a593Smuzhiyun {
1007*4882a593Smuzhiyun pci_unregister_driver(&pvr2fb_pci_driver);
1008*4882a593Smuzhiyun }
1009*4882a593Smuzhiyun #endif /* CONFIG_PCI */
1010*4882a593Smuzhiyun
1011*4882a593Smuzhiyun /*
1012*4882a593Smuzhiyun * Parse command arguments. Supported arguments are:
1013*4882a593Smuzhiyun * inverse Use inverse color maps
1014*4882a593Smuzhiyun * cable:composite|rgb|vga Override the video cable type
1015*4882a593Smuzhiyun * output:NTSC|PAL|VGA Override the video output format
1016*4882a593Smuzhiyun *
1017*4882a593Smuzhiyun * <xres>x<yres>[-<bpp>][@<refresh>] or,
1018*4882a593Smuzhiyun * <name>[-<bpp>][@<refresh>] Startup using this video mode
1019*4882a593Smuzhiyun */
1020*4882a593Smuzhiyun
1021*4882a593Smuzhiyun #ifndef MODULE
pvr2fb_setup(char * options)1022*4882a593Smuzhiyun static int __init pvr2fb_setup(char *options)
1023*4882a593Smuzhiyun {
1024*4882a593Smuzhiyun char *this_opt;
1025*4882a593Smuzhiyun char cable_arg[80];
1026*4882a593Smuzhiyun char output_arg[80];
1027*4882a593Smuzhiyun
1028*4882a593Smuzhiyun if (!options || !*options)
1029*4882a593Smuzhiyun return 0;
1030*4882a593Smuzhiyun
1031*4882a593Smuzhiyun cable_arg[0] = output_arg[0] = 0;
1032*4882a593Smuzhiyun
1033*4882a593Smuzhiyun while ((this_opt = strsep(&options, ","))) {
1034*4882a593Smuzhiyun if (!*this_opt)
1035*4882a593Smuzhiyun continue;
1036*4882a593Smuzhiyun if (!strcmp(this_opt, "inverse")) {
1037*4882a593Smuzhiyun fb_invert_cmaps();
1038*4882a593Smuzhiyun } else if (!strncmp(this_opt, "cable:", 6)) {
1039*4882a593Smuzhiyun strcpy(cable_arg, this_opt + 6);
1040*4882a593Smuzhiyun } else if (!strncmp(this_opt, "output:", 7)) {
1041*4882a593Smuzhiyun strcpy(output_arg, this_opt + 7);
1042*4882a593Smuzhiyun } else if (!strncmp(this_opt, "nopan", 5)) {
1043*4882a593Smuzhiyun nopan = 1;
1044*4882a593Smuzhiyun } else if (!strncmp(this_opt, "nowrap", 6)) {
1045*4882a593Smuzhiyun nowrap = 1;
1046*4882a593Smuzhiyun } else {
1047*4882a593Smuzhiyun mode_option = this_opt;
1048*4882a593Smuzhiyun }
1049*4882a593Smuzhiyun }
1050*4882a593Smuzhiyun
1051*4882a593Smuzhiyun if (*cable_arg)
1052*4882a593Smuzhiyun cable_type = pvr2_get_param_val(cables, cable_arg, 3);
1053*4882a593Smuzhiyun if (*output_arg)
1054*4882a593Smuzhiyun video_output = pvr2_get_param_val(outputs, output_arg, 3);
1055*4882a593Smuzhiyun
1056*4882a593Smuzhiyun return 0;
1057*4882a593Smuzhiyun }
1058*4882a593Smuzhiyun #endif
1059*4882a593Smuzhiyun
1060*4882a593Smuzhiyun static struct pvr2_board {
1061*4882a593Smuzhiyun int (*init)(void);
1062*4882a593Smuzhiyun void (*exit)(void);
1063*4882a593Smuzhiyun char name[16];
1064*4882a593Smuzhiyun } board_driver[] __refdata = {
1065*4882a593Smuzhiyun #ifdef CONFIG_SH_DREAMCAST
1066*4882a593Smuzhiyun { pvr2fb_dc_init, pvr2fb_dc_exit, "Sega DC PVR2" },
1067*4882a593Smuzhiyun #endif
1068*4882a593Smuzhiyun #ifdef CONFIG_PCI
1069*4882a593Smuzhiyun { pvr2fb_pci_init, pvr2fb_pci_exit, "PCI PVR2" },
1070*4882a593Smuzhiyun #endif
1071*4882a593Smuzhiyun { 0, },
1072*4882a593Smuzhiyun };
1073*4882a593Smuzhiyun
pvr2fb_init(void)1074*4882a593Smuzhiyun static int __init pvr2fb_init(void)
1075*4882a593Smuzhiyun {
1076*4882a593Smuzhiyun int i, ret = -ENODEV;
1077*4882a593Smuzhiyun
1078*4882a593Smuzhiyun #ifndef MODULE
1079*4882a593Smuzhiyun char *option = NULL;
1080*4882a593Smuzhiyun
1081*4882a593Smuzhiyun if (fb_get_options("pvr2fb", &option))
1082*4882a593Smuzhiyun return -ENODEV;
1083*4882a593Smuzhiyun pvr2fb_setup(option);
1084*4882a593Smuzhiyun #endif
1085*4882a593Smuzhiyun
1086*4882a593Smuzhiyun fb_info = framebuffer_alloc(sizeof(struct pvr2fb_par), NULL);
1087*4882a593Smuzhiyun if (!fb_info)
1088*4882a593Smuzhiyun return -ENOMEM;
1089*4882a593Smuzhiyun
1090*4882a593Smuzhiyun currentpar = fb_info->par;
1091*4882a593Smuzhiyun
1092*4882a593Smuzhiyun for (i = 0; i < ARRAY_SIZE(board_driver); i++) {
1093*4882a593Smuzhiyun struct pvr2_board *pvr_board = board_driver + i;
1094*4882a593Smuzhiyun
1095*4882a593Smuzhiyun if (!pvr_board->init)
1096*4882a593Smuzhiyun continue;
1097*4882a593Smuzhiyun
1098*4882a593Smuzhiyun ret = pvr_board->init();
1099*4882a593Smuzhiyun
1100*4882a593Smuzhiyun if (ret != 0) {
1101*4882a593Smuzhiyun printk(KERN_ERR "pvr2fb: Failed init of %s device\n",
1102*4882a593Smuzhiyun pvr_board->name);
1103*4882a593Smuzhiyun framebuffer_release(fb_info);
1104*4882a593Smuzhiyun break;
1105*4882a593Smuzhiyun }
1106*4882a593Smuzhiyun }
1107*4882a593Smuzhiyun
1108*4882a593Smuzhiyun return ret;
1109*4882a593Smuzhiyun }
1110*4882a593Smuzhiyun
pvr2fb_exit(void)1111*4882a593Smuzhiyun static void __exit pvr2fb_exit(void)
1112*4882a593Smuzhiyun {
1113*4882a593Smuzhiyun int i;
1114*4882a593Smuzhiyun
1115*4882a593Smuzhiyun for (i = 0; i < ARRAY_SIZE(board_driver); i++) {
1116*4882a593Smuzhiyun struct pvr2_board *pvr_board = board_driver + i;
1117*4882a593Smuzhiyun
1118*4882a593Smuzhiyun if (pvr_board->exit)
1119*4882a593Smuzhiyun pvr_board->exit();
1120*4882a593Smuzhiyun }
1121*4882a593Smuzhiyun
1122*4882a593Smuzhiyun #ifdef CONFIG_SH_STORE_QUEUES
1123*4882a593Smuzhiyun sq_unmap(pvr2fb_map);
1124*4882a593Smuzhiyun #endif
1125*4882a593Smuzhiyun
1126*4882a593Smuzhiyun unregister_framebuffer(fb_info);
1127*4882a593Smuzhiyun framebuffer_release(fb_info);
1128*4882a593Smuzhiyun }
1129*4882a593Smuzhiyun
1130*4882a593Smuzhiyun module_init(pvr2fb_init);
1131*4882a593Smuzhiyun module_exit(pvr2fb_exit);
1132*4882a593Smuzhiyun
1133*4882a593Smuzhiyun MODULE_AUTHOR("Paul Mundt <lethal@linux-sh.org>, M. R. Brown <mrbrown@0xd6.org>");
1134*4882a593Smuzhiyun MODULE_DESCRIPTION("Framebuffer driver for NEC PowerVR 2 based graphics boards");
1135*4882a593Smuzhiyun MODULE_LICENSE("GPL");
1136