xref: /OK3568_Linux_fs/kernel/drivers/video/fbdev/omap2/omapfb/dss/hdmi5.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * HDMI driver for OMAP5
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Copyright (C) 2014 Texas Instruments Incorporated
6*4882a593Smuzhiyun  *
7*4882a593Smuzhiyun  * Authors:
8*4882a593Smuzhiyun  *	Yong Zhi
9*4882a593Smuzhiyun  *	Mythri pk
10*4882a593Smuzhiyun  *	Archit Taneja <archit@ti.com>
11*4882a593Smuzhiyun  *	Tomi Valkeinen <tomi.valkeinen@ti.com>
12*4882a593Smuzhiyun  */
13*4882a593Smuzhiyun 
14*4882a593Smuzhiyun #define DSS_SUBSYS_NAME "HDMI"
15*4882a593Smuzhiyun 
16*4882a593Smuzhiyun #include <linux/kernel.h>
17*4882a593Smuzhiyun #include <linux/module.h>
18*4882a593Smuzhiyun #include <linux/err.h>
19*4882a593Smuzhiyun #include <linux/io.h>
20*4882a593Smuzhiyun #include <linux/interrupt.h>
21*4882a593Smuzhiyun #include <linux/mutex.h>
22*4882a593Smuzhiyun #include <linux/delay.h>
23*4882a593Smuzhiyun #include <linux/string.h>
24*4882a593Smuzhiyun #include <linux/platform_device.h>
25*4882a593Smuzhiyun #include <linux/pm_runtime.h>
26*4882a593Smuzhiyun #include <linux/clk.h>
27*4882a593Smuzhiyun #include <linux/of.h>
28*4882a593Smuzhiyun #include <linux/regulator/consumer.h>
29*4882a593Smuzhiyun #include <linux/component.h>
30*4882a593Smuzhiyun #include <video/omapfb_dss.h>
31*4882a593Smuzhiyun #include <sound/omap-hdmi-audio.h>
32*4882a593Smuzhiyun 
33*4882a593Smuzhiyun #include "hdmi5_core.h"
34*4882a593Smuzhiyun #include "dss.h"
35*4882a593Smuzhiyun #include "dss_features.h"
36*4882a593Smuzhiyun 
37*4882a593Smuzhiyun static struct omap_hdmi hdmi;
38*4882a593Smuzhiyun 
hdmi_runtime_get(void)39*4882a593Smuzhiyun static int hdmi_runtime_get(void)
40*4882a593Smuzhiyun {
41*4882a593Smuzhiyun 	int r;
42*4882a593Smuzhiyun 
43*4882a593Smuzhiyun 	DSSDBG("hdmi_runtime_get\n");
44*4882a593Smuzhiyun 
45*4882a593Smuzhiyun 	r = pm_runtime_get_sync(&hdmi.pdev->dev);
46*4882a593Smuzhiyun 	if (WARN_ON(r < 0)) {
47*4882a593Smuzhiyun 		pm_runtime_put_sync(&hdmi.pdev->dev);
48*4882a593Smuzhiyun 		return r;
49*4882a593Smuzhiyun 	}
50*4882a593Smuzhiyun 
51*4882a593Smuzhiyun 	return 0;
52*4882a593Smuzhiyun }
53*4882a593Smuzhiyun 
hdmi_runtime_put(void)54*4882a593Smuzhiyun static void hdmi_runtime_put(void)
55*4882a593Smuzhiyun {
56*4882a593Smuzhiyun 	int r;
57*4882a593Smuzhiyun 
58*4882a593Smuzhiyun 	DSSDBG("hdmi_runtime_put\n");
59*4882a593Smuzhiyun 
60*4882a593Smuzhiyun 	r = pm_runtime_put_sync(&hdmi.pdev->dev);
61*4882a593Smuzhiyun 	WARN_ON(r < 0 && r != -ENOSYS);
62*4882a593Smuzhiyun }
63*4882a593Smuzhiyun 
hdmi_irq_handler(int irq,void * data)64*4882a593Smuzhiyun static irqreturn_t hdmi_irq_handler(int irq, void *data)
65*4882a593Smuzhiyun {
66*4882a593Smuzhiyun 	struct hdmi_wp_data *wp = data;
67*4882a593Smuzhiyun 	u32 irqstatus;
68*4882a593Smuzhiyun 
69*4882a593Smuzhiyun 	irqstatus = hdmi_wp_get_irqstatus(wp);
70*4882a593Smuzhiyun 	hdmi_wp_set_irqstatus(wp, irqstatus);
71*4882a593Smuzhiyun 
72*4882a593Smuzhiyun 	if ((irqstatus & HDMI_IRQ_LINK_CONNECT) &&
73*4882a593Smuzhiyun 			irqstatus & HDMI_IRQ_LINK_DISCONNECT) {
74*4882a593Smuzhiyun 		u32 v;
75*4882a593Smuzhiyun 		/*
76*4882a593Smuzhiyun 		 * If we get both connect and disconnect interrupts at the same
77*4882a593Smuzhiyun 		 * time, turn off the PHY, clear interrupts, and restart, which
78*4882a593Smuzhiyun 		 * raises connect interrupt if a cable is connected, or nothing
79*4882a593Smuzhiyun 		 * if cable is not connected.
80*4882a593Smuzhiyun 		 */
81*4882a593Smuzhiyun 
82*4882a593Smuzhiyun 		hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_OFF);
83*4882a593Smuzhiyun 
84*4882a593Smuzhiyun 		/*
85*4882a593Smuzhiyun 		 * We always get bogus CONNECT & DISCONNECT interrupts when
86*4882a593Smuzhiyun 		 * setting the PHY to LDOON. To ignore those, we force the RXDET
87*4882a593Smuzhiyun 		 * line to 0 until the PHY power state has been changed.
88*4882a593Smuzhiyun 		 */
89*4882a593Smuzhiyun 		v = hdmi_read_reg(hdmi.phy.base, HDMI_TXPHY_PAD_CFG_CTRL);
90*4882a593Smuzhiyun 		v = FLD_MOD(v, 1, 15, 15); /* FORCE_RXDET_HIGH */
91*4882a593Smuzhiyun 		v = FLD_MOD(v, 0, 14, 7); /* RXDET_LINE */
92*4882a593Smuzhiyun 		hdmi_write_reg(hdmi.phy.base, HDMI_TXPHY_PAD_CFG_CTRL, v);
93*4882a593Smuzhiyun 
94*4882a593Smuzhiyun 		hdmi_wp_set_irqstatus(wp, HDMI_IRQ_LINK_CONNECT |
95*4882a593Smuzhiyun 				HDMI_IRQ_LINK_DISCONNECT);
96*4882a593Smuzhiyun 
97*4882a593Smuzhiyun 		hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_LDOON);
98*4882a593Smuzhiyun 
99*4882a593Smuzhiyun 		REG_FLD_MOD(hdmi.phy.base, HDMI_TXPHY_PAD_CFG_CTRL, 0, 15, 15);
100*4882a593Smuzhiyun 
101*4882a593Smuzhiyun 	} else if (irqstatus & HDMI_IRQ_LINK_CONNECT) {
102*4882a593Smuzhiyun 		hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_TXON);
103*4882a593Smuzhiyun 	} else if (irqstatus & HDMI_IRQ_LINK_DISCONNECT) {
104*4882a593Smuzhiyun 		hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_LDOON);
105*4882a593Smuzhiyun 	}
106*4882a593Smuzhiyun 
107*4882a593Smuzhiyun 	return IRQ_HANDLED;
108*4882a593Smuzhiyun }
109*4882a593Smuzhiyun 
hdmi_init_regulator(void)110*4882a593Smuzhiyun static int hdmi_init_regulator(void)
111*4882a593Smuzhiyun {
112*4882a593Smuzhiyun 	struct regulator *reg;
113*4882a593Smuzhiyun 
114*4882a593Smuzhiyun 	if (hdmi.vdda_reg != NULL)
115*4882a593Smuzhiyun 		return 0;
116*4882a593Smuzhiyun 
117*4882a593Smuzhiyun 	reg = devm_regulator_get(&hdmi.pdev->dev, "vdda");
118*4882a593Smuzhiyun 	if (IS_ERR(reg)) {
119*4882a593Smuzhiyun 		DSSERR("can't get VDDA regulator\n");
120*4882a593Smuzhiyun 		return PTR_ERR(reg);
121*4882a593Smuzhiyun 	}
122*4882a593Smuzhiyun 
123*4882a593Smuzhiyun 	hdmi.vdda_reg = reg;
124*4882a593Smuzhiyun 
125*4882a593Smuzhiyun 	return 0;
126*4882a593Smuzhiyun }
127*4882a593Smuzhiyun 
hdmi_power_on_core(struct omap_dss_device * dssdev)128*4882a593Smuzhiyun static int hdmi_power_on_core(struct omap_dss_device *dssdev)
129*4882a593Smuzhiyun {
130*4882a593Smuzhiyun 	int r;
131*4882a593Smuzhiyun 
132*4882a593Smuzhiyun 	r = regulator_enable(hdmi.vdda_reg);
133*4882a593Smuzhiyun 	if (r)
134*4882a593Smuzhiyun 		return r;
135*4882a593Smuzhiyun 
136*4882a593Smuzhiyun 	r = hdmi_runtime_get();
137*4882a593Smuzhiyun 	if (r)
138*4882a593Smuzhiyun 		goto err_runtime_get;
139*4882a593Smuzhiyun 
140*4882a593Smuzhiyun 	/* Make selection of HDMI in DSS */
141*4882a593Smuzhiyun 	dss_select_hdmi_venc_clk_source(DSS_HDMI_M_PCLK);
142*4882a593Smuzhiyun 
143*4882a593Smuzhiyun 	hdmi.core_enabled = true;
144*4882a593Smuzhiyun 
145*4882a593Smuzhiyun 	return 0;
146*4882a593Smuzhiyun 
147*4882a593Smuzhiyun err_runtime_get:
148*4882a593Smuzhiyun 	regulator_disable(hdmi.vdda_reg);
149*4882a593Smuzhiyun 
150*4882a593Smuzhiyun 	return r;
151*4882a593Smuzhiyun }
152*4882a593Smuzhiyun 
hdmi_power_off_core(struct omap_dss_device * dssdev)153*4882a593Smuzhiyun static void hdmi_power_off_core(struct omap_dss_device *dssdev)
154*4882a593Smuzhiyun {
155*4882a593Smuzhiyun 	hdmi.core_enabled = false;
156*4882a593Smuzhiyun 
157*4882a593Smuzhiyun 	hdmi_runtime_put();
158*4882a593Smuzhiyun 	regulator_disable(hdmi.vdda_reg);
159*4882a593Smuzhiyun }
160*4882a593Smuzhiyun 
hdmi_power_on_full(struct omap_dss_device * dssdev)161*4882a593Smuzhiyun static int hdmi_power_on_full(struct omap_dss_device *dssdev)
162*4882a593Smuzhiyun {
163*4882a593Smuzhiyun 	int r;
164*4882a593Smuzhiyun 	struct omap_video_timings *p;
165*4882a593Smuzhiyun 	struct omap_overlay_manager *mgr = hdmi.output.manager;
166*4882a593Smuzhiyun 	struct dss_pll_clock_info hdmi_cinfo = { 0 };
167*4882a593Smuzhiyun 
168*4882a593Smuzhiyun 	r = hdmi_power_on_core(dssdev);
169*4882a593Smuzhiyun 	if (r)
170*4882a593Smuzhiyun 		return r;
171*4882a593Smuzhiyun 
172*4882a593Smuzhiyun 	p = &hdmi.cfg.timings;
173*4882a593Smuzhiyun 
174*4882a593Smuzhiyun 	DSSDBG("hdmi_power_on x_res= %d y_res = %d\n", p->x_res, p->y_res);
175*4882a593Smuzhiyun 
176*4882a593Smuzhiyun 	hdmi_pll_compute(&hdmi.pll, p->pixelclock, &hdmi_cinfo);
177*4882a593Smuzhiyun 
178*4882a593Smuzhiyun 	/* disable and clear irqs */
179*4882a593Smuzhiyun 	hdmi_wp_clear_irqenable(&hdmi.wp, 0xffffffff);
180*4882a593Smuzhiyun 	hdmi_wp_set_irqstatus(&hdmi.wp,
181*4882a593Smuzhiyun 			hdmi_wp_get_irqstatus(&hdmi.wp));
182*4882a593Smuzhiyun 
183*4882a593Smuzhiyun 	r = dss_pll_enable(&hdmi.pll.pll);
184*4882a593Smuzhiyun 	if (r) {
185*4882a593Smuzhiyun 		DSSERR("Failed to enable PLL\n");
186*4882a593Smuzhiyun 		goto err_pll_enable;
187*4882a593Smuzhiyun 	}
188*4882a593Smuzhiyun 
189*4882a593Smuzhiyun 	r = dss_pll_set_config(&hdmi.pll.pll, &hdmi_cinfo);
190*4882a593Smuzhiyun 	if (r) {
191*4882a593Smuzhiyun 		DSSERR("Failed to configure PLL\n");
192*4882a593Smuzhiyun 		goto err_pll_cfg;
193*4882a593Smuzhiyun 	}
194*4882a593Smuzhiyun 
195*4882a593Smuzhiyun 	r = hdmi_phy_configure(&hdmi.phy, hdmi_cinfo.clkdco,
196*4882a593Smuzhiyun 		hdmi_cinfo.clkout[0]);
197*4882a593Smuzhiyun 	if (r) {
198*4882a593Smuzhiyun 		DSSDBG("Failed to start PHY\n");
199*4882a593Smuzhiyun 		goto err_phy_cfg;
200*4882a593Smuzhiyun 	}
201*4882a593Smuzhiyun 
202*4882a593Smuzhiyun 	r = hdmi_wp_set_phy_pwr(&hdmi.wp, HDMI_PHYPWRCMD_LDOON);
203*4882a593Smuzhiyun 	if (r)
204*4882a593Smuzhiyun 		goto err_phy_pwr;
205*4882a593Smuzhiyun 
206*4882a593Smuzhiyun 	hdmi5_configure(&hdmi.core, &hdmi.wp, &hdmi.cfg);
207*4882a593Smuzhiyun 
208*4882a593Smuzhiyun 	/* bypass TV gamma table */
209*4882a593Smuzhiyun 	dispc_enable_gamma_table(0);
210*4882a593Smuzhiyun 
211*4882a593Smuzhiyun 	/* tv size */
212*4882a593Smuzhiyun 	dss_mgr_set_timings(mgr, p);
213*4882a593Smuzhiyun 
214*4882a593Smuzhiyun 	r = hdmi_wp_video_start(&hdmi.wp);
215*4882a593Smuzhiyun 	if (r)
216*4882a593Smuzhiyun 		goto err_vid_enable;
217*4882a593Smuzhiyun 
218*4882a593Smuzhiyun 	r = dss_mgr_enable(mgr);
219*4882a593Smuzhiyun 	if (r)
220*4882a593Smuzhiyun 		goto err_mgr_enable;
221*4882a593Smuzhiyun 
222*4882a593Smuzhiyun 	hdmi_wp_set_irqenable(&hdmi.wp,
223*4882a593Smuzhiyun 			HDMI_IRQ_LINK_CONNECT | HDMI_IRQ_LINK_DISCONNECT);
224*4882a593Smuzhiyun 
225*4882a593Smuzhiyun 	return 0;
226*4882a593Smuzhiyun 
227*4882a593Smuzhiyun err_mgr_enable:
228*4882a593Smuzhiyun 	hdmi_wp_video_stop(&hdmi.wp);
229*4882a593Smuzhiyun err_vid_enable:
230*4882a593Smuzhiyun 	hdmi_wp_set_phy_pwr(&hdmi.wp, HDMI_PHYPWRCMD_OFF);
231*4882a593Smuzhiyun err_phy_pwr:
232*4882a593Smuzhiyun err_phy_cfg:
233*4882a593Smuzhiyun err_pll_cfg:
234*4882a593Smuzhiyun 	dss_pll_disable(&hdmi.pll.pll);
235*4882a593Smuzhiyun err_pll_enable:
236*4882a593Smuzhiyun 	hdmi_power_off_core(dssdev);
237*4882a593Smuzhiyun 	return -EIO;
238*4882a593Smuzhiyun }
239*4882a593Smuzhiyun 
hdmi_power_off_full(struct omap_dss_device * dssdev)240*4882a593Smuzhiyun static void hdmi_power_off_full(struct omap_dss_device *dssdev)
241*4882a593Smuzhiyun {
242*4882a593Smuzhiyun 	struct omap_overlay_manager *mgr = hdmi.output.manager;
243*4882a593Smuzhiyun 
244*4882a593Smuzhiyun 	hdmi_wp_clear_irqenable(&hdmi.wp, 0xffffffff);
245*4882a593Smuzhiyun 
246*4882a593Smuzhiyun 	dss_mgr_disable(mgr);
247*4882a593Smuzhiyun 
248*4882a593Smuzhiyun 	hdmi_wp_video_stop(&hdmi.wp);
249*4882a593Smuzhiyun 
250*4882a593Smuzhiyun 	hdmi_wp_set_phy_pwr(&hdmi.wp, HDMI_PHYPWRCMD_OFF);
251*4882a593Smuzhiyun 
252*4882a593Smuzhiyun 	dss_pll_disable(&hdmi.pll.pll);
253*4882a593Smuzhiyun 
254*4882a593Smuzhiyun 	hdmi_power_off_core(dssdev);
255*4882a593Smuzhiyun }
256*4882a593Smuzhiyun 
hdmi_display_check_timing(struct omap_dss_device * dssdev,struct omap_video_timings * timings)257*4882a593Smuzhiyun static int hdmi_display_check_timing(struct omap_dss_device *dssdev,
258*4882a593Smuzhiyun 					struct omap_video_timings *timings)
259*4882a593Smuzhiyun {
260*4882a593Smuzhiyun 	struct omap_dss_device *out = &hdmi.output;
261*4882a593Smuzhiyun 
262*4882a593Smuzhiyun 	/* TODO: proper interlace support */
263*4882a593Smuzhiyun 	if (timings->interlace)
264*4882a593Smuzhiyun 		return -EINVAL;
265*4882a593Smuzhiyun 
266*4882a593Smuzhiyun 	if (!dispc_mgr_timings_ok(out->dispc_channel, timings))
267*4882a593Smuzhiyun 		return -EINVAL;
268*4882a593Smuzhiyun 
269*4882a593Smuzhiyun 	return 0;
270*4882a593Smuzhiyun }
271*4882a593Smuzhiyun 
hdmi_display_set_timing(struct omap_dss_device * dssdev,struct omap_video_timings * timings)272*4882a593Smuzhiyun static void hdmi_display_set_timing(struct omap_dss_device *dssdev,
273*4882a593Smuzhiyun 		struct omap_video_timings *timings)
274*4882a593Smuzhiyun {
275*4882a593Smuzhiyun 	mutex_lock(&hdmi.lock);
276*4882a593Smuzhiyun 
277*4882a593Smuzhiyun 	hdmi.cfg.timings = *timings;
278*4882a593Smuzhiyun 
279*4882a593Smuzhiyun 	dispc_set_tv_pclk(timings->pixelclock);
280*4882a593Smuzhiyun 
281*4882a593Smuzhiyun 	mutex_unlock(&hdmi.lock);
282*4882a593Smuzhiyun }
283*4882a593Smuzhiyun 
hdmi_display_get_timings(struct omap_dss_device * dssdev,struct omap_video_timings * timings)284*4882a593Smuzhiyun static void hdmi_display_get_timings(struct omap_dss_device *dssdev,
285*4882a593Smuzhiyun 		struct omap_video_timings *timings)
286*4882a593Smuzhiyun {
287*4882a593Smuzhiyun 	*timings = hdmi.cfg.timings;
288*4882a593Smuzhiyun }
289*4882a593Smuzhiyun 
hdmi_dump_regs(struct seq_file * s)290*4882a593Smuzhiyun static void hdmi_dump_regs(struct seq_file *s)
291*4882a593Smuzhiyun {
292*4882a593Smuzhiyun 	mutex_lock(&hdmi.lock);
293*4882a593Smuzhiyun 
294*4882a593Smuzhiyun 	if (hdmi_runtime_get()) {
295*4882a593Smuzhiyun 		mutex_unlock(&hdmi.lock);
296*4882a593Smuzhiyun 		return;
297*4882a593Smuzhiyun 	}
298*4882a593Smuzhiyun 
299*4882a593Smuzhiyun 	hdmi_wp_dump(&hdmi.wp, s);
300*4882a593Smuzhiyun 	hdmi_pll_dump(&hdmi.pll, s);
301*4882a593Smuzhiyun 	hdmi_phy_dump(&hdmi.phy, s);
302*4882a593Smuzhiyun 	hdmi5_core_dump(&hdmi.core, s);
303*4882a593Smuzhiyun 
304*4882a593Smuzhiyun 	hdmi_runtime_put();
305*4882a593Smuzhiyun 	mutex_unlock(&hdmi.lock);
306*4882a593Smuzhiyun }
307*4882a593Smuzhiyun 
read_edid(u8 * buf,int len)308*4882a593Smuzhiyun static int read_edid(u8 *buf, int len)
309*4882a593Smuzhiyun {
310*4882a593Smuzhiyun 	int r;
311*4882a593Smuzhiyun 	int idlemode;
312*4882a593Smuzhiyun 
313*4882a593Smuzhiyun 	mutex_lock(&hdmi.lock);
314*4882a593Smuzhiyun 
315*4882a593Smuzhiyun 	r = hdmi_runtime_get();
316*4882a593Smuzhiyun 	BUG_ON(r);
317*4882a593Smuzhiyun 
318*4882a593Smuzhiyun 	idlemode = REG_GET(hdmi.wp.base, HDMI_WP_SYSCONFIG, 3, 2);
319*4882a593Smuzhiyun 	/* No-idle mode */
320*4882a593Smuzhiyun 	REG_FLD_MOD(hdmi.wp.base, HDMI_WP_SYSCONFIG, 1, 3, 2);
321*4882a593Smuzhiyun 
322*4882a593Smuzhiyun 	r = hdmi5_read_edid(&hdmi.core,  buf, len);
323*4882a593Smuzhiyun 
324*4882a593Smuzhiyun 	REG_FLD_MOD(hdmi.wp.base, HDMI_WP_SYSCONFIG, idlemode, 3, 2);
325*4882a593Smuzhiyun 
326*4882a593Smuzhiyun 	hdmi_runtime_put();
327*4882a593Smuzhiyun 	mutex_unlock(&hdmi.lock);
328*4882a593Smuzhiyun 
329*4882a593Smuzhiyun 	return r;
330*4882a593Smuzhiyun }
331*4882a593Smuzhiyun 
hdmi_start_audio_stream(struct omap_hdmi * hd)332*4882a593Smuzhiyun static void hdmi_start_audio_stream(struct omap_hdmi *hd)
333*4882a593Smuzhiyun {
334*4882a593Smuzhiyun 	REG_FLD_MOD(hdmi.wp.base, HDMI_WP_SYSCONFIG, 1, 3, 2);
335*4882a593Smuzhiyun 	hdmi_wp_audio_enable(&hd->wp, true);
336*4882a593Smuzhiyun 	hdmi_wp_audio_core_req_enable(&hd->wp, true);
337*4882a593Smuzhiyun }
338*4882a593Smuzhiyun 
hdmi_stop_audio_stream(struct omap_hdmi * hd)339*4882a593Smuzhiyun static void hdmi_stop_audio_stream(struct omap_hdmi *hd)
340*4882a593Smuzhiyun {
341*4882a593Smuzhiyun 	hdmi_wp_audio_core_req_enable(&hd->wp, false);
342*4882a593Smuzhiyun 	hdmi_wp_audio_enable(&hd->wp, false);
343*4882a593Smuzhiyun 	REG_FLD_MOD(hd->wp.base, HDMI_WP_SYSCONFIG, hd->wp_idlemode, 3, 2);
344*4882a593Smuzhiyun }
345*4882a593Smuzhiyun 
hdmi_display_enable(struct omap_dss_device * dssdev)346*4882a593Smuzhiyun static int hdmi_display_enable(struct omap_dss_device *dssdev)
347*4882a593Smuzhiyun {
348*4882a593Smuzhiyun 	struct omap_dss_device *out = &hdmi.output;
349*4882a593Smuzhiyun 	unsigned long flags;
350*4882a593Smuzhiyun 	int r = 0;
351*4882a593Smuzhiyun 
352*4882a593Smuzhiyun 	DSSDBG("ENTER hdmi_display_enable\n");
353*4882a593Smuzhiyun 
354*4882a593Smuzhiyun 	mutex_lock(&hdmi.lock);
355*4882a593Smuzhiyun 
356*4882a593Smuzhiyun 	if (out->manager == NULL) {
357*4882a593Smuzhiyun 		DSSERR("failed to enable display: no output/manager\n");
358*4882a593Smuzhiyun 		r = -ENODEV;
359*4882a593Smuzhiyun 		goto err0;
360*4882a593Smuzhiyun 	}
361*4882a593Smuzhiyun 
362*4882a593Smuzhiyun 	r = hdmi_power_on_full(dssdev);
363*4882a593Smuzhiyun 	if (r) {
364*4882a593Smuzhiyun 		DSSERR("failed to power on device\n");
365*4882a593Smuzhiyun 		goto err0;
366*4882a593Smuzhiyun 	}
367*4882a593Smuzhiyun 
368*4882a593Smuzhiyun 	if (hdmi.audio_configured) {
369*4882a593Smuzhiyun 		r = hdmi5_audio_config(&hdmi.core, &hdmi.wp, &hdmi.audio_config,
370*4882a593Smuzhiyun 				       hdmi.cfg.timings.pixelclock);
371*4882a593Smuzhiyun 		if (r) {
372*4882a593Smuzhiyun 			DSSERR("Error restoring audio configuration: %d", r);
373*4882a593Smuzhiyun 			hdmi.audio_abort_cb(&hdmi.pdev->dev);
374*4882a593Smuzhiyun 			hdmi.audio_configured = false;
375*4882a593Smuzhiyun 		}
376*4882a593Smuzhiyun 	}
377*4882a593Smuzhiyun 
378*4882a593Smuzhiyun 	spin_lock_irqsave(&hdmi.audio_playing_lock, flags);
379*4882a593Smuzhiyun 	if (hdmi.audio_configured && hdmi.audio_playing)
380*4882a593Smuzhiyun 		hdmi_start_audio_stream(&hdmi);
381*4882a593Smuzhiyun 	hdmi.display_enabled = true;
382*4882a593Smuzhiyun 	spin_unlock_irqrestore(&hdmi.audio_playing_lock, flags);
383*4882a593Smuzhiyun 
384*4882a593Smuzhiyun 	mutex_unlock(&hdmi.lock);
385*4882a593Smuzhiyun 	return 0;
386*4882a593Smuzhiyun 
387*4882a593Smuzhiyun err0:
388*4882a593Smuzhiyun 	mutex_unlock(&hdmi.lock);
389*4882a593Smuzhiyun 	return r;
390*4882a593Smuzhiyun }
391*4882a593Smuzhiyun 
hdmi_display_disable(struct omap_dss_device * dssdev)392*4882a593Smuzhiyun static void hdmi_display_disable(struct omap_dss_device *dssdev)
393*4882a593Smuzhiyun {
394*4882a593Smuzhiyun 	unsigned long flags;
395*4882a593Smuzhiyun 
396*4882a593Smuzhiyun 	DSSDBG("Enter hdmi_display_disable\n");
397*4882a593Smuzhiyun 
398*4882a593Smuzhiyun 	mutex_lock(&hdmi.lock);
399*4882a593Smuzhiyun 
400*4882a593Smuzhiyun 	spin_lock_irqsave(&hdmi.audio_playing_lock, flags);
401*4882a593Smuzhiyun 	hdmi_stop_audio_stream(&hdmi);
402*4882a593Smuzhiyun 	hdmi.display_enabled = false;
403*4882a593Smuzhiyun 	spin_unlock_irqrestore(&hdmi.audio_playing_lock, flags);
404*4882a593Smuzhiyun 
405*4882a593Smuzhiyun 	hdmi_power_off_full(dssdev);
406*4882a593Smuzhiyun 
407*4882a593Smuzhiyun 	mutex_unlock(&hdmi.lock);
408*4882a593Smuzhiyun }
409*4882a593Smuzhiyun 
hdmi_core_enable(struct omap_dss_device * dssdev)410*4882a593Smuzhiyun static int hdmi_core_enable(struct omap_dss_device *dssdev)
411*4882a593Smuzhiyun {
412*4882a593Smuzhiyun 	int r = 0;
413*4882a593Smuzhiyun 
414*4882a593Smuzhiyun 	DSSDBG("ENTER omapdss_hdmi_core_enable\n");
415*4882a593Smuzhiyun 
416*4882a593Smuzhiyun 	mutex_lock(&hdmi.lock);
417*4882a593Smuzhiyun 
418*4882a593Smuzhiyun 	r = hdmi_power_on_core(dssdev);
419*4882a593Smuzhiyun 	if (r) {
420*4882a593Smuzhiyun 		DSSERR("failed to power on device\n");
421*4882a593Smuzhiyun 		goto err0;
422*4882a593Smuzhiyun 	}
423*4882a593Smuzhiyun 
424*4882a593Smuzhiyun 	mutex_unlock(&hdmi.lock);
425*4882a593Smuzhiyun 	return 0;
426*4882a593Smuzhiyun 
427*4882a593Smuzhiyun err0:
428*4882a593Smuzhiyun 	mutex_unlock(&hdmi.lock);
429*4882a593Smuzhiyun 	return r;
430*4882a593Smuzhiyun }
431*4882a593Smuzhiyun 
hdmi_core_disable(struct omap_dss_device * dssdev)432*4882a593Smuzhiyun static void hdmi_core_disable(struct omap_dss_device *dssdev)
433*4882a593Smuzhiyun {
434*4882a593Smuzhiyun 	DSSDBG("Enter omapdss_hdmi_core_disable\n");
435*4882a593Smuzhiyun 
436*4882a593Smuzhiyun 	mutex_lock(&hdmi.lock);
437*4882a593Smuzhiyun 
438*4882a593Smuzhiyun 	hdmi_power_off_core(dssdev);
439*4882a593Smuzhiyun 
440*4882a593Smuzhiyun 	mutex_unlock(&hdmi.lock);
441*4882a593Smuzhiyun }
442*4882a593Smuzhiyun 
hdmi_connect(struct omap_dss_device * dssdev,struct omap_dss_device * dst)443*4882a593Smuzhiyun static int hdmi_connect(struct omap_dss_device *dssdev,
444*4882a593Smuzhiyun 		struct omap_dss_device *dst)
445*4882a593Smuzhiyun {
446*4882a593Smuzhiyun 	struct omap_overlay_manager *mgr;
447*4882a593Smuzhiyun 	int r;
448*4882a593Smuzhiyun 
449*4882a593Smuzhiyun 	r = hdmi_init_regulator();
450*4882a593Smuzhiyun 	if (r)
451*4882a593Smuzhiyun 		return r;
452*4882a593Smuzhiyun 
453*4882a593Smuzhiyun 	mgr = omap_dss_get_overlay_manager(dssdev->dispc_channel);
454*4882a593Smuzhiyun 	if (!mgr)
455*4882a593Smuzhiyun 		return -ENODEV;
456*4882a593Smuzhiyun 
457*4882a593Smuzhiyun 	r = dss_mgr_connect(mgr, dssdev);
458*4882a593Smuzhiyun 	if (r)
459*4882a593Smuzhiyun 		return r;
460*4882a593Smuzhiyun 
461*4882a593Smuzhiyun 	r = omapdss_output_set_device(dssdev, dst);
462*4882a593Smuzhiyun 	if (r) {
463*4882a593Smuzhiyun 		DSSERR("failed to connect output to new device: %s\n",
464*4882a593Smuzhiyun 				dst->name);
465*4882a593Smuzhiyun 		dss_mgr_disconnect(mgr, dssdev);
466*4882a593Smuzhiyun 		return r;
467*4882a593Smuzhiyun 	}
468*4882a593Smuzhiyun 
469*4882a593Smuzhiyun 	return 0;
470*4882a593Smuzhiyun }
471*4882a593Smuzhiyun 
hdmi_disconnect(struct omap_dss_device * dssdev,struct omap_dss_device * dst)472*4882a593Smuzhiyun static void hdmi_disconnect(struct omap_dss_device *dssdev,
473*4882a593Smuzhiyun 		struct omap_dss_device *dst)
474*4882a593Smuzhiyun {
475*4882a593Smuzhiyun 	WARN_ON(dst != dssdev->dst);
476*4882a593Smuzhiyun 
477*4882a593Smuzhiyun 	if (dst != dssdev->dst)
478*4882a593Smuzhiyun 		return;
479*4882a593Smuzhiyun 
480*4882a593Smuzhiyun 	omapdss_output_unset_device(dssdev);
481*4882a593Smuzhiyun 
482*4882a593Smuzhiyun 	if (dssdev->manager)
483*4882a593Smuzhiyun 		dss_mgr_disconnect(dssdev->manager, dssdev);
484*4882a593Smuzhiyun }
485*4882a593Smuzhiyun 
hdmi_read_edid(struct omap_dss_device * dssdev,u8 * edid,int len)486*4882a593Smuzhiyun static int hdmi_read_edid(struct omap_dss_device *dssdev,
487*4882a593Smuzhiyun 		u8 *edid, int len)
488*4882a593Smuzhiyun {
489*4882a593Smuzhiyun 	bool need_enable;
490*4882a593Smuzhiyun 	int r;
491*4882a593Smuzhiyun 
492*4882a593Smuzhiyun 	need_enable = hdmi.core_enabled == false;
493*4882a593Smuzhiyun 
494*4882a593Smuzhiyun 	if (need_enable) {
495*4882a593Smuzhiyun 		r = hdmi_core_enable(dssdev);
496*4882a593Smuzhiyun 		if (r)
497*4882a593Smuzhiyun 			return r;
498*4882a593Smuzhiyun 	}
499*4882a593Smuzhiyun 
500*4882a593Smuzhiyun 	r = read_edid(edid, len);
501*4882a593Smuzhiyun 
502*4882a593Smuzhiyun 	if (need_enable)
503*4882a593Smuzhiyun 		hdmi_core_disable(dssdev);
504*4882a593Smuzhiyun 
505*4882a593Smuzhiyun 	return r;
506*4882a593Smuzhiyun }
507*4882a593Smuzhiyun 
hdmi_set_infoframe(struct omap_dss_device * dssdev,const struct hdmi_avi_infoframe * avi)508*4882a593Smuzhiyun static int hdmi_set_infoframe(struct omap_dss_device *dssdev,
509*4882a593Smuzhiyun 		const struct hdmi_avi_infoframe *avi)
510*4882a593Smuzhiyun {
511*4882a593Smuzhiyun 	hdmi.cfg.infoframe = *avi;
512*4882a593Smuzhiyun 	return 0;
513*4882a593Smuzhiyun }
514*4882a593Smuzhiyun 
hdmi_set_hdmi_mode(struct omap_dss_device * dssdev,bool hdmi_mode)515*4882a593Smuzhiyun static int hdmi_set_hdmi_mode(struct omap_dss_device *dssdev,
516*4882a593Smuzhiyun 		bool hdmi_mode)
517*4882a593Smuzhiyun {
518*4882a593Smuzhiyun 	hdmi.cfg.hdmi_dvi_mode = hdmi_mode ? HDMI_HDMI : HDMI_DVI;
519*4882a593Smuzhiyun 	return 0;
520*4882a593Smuzhiyun }
521*4882a593Smuzhiyun 
522*4882a593Smuzhiyun static const struct omapdss_hdmi_ops hdmi_ops = {
523*4882a593Smuzhiyun 	.connect		= hdmi_connect,
524*4882a593Smuzhiyun 	.disconnect		= hdmi_disconnect,
525*4882a593Smuzhiyun 
526*4882a593Smuzhiyun 	.enable			= hdmi_display_enable,
527*4882a593Smuzhiyun 	.disable		= hdmi_display_disable,
528*4882a593Smuzhiyun 
529*4882a593Smuzhiyun 	.check_timings		= hdmi_display_check_timing,
530*4882a593Smuzhiyun 	.set_timings		= hdmi_display_set_timing,
531*4882a593Smuzhiyun 	.get_timings		= hdmi_display_get_timings,
532*4882a593Smuzhiyun 
533*4882a593Smuzhiyun 	.read_edid		= hdmi_read_edid,
534*4882a593Smuzhiyun 	.set_infoframe		= hdmi_set_infoframe,
535*4882a593Smuzhiyun 	.set_hdmi_mode		= hdmi_set_hdmi_mode,
536*4882a593Smuzhiyun };
537*4882a593Smuzhiyun 
hdmi_init_output(struct platform_device * pdev)538*4882a593Smuzhiyun static void hdmi_init_output(struct platform_device *pdev)
539*4882a593Smuzhiyun {
540*4882a593Smuzhiyun 	struct omap_dss_device *out = &hdmi.output;
541*4882a593Smuzhiyun 
542*4882a593Smuzhiyun 	out->dev = &pdev->dev;
543*4882a593Smuzhiyun 	out->id = OMAP_DSS_OUTPUT_HDMI;
544*4882a593Smuzhiyun 	out->output_type = OMAP_DISPLAY_TYPE_HDMI;
545*4882a593Smuzhiyun 	out->name = "hdmi.0";
546*4882a593Smuzhiyun 	out->dispc_channel = OMAP_DSS_CHANNEL_DIGIT;
547*4882a593Smuzhiyun 	out->ops.hdmi = &hdmi_ops;
548*4882a593Smuzhiyun 	out->owner = THIS_MODULE;
549*4882a593Smuzhiyun 
550*4882a593Smuzhiyun 	omapdss_register_output(out);
551*4882a593Smuzhiyun }
552*4882a593Smuzhiyun 
hdmi_uninit_output(struct platform_device * pdev)553*4882a593Smuzhiyun static void hdmi_uninit_output(struct platform_device *pdev)
554*4882a593Smuzhiyun {
555*4882a593Smuzhiyun 	struct omap_dss_device *out = &hdmi.output;
556*4882a593Smuzhiyun 
557*4882a593Smuzhiyun 	omapdss_unregister_output(out);
558*4882a593Smuzhiyun }
559*4882a593Smuzhiyun 
hdmi_probe_of(struct platform_device * pdev)560*4882a593Smuzhiyun static int hdmi_probe_of(struct platform_device *pdev)
561*4882a593Smuzhiyun {
562*4882a593Smuzhiyun 	struct device_node *node = pdev->dev.of_node;
563*4882a593Smuzhiyun 	struct device_node *ep;
564*4882a593Smuzhiyun 	int r;
565*4882a593Smuzhiyun 
566*4882a593Smuzhiyun 	ep = omapdss_of_get_first_endpoint(node);
567*4882a593Smuzhiyun 	if (!ep)
568*4882a593Smuzhiyun 		return 0;
569*4882a593Smuzhiyun 
570*4882a593Smuzhiyun 	r = hdmi_parse_lanes_of(pdev, ep, &hdmi.phy);
571*4882a593Smuzhiyun 	if (r)
572*4882a593Smuzhiyun 		goto err;
573*4882a593Smuzhiyun 
574*4882a593Smuzhiyun 	of_node_put(ep);
575*4882a593Smuzhiyun 	return 0;
576*4882a593Smuzhiyun 
577*4882a593Smuzhiyun err:
578*4882a593Smuzhiyun 	of_node_put(ep);
579*4882a593Smuzhiyun 	return r;
580*4882a593Smuzhiyun }
581*4882a593Smuzhiyun 
582*4882a593Smuzhiyun /* Audio callbacks */
hdmi_audio_startup(struct device * dev,void (* abort_cb)(struct device * dev))583*4882a593Smuzhiyun static int hdmi_audio_startup(struct device *dev,
584*4882a593Smuzhiyun 			      void (*abort_cb)(struct device *dev))
585*4882a593Smuzhiyun {
586*4882a593Smuzhiyun 	struct omap_hdmi *hd = dev_get_drvdata(dev);
587*4882a593Smuzhiyun 	int ret = 0;
588*4882a593Smuzhiyun 
589*4882a593Smuzhiyun 	mutex_lock(&hd->lock);
590*4882a593Smuzhiyun 
591*4882a593Smuzhiyun 	if (!hdmi_mode_has_audio(&hd->cfg) || !hd->display_enabled) {
592*4882a593Smuzhiyun 		ret = -EPERM;
593*4882a593Smuzhiyun 		goto out;
594*4882a593Smuzhiyun 	}
595*4882a593Smuzhiyun 
596*4882a593Smuzhiyun 	hd->audio_abort_cb = abort_cb;
597*4882a593Smuzhiyun 
598*4882a593Smuzhiyun out:
599*4882a593Smuzhiyun 	mutex_unlock(&hd->lock);
600*4882a593Smuzhiyun 
601*4882a593Smuzhiyun 	return ret;
602*4882a593Smuzhiyun }
603*4882a593Smuzhiyun 
hdmi_audio_shutdown(struct device * dev)604*4882a593Smuzhiyun static int hdmi_audio_shutdown(struct device *dev)
605*4882a593Smuzhiyun {
606*4882a593Smuzhiyun 	struct omap_hdmi *hd = dev_get_drvdata(dev);
607*4882a593Smuzhiyun 
608*4882a593Smuzhiyun 	mutex_lock(&hd->lock);
609*4882a593Smuzhiyun 	hd->audio_abort_cb = NULL;
610*4882a593Smuzhiyun 	hd->audio_configured = false;
611*4882a593Smuzhiyun 	hd->audio_playing = false;
612*4882a593Smuzhiyun 	mutex_unlock(&hd->lock);
613*4882a593Smuzhiyun 
614*4882a593Smuzhiyun 	return 0;
615*4882a593Smuzhiyun }
616*4882a593Smuzhiyun 
hdmi_audio_start(struct device * dev)617*4882a593Smuzhiyun static int hdmi_audio_start(struct device *dev)
618*4882a593Smuzhiyun {
619*4882a593Smuzhiyun 	struct omap_hdmi *hd = dev_get_drvdata(dev);
620*4882a593Smuzhiyun 	unsigned long flags;
621*4882a593Smuzhiyun 
622*4882a593Smuzhiyun 	WARN_ON(!hdmi_mode_has_audio(&hd->cfg));
623*4882a593Smuzhiyun 
624*4882a593Smuzhiyun 	spin_lock_irqsave(&hd->audio_playing_lock, flags);
625*4882a593Smuzhiyun 
626*4882a593Smuzhiyun 	if (hd->display_enabled)
627*4882a593Smuzhiyun 		hdmi_start_audio_stream(hd);
628*4882a593Smuzhiyun 	hd->audio_playing = true;
629*4882a593Smuzhiyun 
630*4882a593Smuzhiyun 	spin_unlock_irqrestore(&hd->audio_playing_lock, flags);
631*4882a593Smuzhiyun 	return 0;
632*4882a593Smuzhiyun }
633*4882a593Smuzhiyun 
hdmi_audio_stop(struct device * dev)634*4882a593Smuzhiyun static void hdmi_audio_stop(struct device *dev)
635*4882a593Smuzhiyun {
636*4882a593Smuzhiyun 	struct omap_hdmi *hd = dev_get_drvdata(dev);
637*4882a593Smuzhiyun 	unsigned long flags;
638*4882a593Smuzhiyun 
639*4882a593Smuzhiyun 	WARN_ON(!hdmi_mode_has_audio(&hd->cfg));
640*4882a593Smuzhiyun 
641*4882a593Smuzhiyun 	spin_lock_irqsave(&hd->audio_playing_lock, flags);
642*4882a593Smuzhiyun 
643*4882a593Smuzhiyun 	if (hd->display_enabled)
644*4882a593Smuzhiyun 		hdmi_stop_audio_stream(hd);
645*4882a593Smuzhiyun 	hd->audio_playing = false;
646*4882a593Smuzhiyun 
647*4882a593Smuzhiyun 	spin_unlock_irqrestore(&hd->audio_playing_lock, flags);
648*4882a593Smuzhiyun }
649*4882a593Smuzhiyun 
hdmi_audio_config(struct device * dev,struct omap_dss_audio * dss_audio)650*4882a593Smuzhiyun static int hdmi_audio_config(struct device *dev,
651*4882a593Smuzhiyun 			     struct omap_dss_audio *dss_audio)
652*4882a593Smuzhiyun {
653*4882a593Smuzhiyun 	struct omap_hdmi *hd = dev_get_drvdata(dev);
654*4882a593Smuzhiyun 	int ret;
655*4882a593Smuzhiyun 
656*4882a593Smuzhiyun 	mutex_lock(&hd->lock);
657*4882a593Smuzhiyun 
658*4882a593Smuzhiyun 	if (!hdmi_mode_has_audio(&hd->cfg) || !hd->display_enabled) {
659*4882a593Smuzhiyun 		ret = -EPERM;
660*4882a593Smuzhiyun 		goto out;
661*4882a593Smuzhiyun 	}
662*4882a593Smuzhiyun 
663*4882a593Smuzhiyun 	ret = hdmi5_audio_config(&hd->core, &hd->wp, dss_audio,
664*4882a593Smuzhiyun 				 hd->cfg.timings.pixelclock);
665*4882a593Smuzhiyun 
666*4882a593Smuzhiyun 	if (!ret) {
667*4882a593Smuzhiyun 		hd->audio_configured = true;
668*4882a593Smuzhiyun 		hd->audio_config = *dss_audio;
669*4882a593Smuzhiyun 	}
670*4882a593Smuzhiyun out:
671*4882a593Smuzhiyun 	mutex_unlock(&hd->lock);
672*4882a593Smuzhiyun 
673*4882a593Smuzhiyun 	return ret;
674*4882a593Smuzhiyun }
675*4882a593Smuzhiyun 
676*4882a593Smuzhiyun static const struct omap_hdmi_audio_ops hdmi_audio_ops = {
677*4882a593Smuzhiyun 	.audio_startup = hdmi_audio_startup,
678*4882a593Smuzhiyun 	.audio_shutdown = hdmi_audio_shutdown,
679*4882a593Smuzhiyun 	.audio_start = hdmi_audio_start,
680*4882a593Smuzhiyun 	.audio_stop = hdmi_audio_stop,
681*4882a593Smuzhiyun 	.audio_config = hdmi_audio_config,
682*4882a593Smuzhiyun };
683*4882a593Smuzhiyun 
hdmi_audio_register(struct device * dev)684*4882a593Smuzhiyun static int hdmi_audio_register(struct device *dev)
685*4882a593Smuzhiyun {
686*4882a593Smuzhiyun 	struct omap_hdmi_audio_pdata pdata = {
687*4882a593Smuzhiyun 		.dev = dev,
688*4882a593Smuzhiyun 		.version = 5,
689*4882a593Smuzhiyun 		.audio_dma_addr = hdmi_wp_get_audio_dma_addr(&hdmi.wp),
690*4882a593Smuzhiyun 		.ops = &hdmi_audio_ops,
691*4882a593Smuzhiyun 	};
692*4882a593Smuzhiyun 
693*4882a593Smuzhiyun 	hdmi.audio_pdev = platform_device_register_data(
694*4882a593Smuzhiyun 		dev, "omap-hdmi-audio", PLATFORM_DEVID_AUTO,
695*4882a593Smuzhiyun 		&pdata, sizeof(pdata));
696*4882a593Smuzhiyun 
697*4882a593Smuzhiyun 	if (IS_ERR(hdmi.audio_pdev))
698*4882a593Smuzhiyun 		return PTR_ERR(hdmi.audio_pdev);
699*4882a593Smuzhiyun 
700*4882a593Smuzhiyun 	hdmi_runtime_get();
701*4882a593Smuzhiyun 	hdmi.wp_idlemode =
702*4882a593Smuzhiyun 		REG_GET(hdmi.wp.base, HDMI_WP_SYSCONFIG, 3, 2);
703*4882a593Smuzhiyun 	hdmi_runtime_put();
704*4882a593Smuzhiyun 
705*4882a593Smuzhiyun 	return 0;
706*4882a593Smuzhiyun }
707*4882a593Smuzhiyun 
708*4882a593Smuzhiyun /* HDMI HW IP initialisation */
hdmi5_bind(struct device * dev,struct device * master,void * data)709*4882a593Smuzhiyun static int hdmi5_bind(struct device *dev, struct device *master, void *data)
710*4882a593Smuzhiyun {
711*4882a593Smuzhiyun 	struct platform_device *pdev = to_platform_device(dev);
712*4882a593Smuzhiyun 	int r;
713*4882a593Smuzhiyun 	int irq;
714*4882a593Smuzhiyun 
715*4882a593Smuzhiyun 	hdmi.pdev = pdev;
716*4882a593Smuzhiyun 	dev_set_drvdata(&pdev->dev, &hdmi);
717*4882a593Smuzhiyun 
718*4882a593Smuzhiyun 	mutex_init(&hdmi.lock);
719*4882a593Smuzhiyun 	spin_lock_init(&hdmi.audio_playing_lock);
720*4882a593Smuzhiyun 
721*4882a593Smuzhiyun 	if (pdev->dev.of_node) {
722*4882a593Smuzhiyun 		r = hdmi_probe_of(pdev);
723*4882a593Smuzhiyun 		if (r)
724*4882a593Smuzhiyun 			return r;
725*4882a593Smuzhiyun 	}
726*4882a593Smuzhiyun 
727*4882a593Smuzhiyun 	r = hdmi_wp_init(pdev, &hdmi.wp);
728*4882a593Smuzhiyun 	if (r)
729*4882a593Smuzhiyun 		return r;
730*4882a593Smuzhiyun 
731*4882a593Smuzhiyun 	r = hdmi_pll_init(pdev, &hdmi.pll, &hdmi.wp);
732*4882a593Smuzhiyun 	if (r)
733*4882a593Smuzhiyun 		return r;
734*4882a593Smuzhiyun 
735*4882a593Smuzhiyun 	r = hdmi_phy_init(pdev, &hdmi.phy);
736*4882a593Smuzhiyun 	if (r)
737*4882a593Smuzhiyun 		goto err;
738*4882a593Smuzhiyun 
739*4882a593Smuzhiyun 	r = hdmi5_core_init(pdev, &hdmi.core);
740*4882a593Smuzhiyun 	if (r)
741*4882a593Smuzhiyun 		goto err;
742*4882a593Smuzhiyun 
743*4882a593Smuzhiyun 	irq = platform_get_irq(pdev, 0);
744*4882a593Smuzhiyun 	if (irq < 0) {
745*4882a593Smuzhiyun 		DSSERR("platform_get_irq failed\n");
746*4882a593Smuzhiyun 		r = -ENODEV;
747*4882a593Smuzhiyun 		goto err;
748*4882a593Smuzhiyun 	}
749*4882a593Smuzhiyun 
750*4882a593Smuzhiyun 	r = devm_request_threaded_irq(&pdev->dev, irq,
751*4882a593Smuzhiyun 			NULL, hdmi_irq_handler,
752*4882a593Smuzhiyun 			IRQF_ONESHOT, "OMAP HDMI", &hdmi.wp);
753*4882a593Smuzhiyun 	if (r) {
754*4882a593Smuzhiyun 		DSSERR("HDMI IRQ request failed\n");
755*4882a593Smuzhiyun 		goto err;
756*4882a593Smuzhiyun 	}
757*4882a593Smuzhiyun 
758*4882a593Smuzhiyun 	pm_runtime_enable(&pdev->dev);
759*4882a593Smuzhiyun 
760*4882a593Smuzhiyun 	hdmi_init_output(pdev);
761*4882a593Smuzhiyun 
762*4882a593Smuzhiyun 	r = hdmi_audio_register(&pdev->dev);
763*4882a593Smuzhiyun 	if (r) {
764*4882a593Smuzhiyun 		DSSERR("Registering HDMI audio failed %d\n", r);
765*4882a593Smuzhiyun 		hdmi_uninit_output(pdev);
766*4882a593Smuzhiyun 		pm_runtime_disable(&pdev->dev);
767*4882a593Smuzhiyun 		return r;
768*4882a593Smuzhiyun 	}
769*4882a593Smuzhiyun 
770*4882a593Smuzhiyun 	dss_debugfs_create_file("hdmi", hdmi_dump_regs);
771*4882a593Smuzhiyun 
772*4882a593Smuzhiyun 	return 0;
773*4882a593Smuzhiyun err:
774*4882a593Smuzhiyun 	hdmi_pll_uninit(&hdmi.pll);
775*4882a593Smuzhiyun 	return r;
776*4882a593Smuzhiyun }
777*4882a593Smuzhiyun 
hdmi5_unbind(struct device * dev,struct device * master,void * data)778*4882a593Smuzhiyun static void hdmi5_unbind(struct device *dev, struct device *master, void *data)
779*4882a593Smuzhiyun {
780*4882a593Smuzhiyun 	struct platform_device *pdev = to_platform_device(dev);
781*4882a593Smuzhiyun 
782*4882a593Smuzhiyun 	if (hdmi.audio_pdev)
783*4882a593Smuzhiyun 		platform_device_unregister(hdmi.audio_pdev);
784*4882a593Smuzhiyun 
785*4882a593Smuzhiyun 	hdmi_uninit_output(pdev);
786*4882a593Smuzhiyun 
787*4882a593Smuzhiyun 	hdmi_pll_uninit(&hdmi.pll);
788*4882a593Smuzhiyun 
789*4882a593Smuzhiyun 	pm_runtime_disable(&pdev->dev);
790*4882a593Smuzhiyun }
791*4882a593Smuzhiyun 
792*4882a593Smuzhiyun static const struct component_ops hdmi5_component_ops = {
793*4882a593Smuzhiyun 	.bind	= hdmi5_bind,
794*4882a593Smuzhiyun 	.unbind	= hdmi5_unbind,
795*4882a593Smuzhiyun };
796*4882a593Smuzhiyun 
hdmi5_probe(struct platform_device * pdev)797*4882a593Smuzhiyun static int hdmi5_probe(struct platform_device *pdev)
798*4882a593Smuzhiyun {
799*4882a593Smuzhiyun 	return component_add(&pdev->dev, &hdmi5_component_ops);
800*4882a593Smuzhiyun }
801*4882a593Smuzhiyun 
hdmi5_remove(struct platform_device * pdev)802*4882a593Smuzhiyun static int hdmi5_remove(struct platform_device *pdev)
803*4882a593Smuzhiyun {
804*4882a593Smuzhiyun 	component_del(&pdev->dev, &hdmi5_component_ops);
805*4882a593Smuzhiyun 	return 0;
806*4882a593Smuzhiyun }
807*4882a593Smuzhiyun 
hdmi_runtime_suspend(struct device * dev)808*4882a593Smuzhiyun static int hdmi_runtime_suspend(struct device *dev)
809*4882a593Smuzhiyun {
810*4882a593Smuzhiyun 	dispc_runtime_put();
811*4882a593Smuzhiyun 
812*4882a593Smuzhiyun 	return 0;
813*4882a593Smuzhiyun }
814*4882a593Smuzhiyun 
hdmi_runtime_resume(struct device * dev)815*4882a593Smuzhiyun static int hdmi_runtime_resume(struct device *dev)
816*4882a593Smuzhiyun {
817*4882a593Smuzhiyun 	int r;
818*4882a593Smuzhiyun 
819*4882a593Smuzhiyun 	r = dispc_runtime_get();
820*4882a593Smuzhiyun 	if (r < 0)
821*4882a593Smuzhiyun 		return r;
822*4882a593Smuzhiyun 
823*4882a593Smuzhiyun 	return 0;
824*4882a593Smuzhiyun }
825*4882a593Smuzhiyun 
826*4882a593Smuzhiyun static const struct dev_pm_ops hdmi_pm_ops = {
827*4882a593Smuzhiyun 	.runtime_suspend = hdmi_runtime_suspend,
828*4882a593Smuzhiyun 	.runtime_resume = hdmi_runtime_resume,
829*4882a593Smuzhiyun };
830*4882a593Smuzhiyun 
831*4882a593Smuzhiyun static const struct of_device_id hdmi_of_match[] = {
832*4882a593Smuzhiyun 	{ .compatible = "ti,omap5-hdmi", },
833*4882a593Smuzhiyun 	{ .compatible = "ti,dra7-hdmi", },
834*4882a593Smuzhiyun 	{},
835*4882a593Smuzhiyun };
836*4882a593Smuzhiyun 
837*4882a593Smuzhiyun static struct platform_driver omapdss_hdmihw_driver = {
838*4882a593Smuzhiyun 	.probe		= hdmi5_probe,
839*4882a593Smuzhiyun 	.remove		= hdmi5_remove,
840*4882a593Smuzhiyun 	.driver         = {
841*4882a593Smuzhiyun 		.name   = "omapdss_hdmi5",
842*4882a593Smuzhiyun 		.pm	= &hdmi_pm_ops,
843*4882a593Smuzhiyun 		.of_match_table = hdmi_of_match,
844*4882a593Smuzhiyun 		.suppress_bind_attrs = true,
845*4882a593Smuzhiyun 	},
846*4882a593Smuzhiyun };
847*4882a593Smuzhiyun 
hdmi5_init_platform_driver(void)848*4882a593Smuzhiyun int __init hdmi5_init_platform_driver(void)
849*4882a593Smuzhiyun {
850*4882a593Smuzhiyun 	return platform_driver_register(&omapdss_hdmihw_driver);
851*4882a593Smuzhiyun }
852*4882a593Smuzhiyun 
hdmi5_uninit_platform_driver(void)853*4882a593Smuzhiyun void hdmi5_uninit_platform_driver(void)
854*4882a593Smuzhiyun {
855*4882a593Smuzhiyun 	platform_driver_unregister(&omapdss_hdmihw_driver);
856*4882a593Smuzhiyun }
857