1*4882a593Smuzhiyun# SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyunconfig FB_OMAP2_DSS_INIT 3*4882a593Smuzhiyun bool 4*4882a593Smuzhiyun 5*4882a593Smuzhiyunconfig FB_OMAP2_DSS 6*4882a593Smuzhiyun tristate 7*4882a593Smuzhiyun select VIDEOMODE_HELPERS 8*4882a593Smuzhiyun select FB_OMAP2_DSS_INIT 9*4882a593Smuzhiyun select HDMI 10*4882a593Smuzhiyun 11*4882a593Smuzhiyunconfig FB_OMAP2_DSS_DEBUG 12*4882a593Smuzhiyun bool "Debug support" 13*4882a593Smuzhiyun help 14*4882a593Smuzhiyun This enables printing of debug messages. Alternatively, debug messages 15*4882a593Smuzhiyun can also be enabled by setting CONFIG_DYNAMIC_DEBUG and then setting 16*4882a593Smuzhiyun appropriate flags in <debugfs>/dynamic_debug/control. 17*4882a593Smuzhiyun 18*4882a593Smuzhiyunconfig FB_OMAP2_DSS_DEBUGFS 19*4882a593Smuzhiyun bool "Debugfs filesystem support" 20*4882a593Smuzhiyun depends on DEBUG_FS 21*4882a593Smuzhiyun help 22*4882a593Smuzhiyun This enables debugfs for OMAPDSS at <debugfs>/omapdss. This enables 23*4882a593Smuzhiyun querying about clock configuration and register configuration of dss, 24*4882a593Smuzhiyun dispc, dsi, hdmi and rfbi. 25*4882a593Smuzhiyun 26*4882a593Smuzhiyunconfig FB_OMAP2_DSS_COLLECT_IRQ_STATS 27*4882a593Smuzhiyun bool "Collect DSS IRQ statistics" 28*4882a593Smuzhiyun depends on FB_OMAP2_DSS_DEBUGFS 29*4882a593Smuzhiyun help 30*4882a593Smuzhiyun Collect DSS IRQ statistics, printable via debugfs. 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun The statistics can be found from 33*4882a593Smuzhiyun <debugfs>/omapdss/dispc_irq for DISPC interrupts, and 34*4882a593Smuzhiyun <debugfs>/omapdss/dsi_irq for DSI interrupts. 35*4882a593Smuzhiyun 36*4882a593Smuzhiyunconfig FB_OMAP2_DSS_DPI 37*4882a593Smuzhiyun bool "DPI support" 38*4882a593Smuzhiyun default y 39*4882a593Smuzhiyun help 40*4882a593Smuzhiyun DPI Interface. This is the Parallel Display Interface. 41*4882a593Smuzhiyun 42*4882a593Smuzhiyunconfig FB_OMAP2_DSS_VENC 43*4882a593Smuzhiyun bool "VENC support" 44*4882a593Smuzhiyun default y 45*4882a593Smuzhiyun help 46*4882a593Smuzhiyun OMAP Video Encoder support for S-Video and composite TV-out. 47*4882a593Smuzhiyun 48*4882a593Smuzhiyunconfig FB_OMAP2_DSS_HDMI_COMMON 49*4882a593Smuzhiyun bool 50*4882a593Smuzhiyun 51*4882a593Smuzhiyunconfig FB_OMAP4_DSS_HDMI 52*4882a593Smuzhiyun bool "HDMI support for OMAP4" 53*4882a593Smuzhiyun default y 54*4882a593Smuzhiyun select FB_OMAP2_DSS_HDMI_COMMON 55*4882a593Smuzhiyun help 56*4882a593Smuzhiyun HDMI support for OMAP4 based SoCs. 57*4882a593Smuzhiyun 58*4882a593Smuzhiyunconfig FB_OMAP5_DSS_HDMI 59*4882a593Smuzhiyun bool "HDMI support for OMAP5" 60*4882a593Smuzhiyun select FB_OMAP2_DSS_HDMI_COMMON 61*4882a593Smuzhiyun help 62*4882a593Smuzhiyun HDMI Interface for OMAP5 and similar cores. This adds the High 63*4882a593Smuzhiyun Definition Multimedia Interface. See https://www.hdmi.org/ for HDMI 64*4882a593Smuzhiyun specification. 65*4882a593Smuzhiyun 66*4882a593Smuzhiyunconfig FB_OMAP2_DSS_SDI 67*4882a593Smuzhiyun bool "SDI support" 68*4882a593Smuzhiyun help 69*4882a593Smuzhiyun SDI (Serial Display Interface) support. 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun SDI is a high speed one-way display serial bus between the host 72*4882a593Smuzhiyun processor and a display. 73*4882a593Smuzhiyun 74*4882a593Smuzhiyunconfig FB_OMAP2_DSS_DSI 75*4882a593Smuzhiyun bool "DSI support" 76*4882a593Smuzhiyun help 77*4882a593Smuzhiyun MIPI DSI (Display Serial Interface) support. 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun DSI is a high speed half-duplex serial interface between the host 80*4882a593Smuzhiyun processor and a peripheral, such as a display or a framebuffer chip. 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun See https://www.mipi.org/ for DSI specifications. 83*4882a593Smuzhiyun 84*4882a593Smuzhiyunconfig FB_OMAP2_DSS_MIN_FCK_PER_PCK 85*4882a593Smuzhiyun int "Minimum FCK/PCK ratio (for scaling)" 86*4882a593Smuzhiyun range 0 32 87*4882a593Smuzhiyun default 0 88*4882a593Smuzhiyun help 89*4882a593Smuzhiyun This can be used to adjust the minimum FCK/PCK ratio. 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun With this you can make sure that DISPC FCK is at least 92*4882a593Smuzhiyun n x PCK. Video plane scaling requires higher FCK than 93*4882a593Smuzhiyun normally. 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun If this is set to 0, there's no extra constraint on the 96*4882a593Smuzhiyun DISPC FCK. However, the FCK will at minimum be 97*4882a593Smuzhiyun 2xPCK (if active matrix) or 3xPCK (if passive matrix). 98*4882a593Smuzhiyun 99*4882a593Smuzhiyun Max FCK is 173MHz, so this doesn't work if your PCK 100*4882a593Smuzhiyun is very high. 101*4882a593Smuzhiyun 102*4882a593Smuzhiyunconfig FB_OMAP2_DSS_SLEEP_AFTER_VENC_RESET 103*4882a593Smuzhiyun bool "Sleep 20ms after VENC reset" 104*4882a593Smuzhiyun default y 105*4882a593Smuzhiyun help 106*4882a593Smuzhiyun There is a 20ms sleep after VENC reset which seemed to fix the 107*4882a593Smuzhiyun reset. The reason for the bug is unclear, and it's also unclear 108*4882a593Smuzhiyun on what platforms this happens. 109*4882a593Smuzhiyun 110*4882a593Smuzhiyun This option enables the sleep, and is enabled by default. You can 111*4882a593Smuzhiyun disable the sleep if it doesn't cause problems on your platform. 112