xref: /OK3568_Linux_fs/kernel/drivers/video/fbdev/omap2/omapfb/displays/panel-nec-nl8048hl11.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * NEC NL8048HL11 Panel driver
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Copyright (C) 2010 Texas Instruments Inc.
6*4882a593Smuzhiyun  * Author: Erik Gilling <konkers@android.com>
7*4882a593Smuzhiyun  * Converted to new DSS device model: Tomi Valkeinen <tomi.valkeinen@ti.com>
8*4882a593Smuzhiyun  */
9*4882a593Smuzhiyun 
10*4882a593Smuzhiyun #include <linux/module.h>
11*4882a593Smuzhiyun #include <linux/delay.h>
12*4882a593Smuzhiyun #include <linux/spi/spi.h>
13*4882a593Smuzhiyun #include <linux/fb.h>
14*4882a593Smuzhiyun #include <linux/gpio.h>
15*4882a593Smuzhiyun #include <linux/of_gpio.h>
16*4882a593Smuzhiyun 
17*4882a593Smuzhiyun #include <video/omapfb_dss.h>
18*4882a593Smuzhiyun 
19*4882a593Smuzhiyun struct panel_drv_data {
20*4882a593Smuzhiyun 	struct omap_dss_device	dssdev;
21*4882a593Smuzhiyun 	struct omap_dss_device *in;
22*4882a593Smuzhiyun 
23*4882a593Smuzhiyun 	struct omap_video_timings videomode;
24*4882a593Smuzhiyun 
25*4882a593Smuzhiyun 	int data_lines;
26*4882a593Smuzhiyun 
27*4882a593Smuzhiyun 	int res_gpio;
28*4882a593Smuzhiyun 	int qvga_gpio;
29*4882a593Smuzhiyun 
30*4882a593Smuzhiyun 	struct spi_device *spi;
31*4882a593Smuzhiyun };
32*4882a593Smuzhiyun 
33*4882a593Smuzhiyun #define LCD_XRES		800
34*4882a593Smuzhiyun #define LCD_YRES		480
35*4882a593Smuzhiyun /*
36*4882a593Smuzhiyun  * NEC PIX Clock Ratings
37*4882a593Smuzhiyun  * MIN:21.8MHz TYP:23.8MHz MAX:25.7MHz
38*4882a593Smuzhiyun  */
39*4882a593Smuzhiyun #define LCD_PIXEL_CLOCK		23800000
40*4882a593Smuzhiyun 
41*4882a593Smuzhiyun static const struct {
42*4882a593Smuzhiyun 	unsigned char addr;
43*4882a593Smuzhiyun 	unsigned char dat;
44*4882a593Smuzhiyun } nec_8048_init_seq[] = {
45*4882a593Smuzhiyun 	{ 3, 0x01 }, { 0, 0x00 }, { 1, 0x01 }, { 4, 0x00 }, { 5, 0x14 },
46*4882a593Smuzhiyun 	{ 6, 0x24 }, { 16, 0xD7 }, { 17, 0x00 }, { 18, 0x00 }, { 19, 0x55 },
47*4882a593Smuzhiyun 	{ 20, 0x01 }, { 21, 0x70 }, { 22, 0x1E }, { 23, 0x25 },	{ 24, 0x25 },
48*4882a593Smuzhiyun 	{ 25, 0x02 }, { 26, 0x02 }, { 27, 0xA0 }, { 32, 0x2F }, { 33, 0x0F },
49*4882a593Smuzhiyun 	{ 34, 0x0F }, { 35, 0x0F }, { 36, 0x0F }, { 37, 0x0F },	{ 38, 0x0F },
50*4882a593Smuzhiyun 	{ 39, 0x00 }, { 40, 0x02 }, { 41, 0x02 }, { 42, 0x02 },	{ 43, 0x0F },
51*4882a593Smuzhiyun 	{ 44, 0x0F }, { 45, 0x0F }, { 46, 0x0F }, { 47, 0x0F },	{ 48, 0x0F },
52*4882a593Smuzhiyun 	{ 49, 0x0F }, { 50, 0x00 }, { 51, 0x02 }, { 52, 0x02 }, { 53, 0x02 },
53*4882a593Smuzhiyun 	{ 80, 0x0C }, { 83, 0x42 }, { 84, 0x42 }, { 85, 0x41 },	{ 86, 0x14 },
54*4882a593Smuzhiyun 	{ 89, 0x88 }, { 90, 0x01 }, { 91, 0x00 }, { 92, 0x02 },	{ 93, 0x0C },
55*4882a593Smuzhiyun 	{ 94, 0x1C }, { 95, 0x27 }, { 98, 0x49 }, { 99, 0x27 }, { 102, 0x76 },
56*4882a593Smuzhiyun 	{ 103, 0x27 }, { 112, 0x01 }, { 113, 0x0E }, { 114, 0x02 },
57*4882a593Smuzhiyun 	{ 115, 0x0C }, { 118, 0x0C }, { 121, 0x30 }, { 130, 0x00 },
58*4882a593Smuzhiyun 	{ 131, 0x00 }, { 132, 0xFC }, { 134, 0x00 }, { 136, 0x00 },
59*4882a593Smuzhiyun 	{ 138, 0x00 }, { 139, 0x00 }, { 140, 0x00 }, { 141, 0xFC },
60*4882a593Smuzhiyun 	{ 143, 0x00 }, { 145, 0x00 }, { 147, 0x00 }, { 148, 0x00 },
61*4882a593Smuzhiyun 	{ 149, 0x00 }, { 150, 0xFC }, { 152, 0x00 }, { 154, 0x00 },
62*4882a593Smuzhiyun 	{ 156, 0x00 }, { 157, 0x00 }, { 2, 0x00 },
63*4882a593Smuzhiyun };
64*4882a593Smuzhiyun 
65*4882a593Smuzhiyun static const struct omap_video_timings nec_8048_panel_timings = {
66*4882a593Smuzhiyun 	.x_res		= LCD_XRES,
67*4882a593Smuzhiyun 	.y_res		= LCD_YRES,
68*4882a593Smuzhiyun 	.pixelclock	= LCD_PIXEL_CLOCK,
69*4882a593Smuzhiyun 	.hfp		= 6,
70*4882a593Smuzhiyun 	.hsw		= 1,
71*4882a593Smuzhiyun 	.hbp		= 4,
72*4882a593Smuzhiyun 	.vfp		= 3,
73*4882a593Smuzhiyun 	.vsw		= 1,
74*4882a593Smuzhiyun 	.vbp		= 4,
75*4882a593Smuzhiyun 
76*4882a593Smuzhiyun 	.vsync_level	= OMAPDSS_SIG_ACTIVE_LOW,
77*4882a593Smuzhiyun 	.hsync_level	= OMAPDSS_SIG_ACTIVE_LOW,
78*4882a593Smuzhiyun 	.data_pclk_edge	= OMAPDSS_DRIVE_SIG_RISING_EDGE,
79*4882a593Smuzhiyun 	.de_level	= OMAPDSS_SIG_ACTIVE_HIGH,
80*4882a593Smuzhiyun 	.sync_pclk_edge	= OMAPDSS_DRIVE_SIG_RISING_EDGE,
81*4882a593Smuzhiyun };
82*4882a593Smuzhiyun 
83*4882a593Smuzhiyun #define to_panel_data(p) container_of(p, struct panel_drv_data, dssdev)
84*4882a593Smuzhiyun 
nec_8048_spi_send(struct spi_device * spi,unsigned char reg_addr,unsigned char reg_data)85*4882a593Smuzhiyun static int nec_8048_spi_send(struct spi_device *spi, unsigned char reg_addr,
86*4882a593Smuzhiyun 			unsigned char reg_data)
87*4882a593Smuzhiyun {
88*4882a593Smuzhiyun 	int ret = 0;
89*4882a593Smuzhiyun 	unsigned int cmd = 0, data = 0;
90*4882a593Smuzhiyun 
91*4882a593Smuzhiyun 	cmd = 0x0000 | reg_addr; /* register address write */
92*4882a593Smuzhiyun 	data = 0x0100 | reg_data; /* register data write */
93*4882a593Smuzhiyun 	data = (cmd << 16) | data;
94*4882a593Smuzhiyun 
95*4882a593Smuzhiyun 	ret = spi_write(spi, (unsigned char *)&data, 4);
96*4882a593Smuzhiyun 	if (ret)
97*4882a593Smuzhiyun 		pr_err("error in spi_write %x\n", data);
98*4882a593Smuzhiyun 
99*4882a593Smuzhiyun 	return ret;
100*4882a593Smuzhiyun }
101*4882a593Smuzhiyun 
init_nec_8048_wvga_lcd(struct spi_device * spi)102*4882a593Smuzhiyun static int init_nec_8048_wvga_lcd(struct spi_device *spi)
103*4882a593Smuzhiyun {
104*4882a593Smuzhiyun 	unsigned int i;
105*4882a593Smuzhiyun 	/* Initialization Sequence */
106*4882a593Smuzhiyun 	/* nec_8048_spi_send(spi, REG, VAL) */
107*4882a593Smuzhiyun 	for (i = 0; i < (ARRAY_SIZE(nec_8048_init_seq) - 1); i++)
108*4882a593Smuzhiyun 		nec_8048_spi_send(spi, nec_8048_init_seq[i].addr,
109*4882a593Smuzhiyun 				nec_8048_init_seq[i].dat);
110*4882a593Smuzhiyun 	udelay(20);
111*4882a593Smuzhiyun 	nec_8048_spi_send(spi, nec_8048_init_seq[i].addr,
112*4882a593Smuzhiyun 				nec_8048_init_seq[i].dat);
113*4882a593Smuzhiyun 	return 0;
114*4882a593Smuzhiyun }
115*4882a593Smuzhiyun 
nec_8048_connect(struct omap_dss_device * dssdev)116*4882a593Smuzhiyun static int nec_8048_connect(struct omap_dss_device *dssdev)
117*4882a593Smuzhiyun {
118*4882a593Smuzhiyun 	struct panel_drv_data *ddata = to_panel_data(dssdev);
119*4882a593Smuzhiyun 	struct omap_dss_device *in = ddata->in;
120*4882a593Smuzhiyun 	int r;
121*4882a593Smuzhiyun 
122*4882a593Smuzhiyun 	if (omapdss_device_is_connected(dssdev))
123*4882a593Smuzhiyun 		return 0;
124*4882a593Smuzhiyun 
125*4882a593Smuzhiyun 	r = in->ops.dpi->connect(in, dssdev);
126*4882a593Smuzhiyun 	if (r)
127*4882a593Smuzhiyun 		return r;
128*4882a593Smuzhiyun 
129*4882a593Smuzhiyun 	return 0;
130*4882a593Smuzhiyun }
131*4882a593Smuzhiyun 
nec_8048_disconnect(struct omap_dss_device * dssdev)132*4882a593Smuzhiyun static void nec_8048_disconnect(struct omap_dss_device *dssdev)
133*4882a593Smuzhiyun {
134*4882a593Smuzhiyun 	struct panel_drv_data *ddata = to_panel_data(dssdev);
135*4882a593Smuzhiyun 	struct omap_dss_device *in = ddata->in;
136*4882a593Smuzhiyun 
137*4882a593Smuzhiyun 	if (!omapdss_device_is_connected(dssdev))
138*4882a593Smuzhiyun 		return;
139*4882a593Smuzhiyun 
140*4882a593Smuzhiyun 	in->ops.dpi->disconnect(in, dssdev);
141*4882a593Smuzhiyun }
142*4882a593Smuzhiyun 
nec_8048_enable(struct omap_dss_device * dssdev)143*4882a593Smuzhiyun static int nec_8048_enable(struct omap_dss_device *dssdev)
144*4882a593Smuzhiyun {
145*4882a593Smuzhiyun 	struct panel_drv_data *ddata = to_panel_data(dssdev);
146*4882a593Smuzhiyun 	struct omap_dss_device *in = ddata->in;
147*4882a593Smuzhiyun 	int r;
148*4882a593Smuzhiyun 
149*4882a593Smuzhiyun 	if (!omapdss_device_is_connected(dssdev))
150*4882a593Smuzhiyun 		return -ENODEV;
151*4882a593Smuzhiyun 
152*4882a593Smuzhiyun 	if (omapdss_device_is_enabled(dssdev))
153*4882a593Smuzhiyun 		return 0;
154*4882a593Smuzhiyun 
155*4882a593Smuzhiyun 	if (ddata->data_lines)
156*4882a593Smuzhiyun 		in->ops.dpi->set_data_lines(in, ddata->data_lines);
157*4882a593Smuzhiyun 	in->ops.dpi->set_timings(in, &ddata->videomode);
158*4882a593Smuzhiyun 
159*4882a593Smuzhiyun 	r = in->ops.dpi->enable(in);
160*4882a593Smuzhiyun 	if (r)
161*4882a593Smuzhiyun 		return r;
162*4882a593Smuzhiyun 
163*4882a593Smuzhiyun 	if (gpio_is_valid(ddata->res_gpio))
164*4882a593Smuzhiyun 		gpio_set_value_cansleep(ddata->res_gpio, 1);
165*4882a593Smuzhiyun 
166*4882a593Smuzhiyun 	dssdev->state = OMAP_DSS_DISPLAY_ACTIVE;
167*4882a593Smuzhiyun 
168*4882a593Smuzhiyun 	return 0;
169*4882a593Smuzhiyun }
170*4882a593Smuzhiyun 
nec_8048_disable(struct omap_dss_device * dssdev)171*4882a593Smuzhiyun static void nec_8048_disable(struct omap_dss_device *dssdev)
172*4882a593Smuzhiyun {
173*4882a593Smuzhiyun 	struct panel_drv_data *ddata = to_panel_data(dssdev);
174*4882a593Smuzhiyun 	struct omap_dss_device *in = ddata->in;
175*4882a593Smuzhiyun 
176*4882a593Smuzhiyun 	if (!omapdss_device_is_enabled(dssdev))
177*4882a593Smuzhiyun 		return;
178*4882a593Smuzhiyun 
179*4882a593Smuzhiyun 	if (gpio_is_valid(ddata->res_gpio))
180*4882a593Smuzhiyun 		gpio_set_value_cansleep(ddata->res_gpio, 0);
181*4882a593Smuzhiyun 
182*4882a593Smuzhiyun 	in->ops.dpi->disable(in);
183*4882a593Smuzhiyun 
184*4882a593Smuzhiyun 	dssdev->state = OMAP_DSS_DISPLAY_DISABLED;
185*4882a593Smuzhiyun }
186*4882a593Smuzhiyun 
nec_8048_set_timings(struct omap_dss_device * dssdev,struct omap_video_timings * timings)187*4882a593Smuzhiyun static void nec_8048_set_timings(struct omap_dss_device *dssdev,
188*4882a593Smuzhiyun 		struct omap_video_timings *timings)
189*4882a593Smuzhiyun {
190*4882a593Smuzhiyun 	struct panel_drv_data *ddata = to_panel_data(dssdev);
191*4882a593Smuzhiyun 	struct omap_dss_device *in = ddata->in;
192*4882a593Smuzhiyun 
193*4882a593Smuzhiyun 	ddata->videomode = *timings;
194*4882a593Smuzhiyun 	dssdev->panel.timings = *timings;
195*4882a593Smuzhiyun 
196*4882a593Smuzhiyun 	in->ops.dpi->set_timings(in, timings);
197*4882a593Smuzhiyun }
198*4882a593Smuzhiyun 
nec_8048_get_timings(struct omap_dss_device * dssdev,struct omap_video_timings * timings)199*4882a593Smuzhiyun static void nec_8048_get_timings(struct omap_dss_device *dssdev,
200*4882a593Smuzhiyun 		struct omap_video_timings *timings)
201*4882a593Smuzhiyun {
202*4882a593Smuzhiyun 	struct panel_drv_data *ddata = to_panel_data(dssdev);
203*4882a593Smuzhiyun 
204*4882a593Smuzhiyun 	*timings = ddata->videomode;
205*4882a593Smuzhiyun }
206*4882a593Smuzhiyun 
nec_8048_check_timings(struct omap_dss_device * dssdev,struct omap_video_timings * timings)207*4882a593Smuzhiyun static int nec_8048_check_timings(struct omap_dss_device *dssdev,
208*4882a593Smuzhiyun 		struct omap_video_timings *timings)
209*4882a593Smuzhiyun {
210*4882a593Smuzhiyun 	struct panel_drv_data *ddata = to_panel_data(dssdev);
211*4882a593Smuzhiyun 	struct omap_dss_device *in = ddata->in;
212*4882a593Smuzhiyun 
213*4882a593Smuzhiyun 	return in->ops.dpi->check_timings(in, timings);
214*4882a593Smuzhiyun }
215*4882a593Smuzhiyun 
216*4882a593Smuzhiyun static struct omap_dss_driver nec_8048_ops = {
217*4882a593Smuzhiyun 	.connect	= nec_8048_connect,
218*4882a593Smuzhiyun 	.disconnect	= nec_8048_disconnect,
219*4882a593Smuzhiyun 
220*4882a593Smuzhiyun 	.enable		= nec_8048_enable,
221*4882a593Smuzhiyun 	.disable	= nec_8048_disable,
222*4882a593Smuzhiyun 
223*4882a593Smuzhiyun 	.set_timings	= nec_8048_set_timings,
224*4882a593Smuzhiyun 	.get_timings	= nec_8048_get_timings,
225*4882a593Smuzhiyun 	.check_timings	= nec_8048_check_timings,
226*4882a593Smuzhiyun 
227*4882a593Smuzhiyun 	.get_resolution	= omapdss_default_get_resolution,
228*4882a593Smuzhiyun };
229*4882a593Smuzhiyun 
230*4882a593Smuzhiyun 
nec_8048_probe_of(struct spi_device * spi)231*4882a593Smuzhiyun static int nec_8048_probe_of(struct spi_device *spi)
232*4882a593Smuzhiyun {
233*4882a593Smuzhiyun 	struct device_node *node = spi->dev.of_node;
234*4882a593Smuzhiyun 	struct panel_drv_data *ddata = dev_get_drvdata(&spi->dev);
235*4882a593Smuzhiyun 	struct omap_dss_device *in;
236*4882a593Smuzhiyun 	int gpio;
237*4882a593Smuzhiyun 
238*4882a593Smuzhiyun 	gpio = of_get_named_gpio(node, "reset-gpios", 0);
239*4882a593Smuzhiyun 	if (!gpio_is_valid(gpio)) {
240*4882a593Smuzhiyun 		dev_err(&spi->dev, "failed to parse enable gpio\n");
241*4882a593Smuzhiyun 		return gpio;
242*4882a593Smuzhiyun 	}
243*4882a593Smuzhiyun 	ddata->res_gpio = gpio;
244*4882a593Smuzhiyun 
245*4882a593Smuzhiyun 	/* XXX the panel spec doesn't mention any QVGA pin?? */
246*4882a593Smuzhiyun 	ddata->qvga_gpio = -ENOENT;
247*4882a593Smuzhiyun 
248*4882a593Smuzhiyun 	in = omapdss_of_find_source_for_first_ep(node);
249*4882a593Smuzhiyun 	if (IS_ERR(in)) {
250*4882a593Smuzhiyun 		dev_err(&spi->dev, "failed to find video source\n");
251*4882a593Smuzhiyun 		return PTR_ERR(in);
252*4882a593Smuzhiyun 	}
253*4882a593Smuzhiyun 
254*4882a593Smuzhiyun 	ddata->in = in;
255*4882a593Smuzhiyun 
256*4882a593Smuzhiyun 	return 0;
257*4882a593Smuzhiyun }
258*4882a593Smuzhiyun 
nec_8048_probe(struct spi_device * spi)259*4882a593Smuzhiyun static int nec_8048_probe(struct spi_device *spi)
260*4882a593Smuzhiyun {
261*4882a593Smuzhiyun 	struct panel_drv_data *ddata;
262*4882a593Smuzhiyun 	struct omap_dss_device *dssdev;
263*4882a593Smuzhiyun 	int r;
264*4882a593Smuzhiyun 
265*4882a593Smuzhiyun 	dev_dbg(&spi->dev, "%s\n", __func__);
266*4882a593Smuzhiyun 
267*4882a593Smuzhiyun 	if (!spi->dev.of_node)
268*4882a593Smuzhiyun 		return -ENODEV;
269*4882a593Smuzhiyun 
270*4882a593Smuzhiyun 	spi->mode = SPI_MODE_0;
271*4882a593Smuzhiyun 	spi->bits_per_word = 32;
272*4882a593Smuzhiyun 
273*4882a593Smuzhiyun 	r = spi_setup(spi);
274*4882a593Smuzhiyun 	if (r < 0) {
275*4882a593Smuzhiyun 		dev_err(&spi->dev, "spi_setup failed: %d\n", r);
276*4882a593Smuzhiyun 		return r;
277*4882a593Smuzhiyun 	}
278*4882a593Smuzhiyun 
279*4882a593Smuzhiyun 	init_nec_8048_wvga_lcd(spi);
280*4882a593Smuzhiyun 
281*4882a593Smuzhiyun 	ddata = devm_kzalloc(&spi->dev, sizeof(*ddata), GFP_KERNEL);
282*4882a593Smuzhiyun 	if (ddata == NULL)
283*4882a593Smuzhiyun 		return -ENOMEM;
284*4882a593Smuzhiyun 
285*4882a593Smuzhiyun 	dev_set_drvdata(&spi->dev, ddata);
286*4882a593Smuzhiyun 
287*4882a593Smuzhiyun 	ddata->spi = spi;
288*4882a593Smuzhiyun 
289*4882a593Smuzhiyun 	r = nec_8048_probe_of(spi);
290*4882a593Smuzhiyun 	if (r)
291*4882a593Smuzhiyun 		return r;
292*4882a593Smuzhiyun 
293*4882a593Smuzhiyun 	if (gpio_is_valid(ddata->qvga_gpio)) {
294*4882a593Smuzhiyun 		r = devm_gpio_request_one(&spi->dev, ddata->qvga_gpio,
295*4882a593Smuzhiyun 				GPIOF_OUT_INIT_HIGH, "lcd QVGA");
296*4882a593Smuzhiyun 		if (r)
297*4882a593Smuzhiyun 			goto err_gpio;
298*4882a593Smuzhiyun 	}
299*4882a593Smuzhiyun 
300*4882a593Smuzhiyun 	if (gpio_is_valid(ddata->res_gpio)) {
301*4882a593Smuzhiyun 		r = devm_gpio_request_one(&spi->dev, ddata->res_gpio,
302*4882a593Smuzhiyun 				GPIOF_OUT_INIT_LOW, "lcd RES");
303*4882a593Smuzhiyun 		if (r)
304*4882a593Smuzhiyun 			goto err_gpio;
305*4882a593Smuzhiyun 	}
306*4882a593Smuzhiyun 
307*4882a593Smuzhiyun 	ddata->videomode = nec_8048_panel_timings;
308*4882a593Smuzhiyun 
309*4882a593Smuzhiyun 	dssdev = &ddata->dssdev;
310*4882a593Smuzhiyun 	dssdev->dev = &spi->dev;
311*4882a593Smuzhiyun 	dssdev->driver = &nec_8048_ops;
312*4882a593Smuzhiyun 	dssdev->type = OMAP_DISPLAY_TYPE_DPI;
313*4882a593Smuzhiyun 	dssdev->owner = THIS_MODULE;
314*4882a593Smuzhiyun 	dssdev->panel.timings = ddata->videomode;
315*4882a593Smuzhiyun 
316*4882a593Smuzhiyun 	r = omapdss_register_display(dssdev);
317*4882a593Smuzhiyun 	if (r) {
318*4882a593Smuzhiyun 		dev_err(&spi->dev, "Failed to register panel\n");
319*4882a593Smuzhiyun 		goto err_reg;
320*4882a593Smuzhiyun 	}
321*4882a593Smuzhiyun 
322*4882a593Smuzhiyun 	return 0;
323*4882a593Smuzhiyun 
324*4882a593Smuzhiyun err_reg:
325*4882a593Smuzhiyun err_gpio:
326*4882a593Smuzhiyun 	omap_dss_put_device(ddata->in);
327*4882a593Smuzhiyun 	return r;
328*4882a593Smuzhiyun }
329*4882a593Smuzhiyun 
nec_8048_remove(struct spi_device * spi)330*4882a593Smuzhiyun static int nec_8048_remove(struct spi_device *spi)
331*4882a593Smuzhiyun {
332*4882a593Smuzhiyun 	struct panel_drv_data *ddata = dev_get_drvdata(&spi->dev);
333*4882a593Smuzhiyun 	struct omap_dss_device *dssdev = &ddata->dssdev;
334*4882a593Smuzhiyun 	struct omap_dss_device *in = ddata->in;
335*4882a593Smuzhiyun 
336*4882a593Smuzhiyun 	dev_dbg(&ddata->spi->dev, "%s\n", __func__);
337*4882a593Smuzhiyun 
338*4882a593Smuzhiyun 	omapdss_unregister_display(dssdev);
339*4882a593Smuzhiyun 
340*4882a593Smuzhiyun 	nec_8048_disable(dssdev);
341*4882a593Smuzhiyun 	nec_8048_disconnect(dssdev);
342*4882a593Smuzhiyun 
343*4882a593Smuzhiyun 	omap_dss_put_device(in);
344*4882a593Smuzhiyun 
345*4882a593Smuzhiyun 	return 0;
346*4882a593Smuzhiyun }
347*4882a593Smuzhiyun 
348*4882a593Smuzhiyun #ifdef CONFIG_PM_SLEEP
nec_8048_suspend(struct device * dev)349*4882a593Smuzhiyun static int nec_8048_suspend(struct device *dev)
350*4882a593Smuzhiyun {
351*4882a593Smuzhiyun 	struct spi_device *spi = to_spi_device(dev);
352*4882a593Smuzhiyun 
353*4882a593Smuzhiyun 	nec_8048_spi_send(spi, 2, 0x01);
354*4882a593Smuzhiyun 	mdelay(40);
355*4882a593Smuzhiyun 
356*4882a593Smuzhiyun 	return 0;
357*4882a593Smuzhiyun }
358*4882a593Smuzhiyun 
nec_8048_resume(struct device * dev)359*4882a593Smuzhiyun static int nec_8048_resume(struct device *dev)
360*4882a593Smuzhiyun {
361*4882a593Smuzhiyun 	struct spi_device *spi = to_spi_device(dev);
362*4882a593Smuzhiyun 
363*4882a593Smuzhiyun 	/* reinitialize the panel */
364*4882a593Smuzhiyun 	spi_setup(spi);
365*4882a593Smuzhiyun 	nec_8048_spi_send(spi, 2, 0x00);
366*4882a593Smuzhiyun 	init_nec_8048_wvga_lcd(spi);
367*4882a593Smuzhiyun 
368*4882a593Smuzhiyun 	return 0;
369*4882a593Smuzhiyun }
370*4882a593Smuzhiyun static SIMPLE_DEV_PM_OPS(nec_8048_pm_ops, nec_8048_suspend,
371*4882a593Smuzhiyun 		nec_8048_resume);
372*4882a593Smuzhiyun #define NEC_8048_PM_OPS (&nec_8048_pm_ops)
373*4882a593Smuzhiyun #else
374*4882a593Smuzhiyun #define NEC_8048_PM_OPS NULL
375*4882a593Smuzhiyun #endif
376*4882a593Smuzhiyun 
377*4882a593Smuzhiyun static const struct of_device_id nec_8048_of_match[] = {
378*4882a593Smuzhiyun 	{ .compatible = "omapdss,nec,nl8048hl11", },
379*4882a593Smuzhiyun 	{},
380*4882a593Smuzhiyun };
381*4882a593Smuzhiyun 
382*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, nec_8048_of_match);
383*4882a593Smuzhiyun 
384*4882a593Smuzhiyun static struct spi_driver nec_8048_driver = {
385*4882a593Smuzhiyun 	.driver = {
386*4882a593Smuzhiyun 		.name	= "panel-nec-nl8048hl11",
387*4882a593Smuzhiyun 		.pm	= NEC_8048_PM_OPS,
388*4882a593Smuzhiyun 		.of_match_table = nec_8048_of_match,
389*4882a593Smuzhiyun 		.suppress_bind_attrs = true,
390*4882a593Smuzhiyun 	},
391*4882a593Smuzhiyun 	.probe	= nec_8048_probe,
392*4882a593Smuzhiyun 	.remove	= nec_8048_remove,
393*4882a593Smuzhiyun };
394*4882a593Smuzhiyun 
395*4882a593Smuzhiyun module_spi_driver(nec_8048_driver);
396*4882a593Smuzhiyun 
397*4882a593Smuzhiyun MODULE_ALIAS("spi:nec,nl8048hl11");
398*4882a593Smuzhiyun MODULE_AUTHOR("Erik Gilling <konkers@android.com>");
399*4882a593Smuzhiyun MODULE_DESCRIPTION("NEC-NL8048HL11 Driver");
400*4882a593Smuzhiyun MODULE_LICENSE("GPL");
401