1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * linux/drivers/video/nvidia/nvidia-i2c.c - nVidia i2c
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * Copyright 2004 Antonino A. Daplas <adaplas @pol.net>
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * Based on rivafb-i2c.c
7*4882a593Smuzhiyun *
8*4882a593Smuzhiyun * This file is subject to the terms and conditions of the GNU General Public
9*4882a593Smuzhiyun * License. See the file COPYING in the main directory of this archive
10*4882a593Smuzhiyun * for more details.
11*4882a593Smuzhiyun */
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun #include <linux/module.h>
14*4882a593Smuzhiyun #include <linux/kernel.h>
15*4882a593Smuzhiyun #include <linux/delay.h>
16*4882a593Smuzhiyun #include <linux/gfp.h>
17*4882a593Smuzhiyun #include <linux/pci.h>
18*4882a593Smuzhiyun #include <linux/fb.h>
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun #include <asm/io.h>
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun #include "nv_type.h"
23*4882a593Smuzhiyun #include "nv_local.h"
24*4882a593Smuzhiyun #include "nv_proto.h"
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun #include "../edid.h"
27*4882a593Smuzhiyun
nvidia_gpio_setscl(void * data,int state)28*4882a593Smuzhiyun static void nvidia_gpio_setscl(void *data, int state)
29*4882a593Smuzhiyun {
30*4882a593Smuzhiyun struct nvidia_i2c_chan *chan = data;
31*4882a593Smuzhiyun struct nvidia_par *par = chan->par;
32*4882a593Smuzhiyun u32 val;
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun val = NVReadCrtc(par, chan->ddc_base + 1) & 0xf0;
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun if (state)
37*4882a593Smuzhiyun val |= 0x20;
38*4882a593Smuzhiyun else
39*4882a593Smuzhiyun val &= ~0x20;
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun NVWriteCrtc(par, chan->ddc_base + 1, val | 0x01);
42*4882a593Smuzhiyun }
43*4882a593Smuzhiyun
nvidia_gpio_setsda(void * data,int state)44*4882a593Smuzhiyun static void nvidia_gpio_setsda(void *data, int state)
45*4882a593Smuzhiyun {
46*4882a593Smuzhiyun struct nvidia_i2c_chan *chan = data;
47*4882a593Smuzhiyun struct nvidia_par *par = chan->par;
48*4882a593Smuzhiyun u32 val;
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun val = NVReadCrtc(par, chan->ddc_base + 1) & 0xf0;
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun if (state)
53*4882a593Smuzhiyun val |= 0x10;
54*4882a593Smuzhiyun else
55*4882a593Smuzhiyun val &= ~0x10;
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun NVWriteCrtc(par, chan->ddc_base + 1, val | 0x01);
58*4882a593Smuzhiyun }
59*4882a593Smuzhiyun
nvidia_gpio_getscl(void * data)60*4882a593Smuzhiyun static int nvidia_gpio_getscl(void *data)
61*4882a593Smuzhiyun {
62*4882a593Smuzhiyun struct nvidia_i2c_chan *chan = data;
63*4882a593Smuzhiyun struct nvidia_par *par = chan->par;
64*4882a593Smuzhiyun u32 val = 0;
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun if (NVReadCrtc(par, chan->ddc_base) & 0x04)
67*4882a593Smuzhiyun val = 1;
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun return val;
70*4882a593Smuzhiyun }
71*4882a593Smuzhiyun
nvidia_gpio_getsda(void * data)72*4882a593Smuzhiyun static int nvidia_gpio_getsda(void *data)
73*4882a593Smuzhiyun {
74*4882a593Smuzhiyun struct nvidia_i2c_chan *chan = data;
75*4882a593Smuzhiyun struct nvidia_par *par = chan->par;
76*4882a593Smuzhiyun u32 val = 0;
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun if (NVReadCrtc(par, chan->ddc_base) & 0x08)
79*4882a593Smuzhiyun val = 1;
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun return val;
82*4882a593Smuzhiyun }
83*4882a593Smuzhiyun
nvidia_setup_i2c_bus(struct nvidia_i2c_chan * chan,const char * name,unsigned int i2c_class)84*4882a593Smuzhiyun static int nvidia_setup_i2c_bus(struct nvidia_i2c_chan *chan, const char *name,
85*4882a593Smuzhiyun unsigned int i2c_class)
86*4882a593Smuzhiyun {
87*4882a593Smuzhiyun int rc;
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun strscpy(chan->adapter.name, name, sizeof(chan->adapter.name));
90*4882a593Smuzhiyun chan->adapter.owner = THIS_MODULE;
91*4882a593Smuzhiyun chan->adapter.class = i2c_class;
92*4882a593Smuzhiyun chan->adapter.algo_data = &chan->algo;
93*4882a593Smuzhiyun chan->adapter.dev.parent = &chan->par->pci_dev->dev;
94*4882a593Smuzhiyun chan->algo.setsda = nvidia_gpio_setsda;
95*4882a593Smuzhiyun chan->algo.setscl = nvidia_gpio_setscl;
96*4882a593Smuzhiyun chan->algo.getsda = nvidia_gpio_getsda;
97*4882a593Smuzhiyun chan->algo.getscl = nvidia_gpio_getscl;
98*4882a593Smuzhiyun chan->algo.udelay = 40;
99*4882a593Smuzhiyun chan->algo.timeout = msecs_to_jiffies(2);
100*4882a593Smuzhiyun chan->algo.data = chan;
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun i2c_set_adapdata(&chan->adapter, chan);
103*4882a593Smuzhiyun
104*4882a593Smuzhiyun /* Raise SCL and SDA */
105*4882a593Smuzhiyun nvidia_gpio_setsda(chan, 1);
106*4882a593Smuzhiyun nvidia_gpio_setscl(chan, 1);
107*4882a593Smuzhiyun udelay(20);
108*4882a593Smuzhiyun
109*4882a593Smuzhiyun rc = i2c_bit_add_bus(&chan->adapter);
110*4882a593Smuzhiyun if (rc == 0)
111*4882a593Smuzhiyun dev_dbg(&chan->par->pci_dev->dev,
112*4882a593Smuzhiyun "I2C bus %s registered.\n", name);
113*4882a593Smuzhiyun else {
114*4882a593Smuzhiyun dev_warn(&chan->par->pci_dev->dev,
115*4882a593Smuzhiyun "Failed to register I2C bus %s.\n", name);
116*4882a593Smuzhiyun chan->par = NULL;
117*4882a593Smuzhiyun }
118*4882a593Smuzhiyun
119*4882a593Smuzhiyun return rc;
120*4882a593Smuzhiyun }
121*4882a593Smuzhiyun
nvidia_create_i2c_busses(struct nvidia_par * par)122*4882a593Smuzhiyun void nvidia_create_i2c_busses(struct nvidia_par *par)
123*4882a593Smuzhiyun {
124*4882a593Smuzhiyun par->chan[0].par = par;
125*4882a593Smuzhiyun par->chan[1].par = par;
126*4882a593Smuzhiyun par->chan[2].par = par;
127*4882a593Smuzhiyun
128*4882a593Smuzhiyun par->chan[0].ddc_base = (par->reverse_i2c) ? 0x36 : 0x3e;
129*4882a593Smuzhiyun nvidia_setup_i2c_bus(&par->chan[0], "nvidia #0",
130*4882a593Smuzhiyun (par->reverse_i2c) ? I2C_CLASS_HWMON : 0);
131*4882a593Smuzhiyun
132*4882a593Smuzhiyun par->chan[1].ddc_base = (par->reverse_i2c) ? 0x3e : 0x36;
133*4882a593Smuzhiyun nvidia_setup_i2c_bus(&par->chan[1], "nvidia #1",
134*4882a593Smuzhiyun (par->reverse_i2c) ? 0 : I2C_CLASS_HWMON);
135*4882a593Smuzhiyun
136*4882a593Smuzhiyun par->chan[2].ddc_base = 0x50;
137*4882a593Smuzhiyun nvidia_setup_i2c_bus(&par->chan[2], "nvidia #2", 0);
138*4882a593Smuzhiyun }
139*4882a593Smuzhiyun
nvidia_delete_i2c_busses(struct nvidia_par * par)140*4882a593Smuzhiyun void nvidia_delete_i2c_busses(struct nvidia_par *par)
141*4882a593Smuzhiyun {
142*4882a593Smuzhiyun int i;
143*4882a593Smuzhiyun
144*4882a593Smuzhiyun for (i = 0; i < 3; i++) {
145*4882a593Smuzhiyun if (!par->chan[i].par)
146*4882a593Smuzhiyun continue;
147*4882a593Smuzhiyun i2c_del_adapter(&par->chan[i].adapter);
148*4882a593Smuzhiyun par->chan[i].par = NULL;
149*4882a593Smuzhiyun }
150*4882a593Smuzhiyun }
151*4882a593Smuzhiyun
nvidia_probe_i2c_connector(struct fb_info * info,int conn,u8 ** out_edid)152*4882a593Smuzhiyun int nvidia_probe_i2c_connector(struct fb_info *info, int conn, u8 **out_edid)
153*4882a593Smuzhiyun {
154*4882a593Smuzhiyun struct nvidia_par *par = info->par;
155*4882a593Smuzhiyun u8 *edid = NULL;
156*4882a593Smuzhiyun
157*4882a593Smuzhiyun if (par->chan[conn - 1].par)
158*4882a593Smuzhiyun edid = fb_ddc_read(&par->chan[conn - 1].adapter);
159*4882a593Smuzhiyun
160*4882a593Smuzhiyun if (!edid && conn == 1) {
161*4882a593Smuzhiyun /* try to get from firmware */
162*4882a593Smuzhiyun const u8 *e = fb_firmware_edid(info->device);
163*4882a593Smuzhiyun
164*4882a593Smuzhiyun if (e != NULL)
165*4882a593Smuzhiyun edid = kmemdup(e, EDID_LENGTH, GFP_KERNEL);
166*4882a593Smuzhiyun }
167*4882a593Smuzhiyun
168*4882a593Smuzhiyun *out_edid = edid;
169*4882a593Smuzhiyun
170*4882a593Smuzhiyun return (edid) ? 0 : 1;
171*4882a593Smuzhiyun }
172